diff --git a/pal/baremetal/target/RDN2/common/src/pal_bm_exerciser.c b/pal/baremetal/target/RDN2/common/src/pal_bm_exerciser.c index c412ba98..eda8ae97 100644 --- a/pal/baremetal/target/RDN2/common/src/pal_bm_exerciser.c +++ b/pal/baremetal/target/RDN2/common/src/pal_bm_exerciser.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2024, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -73,6 +73,7 @@ uint32_t pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, uint64_t Value1, uin uint64_t Base; uint64_t Ecam; uint32_t bdf; + uint32_t upper_range, lower_range; Base = pal_exerciser_get_ecsr_base(Bdf,0); Ecam = pal_exerciser_get_ecam(Bdf); @@ -86,8 +87,13 @@ uint32_t pal_exerciser_set_param(EXERCISER_PARAM_TYPE Type, uint64_t Value1, uin return 0; case DMA_ATTRIBUTES: - pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2 - pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3 + /* writing into the DMA Control Register 2 */ + lower_range = (uint32_t)(Value1 & 0xFFFFFFFF); + upper_range = (uint32_t)((Value1 >> 32) & 0xFFFFFFFF); + pal_mmio_write(Base + DMA_BUS_ADDR, lower_range); + pal_mmio_write(Base + DMA_BUS_ADDR + 4, upper_range); + /* writing into the DMA Control Register 3 */ + pal_mmio_write(Base + DMA_LEN, (uint32_t)Value2); return 0; case P2P_ATTRIBUTES: @@ -242,6 +248,7 @@ uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, uint64_t *Value1, ui uint32_t addr_high = 0; uint32_t data_low = 0; uint32_t data_high = 0; + uint32_t upper_range, lower_range; Base = pal_exerciser_get_ecsr_base(Bdf,0); switch (Type) { @@ -252,8 +259,12 @@ uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, uint64_t *Value1, ui *Value1 = pal_mmio_read(Base + INTXCTL); return pal_mmio_read(Base + INTXCTL) | MASK_BIT ; case DMA_ATTRIBUTES: - *Value1 = pal_mmio_read(Base + DMA_BUS_ADDR); // Reading the data from DMA Control Register 2 - *Value2 = pal_mmio_read(Base + DMA_LEN); // Reading the data from DMA Control Register 3 + /* Reading the data from DMA Control Register 2 */ + lower_range = pal_mmio_read(Base + DMA_BUS_ADDR); + upper_range = pal_mmio_read(Base + DMA_BUS_ADDR + 4); + *Value1 = ((uint64_t)upper_range << 32) | lower_range; + /* Reading the data from DMA Control Register 3 */ + *Value2 = pal_mmio_read(Base + DMA_LEN); Temp = pal_mmio_read(Base + DMASTATUS); Status = Temp & MASK_BIT;// returning the DMA status return Status; @@ -266,7 +277,9 @@ uint32_t pal_exerciser_get_param(EXERCISER_PARAM_TYPE Type, uint64_t *Value1, ui *Value1 = pal_mmio_read(Base + MSICTL); return pal_mmio_read(Base + MSICTL) | MASK_BIT; case ATS_RES_ATTRIBUTES: - *Value1 = pal_mmio_read(Base + ATS_ADDR); + lower_range = pal_mmio_read(Base + ATS_ADDR); + upper_range = pal_mmio_read(Base + ATS_ADDR + 4); + *Value1 = ((uint64_t)upper_range << 32) | lower_range; return 0; case CFG_TXN_ATTRIBUTES: case TRANSACTION_TYPE: @@ -348,6 +361,7 @@ uint32_t pal_exerciser_ops(EXERCISER_OPS Ops, uint64_t Param, uint32_t Bdf) uint64_t Ecam; uint32_t CapabilityOffset = 0; uint32_t data; + uint32_t upper_range, lower_range; Base = pal_exerciser_get_ecsr_base(Bdf,0); Ecam = pal_exerciser_get_ecam(Bdf); // Getting the ECAM address @@ -423,7 +437,10 @@ uint32_t pal_exerciser_ops(EXERCISER_OPS Ops, uint64_t Param, uint32_t Bdf) return 0; case ATS_TXN_REQ: - pal_mmio_write(Base + DMA_BUS_ADDR, Param); + lower_range = (uint32_t)(Param & 0xFFFFFFFF); + upper_range = (uint32_t)((Param >> 32) & 0xFFFFFFFF); + pal_mmio_write(Base + DMA_BUS_ADDR, lower_range); + pal_mmio_write(Base + DMA_BUS_ADDR + 4, upper_range); pal_mmio_write(Base + ATSCTL, ATS_TRIGGER); return !(pal_mmio_read(Base + ATSCTL) & ATS_STATUS); diff --git a/pal/uefi_acpi/common/src/pal_exerciser.c b/pal/uefi_acpi/common/src/pal_exerciser.c index 2f1cd34e..da30b92d 100644 --- a/pal/uefi_acpi/common/src/pal_exerciser.c +++ b/pal/uefi_acpi/common/src/pal_exerciser.c @@ -237,6 +237,7 @@ UINT32 pal_exerciser_set_param ( UINT64 Base; UINT64 Ecam; UINT32 bdf; + UINT32 Lower_Range, Upper_Range; Base = pal_exerciser_get_ecsr_base(Bdf,0); Ecam = pal_pcie_get_mcfg_ecam(Bdf); // Getting the ECAM address @@ -250,8 +251,14 @@ UINT32 pal_exerciser_set_param ( return 0; case DMA_ATTRIBUTES: - pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2 - pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3 + /* writing into the DMA Control Register 2 */ + Lower_Range = (UINT32)(Value1 & 0xFFFFFFFF); + Upper_Range = (UINT32)((Value1 >> 32) & 0xFFFFFFFF); + pal_mmio_write(Base + DMA_BUS_ADDR, Lower_Range); + pal_mmio_write(Base + DMA_BUS_ADDR + 4, Upper_Range); + + /* writing into the DMA Control Register 3 */ + pal_mmio_write(Base + DMA_LEN, (UINT32)Value2); return 0; case P2P_ATTRIBUTES: @@ -375,6 +382,7 @@ pal_exerciser_get_param ( UINT32 addr_high = 0; UINT32 data_low = 0; UINT32 data_high = 0; + UINT32 Upper_Range, Lower_Range; Base = pal_exerciser_get_ecsr_base(Bdf,0); switch (Type) { @@ -385,8 +393,12 @@ pal_exerciser_get_param ( *Value1 = pal_mmio_read(Base + INTXCTL); return pal_mmio_read(Base + INTXCTL) | MASK_BIT ; case DMA_ATTRIBUTES: - *Value1 = pal_mmio_read(Base + DMA_BUS_ADDR); // Reading the data from DMA Control Register 2 - *Value2 = pal_mmio_read(Base + DMA_LEN); // Reading the data from DMA Control Register 3 + /* Reading the data from DMA Control Register 2 */ + Lower_Range = pal_mmio_read(Base + DMA_BUS_ADDR); + Upper_Range = pal_mmio_read(Base + DMA_BUS_ADDR + 4); + *Value1 = ((UINT64)Upper_Range << 32) | Lower_Range; + /* Reading the data from DMA Control Register 3 */ + *Value2 = pal_mmio_read(Base + DMA_LEN); Temp = pal_mmio_read(Base + DMASTATUS); Status = Temp & MASK_BIT;// returning the DMA status return Status; @@ -399,7 +411,9 @@ pal_exerciser_get_param ( *Value1 = pal_mmio_read(Base + MSICTL); return pal_mmio_read(Base + MSICTL) | MASK_BIT; case ATS_RES_ATTRIBUTES: - *Value1 = pal_mmio_read(Base + ATS_ADDR); + Lower_Range = pal_mmio_read(Base + ATS_ADDR); + Upper_Range = pal_mmio_read(Base + ATS_ADDR + 4); + *Value1 = ((UINT64)Upper_Range << 32) | Lower_Range; return 0; case CFG_TXN_ATTRIBUTES: case TRANSACTION_TYPE: @@ -497,6 +511,7 @@ pal_exerciser_ops ( UINT64 Ecam; UINT32 CapabilityOffset = 0; UINT32 data; + UINT32 Upper_Range, Lower_Range; Base = pal_exerciser_get_ecsr_base(Bdf,0); Ecam = pal_pcie_get_mcfg_ecam(Bdf); // Getting the ECAM address @@ -571,7 +586,10 @@ pal_exerciser_ops ( return 0; case ATS_TXN_REQ: - pal_mmio_write(Base + DMA_BUS_ADDR, Param); + Lower_Range = (UINT32)(Param & 0xFFFFFFFF); + Upper_Range = (UINT32)((Param >> 32) & 0xFFFFFFFF); + pal_mmio_write(Base + DMA_BUS_ADDR, Lower_Range); + pal_mmio_write(Base + DMA_BUS_ADDR + 4, Upper_Range); pal_mmio_write(Base + ATSCTL, ATS_TRIGGER); return !(pal_mmio_read(Base + ATSCTL) & ATS_STATUS); diff --git a/pal/uefi_dt/bsa/src/pal_exerciser.c b/pal/uefi_dt/bsa/src/pal_exerciser.c index bd5ea685..2753a501 100644 --- a/pal/uefi_dt/bsa/src/pal_exerciser.c +++ b/pal/uefi_dt/bsa/src/pal_exerciser.c @@ -166,7 +166,7 @@ pal_exerciser_start_dma_direction ( /** @brief This function finds the PCI capability and return 0 if it finds. - @param ID PCI capability IF + @param ID PCI capability IF @param Bdf BDF value for the device @param Value 1 PCIE capability 0 PCI capability @param Offset capability offset @@ -235,6 +235,7 @@ UINT32 pal_exerciser_set_param ( { UINT32 Data; UINT64 Base; + UINT32 Lower_Range, Upper_Range; Base = pal_exerciser_get_ecsr_base(Bdf,0); switch (Type) { @@ -246,8 +247,14 @@ UINT32 pal_exerciser_set_param ( return 0; case DMA_ATTRIBUTES: - pal_mmio_write(Base + DMA_BUS_ADDR,Value1);// wrting into the DMA Control Register 2 - pal_mmio_write(Base + DMA_LEN,Value2);// writing into the DMA Control Register 3 + /* writing into the DMA Control Register 2 */ + Lower_Range = (UINT32)(Value1 & 0xFFFFFFFF); + Upper_Range = (UINT32)((Value1 >> 32) & 0xFFFFFFFF); + pal_mmio_write(Base + DMA_BUS_ADDR, Lower_Range); + pal_mmio_write(Base + DMA_BUS_ADDR + 4, Upper_Range); + + /* writing into the DMA Control Register 3 */ + pal_mmio_write(Base + DMA_LEN, (UINT32)Value2); return 0; case P2P_ATTRIBUTES: @@ -330,6 +337,7 @@ pal_exerciser_get_param ( UINT32 Status; UINT32 Temp; UINT64 Base; + UINT32 Upper_Range, Lower_Range; Base = pal_exerciser_get_ecsr_base(Bdf,0); switch (Type) { @@ -340,8 +348,12 @@ pal_exerciser_get_param ( *Value1 = pal_mmio_read(Base + INTXCTL); return pal_mmio_read(Base + INTXCTL) | MASK_BIT ; case DMA_ATTRIBUTES: - *Value1 = pal_mmio_read(Base + DMA_BUS_ADDR); // Reading the data from DMA Control Register 2 - *Value2 = pal_mmio_read(Base + DMA_LEN); // Reading the data from DMA Control Register 3 + /* Reading the data from DMA Control Register 2 */ + Lower_Range = pal_mmio_read(Base + DMA_BUS_ADDR); + Upper_Range = pal_mmio_read(Base + DMA_BUS_ADDR + 4); + *Value1 = ((UINT64)Upper_Range << 32) | Lower_Range; + /* Reading the data from DMA Control Register 3 */ + *Value2 = pal_mmio_read(Base + DMA_LEN); Temp = pal_mmio_read(Base + DMASTATUS); Status = Temp & MASK_BIT;// returning the DMA status return Status; @@ -354,7 +366,9 @@ pal_exerciser_get_param ( *Value1 = pal_mmio_read(Base + MSICTL); return pal_mmio_read(Base + MSICTL) | MASK_BIT; case ATS_RES_ATTRIBUTES: - *Value1 = pal_mmio_read(Base + ATS_ADDR); + Lower_Range = pal_mmio_read(Base + ATS_ADDR); + Upper_Range = pal_mmio_read(Base + ATS_ADDR + 4); + *Value1 = ((UINT64)Upper_Range << 32) | Lower_Range; return 0; default: return 1; @@ -413,6 +427,7 @@ pal_exerciser_ops ( UINT64 Ecam; UINT32 CapabilityOffset; UINT32 data; + UINT32 Upper_Range, Lower_Range; Base = pal_exerciser_get_ecsr_base(Bdf,0); Ecam = pal_pcie_get_mcfg_ecam(Bdf); // Getting the ECAM address @@ -487,7 +502,10 @@ pal_exerciser_ops ( return 0; case ATS_TXN_REQ: - pal_mmio_write(Base + DMA_BUS_ADDR, Param); + Lower_Range = (UINT32)(Param & 0xFFFFFFFF); + Upper_Range = (UINT32)((Param >> 32) & 0xFFFFFFFF); + pal_mmio_write(Base + DMA_BUS_ADDR, Lower_Range); + pal_mmio_write(Base + DMA_BUS_ADDR + 4, Upper_Range); pal_mmio_write(Base + ATSCTL, ATS_TRIGGER); return !(pal_mmio_read(Base + ATSCTL) & ATS_STATUS); diff --git a/test_pool/exerciser/operating_system/test_os_e007.c b/test_pool/exerciser/operating_system/test_os_e007.c index 318ce098..8055f111 100644 --- a/test_pool/exerciser/operating_system/test_os_e007.c +++ b/test_pool/exerciser/operating_system/test_os_e007.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2018-2021,2023-2024, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2018-2021,2023-2025, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -71,11 +71,11 @@ uint32_t test_sequence2(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t ins val_pe_cache_clean_invalidate_range((uint64_t)dram_buf2_virt, (uint64_t)dma_len); /* Perform DMA OUT to copy contents of dram_buf2 to exerciser memory */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_phys, dma_len, instance); + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf2_phys, (uint64_t)dma_len, instance); val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); /* Perform DMA IN to copy content back from exerciser memory to dram_buf1 */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance); + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, (uint64_t)dma_len, instance); val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance); /* Invalidate dram_buf1 and dram_buf2 contents present in CPU caches */ @@ -110,11 +110,11 @@ uint32_t test_sequence1(void *dram_buf1_virt, void *dram_buf1_phys, uint32_t ins val_memory_set(dram_buf1_virt, dma_len, NEW_DATA); /* Perform DMA OUT to copy contents of dram_buf1 to exerciser memory */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance); + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, (uint64_t)dma_len, instance); val_exerciser_ops(START_DMA, EDMA_TO_DEVICE, instance); /* Perform DMA IN to copy the content from exerciser memory to dram_buf1 */ - val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, dma_len, instance); + val_exerciser_set_param(DMA_ATTRIBUTES, (uint64_t)dram_buf1_phys, (uint64_t)dma_len, instance); val_exerciser_ops(START_DMA, EDMA_FROM_DEVICE, instance); /* Write dram_buf2 with NEW_DATA to compare dram_buf1 content */