From 5730b43fd878e05875864e739e3b163bee469502 Mon Sep 17 00:00:00 2001 From: Ashish Singhal Date: Sun, 21 Dec 2025 22:16:55 -0700 Subject: [PATCH 1/2] feat(pal): Enable MMU and caches on secondary PEs - Capture primary PE's MMU configuration during PE info table creation - Secondary PEs now enable MMU and caches using primary PE's configuration - Disable MMU and caches before PSCI CPU_OFF on secondary PEs - This ensures consistent memory behavior across all PEs during test execution Signed-off-by: Ashish Singhal --- pal/uefi_acpi/include/pal_uefi.h | 13 +++ pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S | 91 ++++++++++++++++++++ pal/uefi_acpi/src/pal_pe.c | 77 +++++++++++++++++ pal/uefi_dt/include/pal_uefi.h | 13 +++ pal/uefi_dt/src/AArch64/ModuleEntryPoint.S | 91 ++++++++++++++++++++ pal/uefi_dt/src/pal_pe.c | 77 +++++++++++++++++ val/include/pal_interface.h | 14 +++ val/src/AArch64/PeRegSysSupport.S | 65 ++++++++++++++ val/src/acs_pe_infra.c | 1 + 9 files changed, 442 insertions(+) diff --git a/pal/uefi_acpi/include/pal_uefi.h b/pal/uefi_acpi/include/pal_uefi.h index 34bf132e..a8739043 100644 --- a/pal/uefi_acpi/include/pal_uefi.h +++ b/pal/uefi_acpi/include/pal_uefi.h @@ -130,6 +130,19 @@ typedef struct { PE_INFO_ENTRY pe_info[]; }PE_INFO_TABLE; +/** + @brief MMU configuration structure for secondary PE initialization + This structure holds the primary PE's MMU configuration which + is used to enable MMU/caches on secondary PEs. +**/ +typedef struct { + UINT64 ttbr0; ///< Translation Table Base Register 0 + UINT64 tcr; ///< Translation Control Register + UINT64 mair; ///< Memory Attribute Indirection Register + UINT64 sctlr; ///< System Control Register + UINT32 current_el; ///< Current Exception Level (1 or 2) +} PE_MMU_CONFIG; + /** @brief Instance of smbios type 4 processor info **/ diff --git a/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S b/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S index 1be354a3..ee6e1189 100644 --- a/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S +++ b/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S @@ -22,12 +22,99 @@ GCC_ASM_IMPORT(ArmReadMpidr) GCC_ASM_IMPORT(PalGetSecondaryStackBase) GCC_ASM_IMPORT(PalGetMaxMpidr) +GCC_ASM_IMPORT(PalGetMmuConfigAddr) GCC_ASM_EXPORT(ModuleEntryPoint) StartupAddr: .8byte ASM_PFX(val_test_entry) ASM_PFX(StackSize): .8byte 0x100 +// PE_MMU_CONFIG structure offsets +.equ MMU_CFG_TTBR0, 0 +.equ MMU_CFG_TCR, 8 +.equ MMU_CFG_MAIR, 16 +.equ MMU_CFG_SCTLR, 24 +.equ MMU_CFG_EL, 32 + +// SCTLR bits +.equ SCTLR_M_BIT, (1 << 0) // MMU enable +.equ SCTLR_C_BIT, (1 << 2) // Data cache enable +.equ SCTLR_I_BIT, (1 << 12) // Instruction cache enable + ASM_PFX(ModuleEntryPoint): + // + // Enable MMU and caches using primary PE's configuration + // +_EnableMmu: + // Get the MMU configuration address from primary PE + // Note: This is a C function call, but we haven't set up stack yet + // so we use a special calling convention (just branch and link) + adr x9, MmuConfigAddr + ldr x9, [x9] + blr x9 + + // x0 now contains the address of PE_MMU_CONFIG structure + mov x11, x0 // Save config address in x11 + + // Load all config values from the structure + ldr x12, [x11, #MMU_CFG_TTBR0] // TTBR0 + ldr x13, [x11, #MMU_CFG_TCR] // TCR + ldr x14, [x11, #MMU_CFG_MAIR] // MAIR + ldr x15, [x11, #MMU_CFG_SCTLR] // SCTLR + ldr w16, [x11, #MMU_CFG_EL] // Current EL (32-bit) + + // Determine current exception level + mrs x17, CurrentEL + lsr x17, x17, 2 + and x17, x17, 0x3 + + // Check if we're at EL2 + cmp x17, #2 + b.eq _SetupMmuEl2 + +_SetupMmuEl1: + // Invalidate TLB for EL1 + tlbi vmalle1 + dsb sy + isb + + // Set MAIR, TCR, TTBR0 for EL1 + msr mair_el1, x14 + isb + msr tcr_el1, x13 + isb + msr ttbr0_el1, x12 + isb + + // Enable MMU and caches for EL1 + // Use the same SCTLR value as primary PE (which has M, C, I bits set) + msr sctlr_el1, x15 + isb + b _MmuEnabled + +_SetupMmuEl2: + // Invalidate TLB for EL2 + tlbi alle2 + dsb sy + isb + + // Set MAIR, TCR, TTBR0 for EL2 + msr mair_el2, x14 + isb + msr tcr_el2, x13 + isb + msr ttbr0_el2, x12 + isb + + // Enable MMU and caches for EL2 + // Use the same SCTLR value as primary PE (which has M, C, I bits set) + msr sctlr_el2, x15 + isb + +_MmuEnabled: + // + // MMU and caches are now enabled, proceed with original entry code + // + // Get ID of this CPU in Multicore system bl ASM_PFX(ArmReadMpidr) // Keep a copy of the MpId register value @@ -80,3 +167,7 @@ _PrepareArguments: _NeverReturn: b _NeverReturn + +// Function pointer for PalGetMmuConfigAddr +.align 3 +MmuConfigAddr: .8byte ASM_PFX(PalGetMmuConfigAddr) diff --git a/pal/uefi_acpi/src/pal_pe.c b/pal/uefi_acpi/src/pal_pe.c index a5ad76cb..55ab63c5 100644 --- a/pal/uefi_acpi/src/pal_pe.c +++ b/pal/uefi_acpi/src/pal_pe.c @@ -33,6 +33,24 @@ UINT64 gMpidrMax; static UINT32 g_num_pe; extern INT32 gPsciConduit; +/** + Global MMU configuration structure for secondary PE initialization. + This is populated by the primary PE and used by secondary PEs to + enable MMU/caches with the same page table configuration. +**/ +static PE_MMU_CONFIG gMmuConfig __attribute__((aligned(64))); + +/* External assembly functions for reading MMU registers */ +UINT64 AA64ReadCurrentEL(VOID); +UINT64 AA64ReadTtbr0El1(VOID); +UINT64 AA64ReadTtbr0El2(VOID); +UINT64 AA64ReadTcr1(VOID); +UINT64 AA64ReadTcr2(VOID); +UINT64 AA64ReadMair1(VOID); +UINT64 AA64ReadMair2(VOID); +UINT64 AA64ReadSctlr1(VOID); +UINT64 AA64ReadSctlr2(VOID); + #define MAX_NUM_OF_SMBIOS_SLOTS_SUPPORTED 1024 #define SIZE_STACK_SECONDARY_PE 0x100 //256 bytes per core #define UPDATE_AFF_MAX(src,dest,mask) ((dest & mask) > (src & mask) ? (dest & mask) : (src & mask)) @@ -204,6 +222,62 @@ PalGetMaxMpidr() return gMpidrMax; } +/** + @brief Captures the primary PE's MMU configuration for use by secondary PEs. + This function reads TTBR0, TCR, MAIR, and SCTLR from the current EL + and stores them in a global structure that secondary PEs can access. + + @param None + @return None +**/ +STATIC +VOID +PalCaptureMmuConfig(VOID) +{ + UINT64 CurrentEl; + + /* Read current exception level */ + CurrentEl = (AA64ReadCurrentEL() >> 2) & 0x3; + gMmuConfig.current_el = (UINT32)CurrentEl; + + /* Read MMU configuration registers based on current EL */ + if (CurrentEl == 2) { + gMmuConfig.ttbr0 = AA64ReadTtbr0El2(); + gMmuConfig.tcr = AA64ReadTcr2(); + gMmuConfig.mair = AA64ReadMair2(); + gMmuConfig.sctlr = AA64ReadSctlr2(); + } else { + /* Assume EL1 */ + gMmuConfig.ttbr0 = AA64ReadTtbr0El1(); + gMmuConfig.tcr = AA64ReadTcr1(); + gMmuConfig.mair = AA64ReadMair1(); + gMmuConfig.sctlr = AA64ReadSctlr1(); + } + + acs_print(ACS_PRINT_INFO, L" MMU Config captured at EL%d\n", gMmuConfig.current_el); + acs_print(ACS_PRINT_DEBUG, L" TTBR0: 0x%lx\n", gMmuConfig.ttbr0); + acs_print(ACS_PRINT_DEBUG, L" TCR: 0x%lx\n", gMmuConfig.tcr); + acs_print(ACS_PRINT_DEBUG, L" MAIR: 0x%lx\n", gMmuConfig.mair); + acs_print(ACS_PRINT_DEBUG, L" SCTLR: 0x%lx\n", gMmuConfig.sctlr); + + /* Clean cache to ensure secondary PEs see the config */ + pal_pe_data_cache_ops_by_va((UINT64)&gMmuConfig, CLEAN_AND_INVALIDATE); +} + +/** + @brief Returns the address of the MMU configuration structure. + This function is called by secondary PE entry code to get + the primary PE's MMU configuration. + + @param None + @return Address of PE_MMU_CONFIG structure +**/ +UINT64 +PalGetMmuConfigAddr(VOID) +{ + return (UINT64)&gMmuConfig; +} + /** @brief Allocate memory region for secondary PE stack use. SIZE of stack for each PE is a #define @@ -354,6 +428,9 @@ pal_pe_create_info_table(PE_INFO_TABLE *PeTable) pal_pe_data_cache_ops_by_va((UINT64)&gMpidrMax, CLEAN_AND_INVALIDATE); PalAllocateSecondaryStack(gMpidrMax); + /* Capture primary PE's MMU configuration for secondary PE initialization */ + PalCaptureMmuConfig(); + } /** diff --git a/pal/uefi_dt/include/pal_uefi.h b/pal/uefi_dt/include/pal_uefi.h index 4f0c84da..a2040b35 100644 --- a/pal/uefi_dt/include/pal_uefi.h +++ b/pal/uefi_dt/include/pal_uefi.h @@ -118,6 +118,19 @@ typedef struct { PE_INFO_ENTRY pe_info[]; }PE_INFO_TABLE; +/** + @brief MMU configuration structure for secondary PE initialization + This structure holds the primary PE's MMU configuration which + is used to enable MMU/caches on secondary PEs. +**/ +typedef struct { + UINT64 ttbr0; ///< Translation Table Base Register 0 + UINT64 tcr; ///< Translation Control Register + UINT64 mair; ///< Memory Attribute Indirection Register + UINT64 sctlr; ///< System Control Register + UINT32 current_el; ///< Current Exception Level (1 or 2) +} PE_MMU_CONFIG; + /** @brief Instance of smbios type 4 processor info **/ diff --git a/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S b/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S index 1be354a3..ee6e1189 100644 --- a/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S +++ b/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S @@ -22,12 +22,99 @@ GCC_ASM_IMPORT(ArmReadMpidr) GCC_ASM_IMPORT(PalGetSecondaryStackBase) GCC_ASM_IMPORT(PalGetMaxMpidr) +GCC_ASM_IMPORT(PalGetMmuConfigAddr) GCC_ASM_EXPORT(ModuleEntryPoint) StartupAddr: .8byte ASM_PFX(val_test_entry) ASM_PFX(StackSize): .8byte 0x100 +// PE_MMU_CONFIG structure offsets +.equ MMU_CFG_TTBR0, 0 +.equ MMU_CFG_TCR, 8 +.equ MMU_CFG_MAIR, 16 +.equ MMU_CFG_SCTLR, 24 +.equ MMU_CFG_EL, 32 + +// SCTLR bits +.equ SCTLR_M_BIT, (1 << 0) // MMU enable +.equ SCTLR_C_BIT, (1 << 2) // Data cache enable +.equ SCTLR_I_BIT, (1 << 12) // Instruction cache enable + ASM_PFX(ModuleEntryPoint): + // + // Enable MMU and caches using primary PE's configuration + // +_EnableMmu: + // Get the MMU configuration address from primary PE + // Note: This is a C function call, but we haven't set up stack yet + // so we use a special calling convention (just branch and link) + adr x9, MmuConfigAddr + ldr x9, [x9] + blr x9 + + // x0 now contains the address of PE_MMU_CONFIG structure + mov x11, x0 // Save config address in x11 + + // Load all config values from the structure + ldr x12, [x11, #MMU_CFG_TTBR0] // TTBR0 + ldr x13, [x11, #MMU_CFG_TCR] // TCR + ldr x14, [x11, #MMU_CFG_MAIR] // MAIR + ldr x15, [x11, #MMU_CFG_SCTLR] // SCTLR + ldr w16, [x11, #MMU_CFG_EL] // Current EL (32-bit) + + // Determine current exception level + mrs x17, CurrentEL + lsr x17, x17, 2 + and x17, x17, 0x3 + + // Check if we're at EL2 + cmp x17, #2 + b.eq _SetupMmuEl2 + +_SetupMmuEl1: + // Invalidate TLB for EL1 + tlbi vmalle1 + dsb sy + isb + + // Set MAIR, TCR, TTBR0 for EL1 + msr mair_el1, x14 + isb + msr tcr_el1, x13 + isb + msr ttbr0_el1, x12 + isb + + // Enable MMU and caches for EL1 + // Use the same SCTLR value as primary PE (which has M, C, I bits set) + msr sctlr_el1, x15 + isb + b _MmuEnabled + +_SetupMmuEl2: + // Invalidate TLB for EL2 + tlbi alle2 + dsb sy + isb + + // Set MAIR, TCR, TTBR0 for EL2 + msr mair_el2, x14 + isb + msr tcr_el2, x13 + isb + msr ttbr0_el2, x12 + isb + + // Enable MMU and caches for EL2 + // Use the same SCTLR value as primary PE (which has M, C, I bits set) + msr sctlr_el2, x15 + isb + +_MmuEnabled: + // + // MMU and caches are now enabled, proceed with original entry code + // + // Get ID of this CPU in Multicore system bl ASM_PFX(ArmReadMpidr) // Keep a copy of the MpId register value @@ -80,3 +167,7 @@ _PrepareArguments: _NeverReturn: b _NeverReturn + +// Function pointer for PalGetMmuConfigAddr +.align 3 +MmuConfigAddr: .8byte ASM_PFX(PalGetMmuConfigAddr) diff --git a/pal/uefi_dt/src/pal_pe.c b/pal/uefi_dt/src/pal_pe.c index b2476baf..8f8f9a21 100644 --- a/pal/uefi_dt/src/pal_pe.c +++ b/pal/uefi_dt/src/pal_pe.c @@ -37,6 +37,24 @@ extern INT32 gPsciConduit; UINT32 pal_strncmp(CHAR8 *str1, CHAR8 *str2, UINT32 len); +/** + Global MMU configuration structure for secondary PE initialization. + This is populated by the primary PE and used by secondary PEs to + enable MMU/caches with the same page table configuration. +**/ +static PE_MMU_CONFIG gMmuConfig __attribute__((aligned(64))); + +/* External assembly functions for reading MMU registers */ +UINT64 AA64ReadCurrentEL(VOID); +UINT64 AA64ReadTtbr0El1(VOID); +UINT64 AA64ReadTtbr0El2(VOID); +UINT64 AA64ReadTcr1(VOID); +UINT64 AA64ReadTcr2(VOID); +UINT64 AA64ReadMair1(VOID); +UINT64 AA64ReadMair2(VOID); +UINT64 AA64ReadSctlr1(VOID); +UINT64 AA64ReadSctlr2(VOID); + static char pmu_dt_arr[][PMU_COMPATIBLE_STR_LEN] = { "arm,armv8-pmuv3", "arm,cortex-a78-pmu", @@ -246,6 +264,62 @@ PalGetMaxMpidr() return gMpidrMax; } +/** + @brief Captures the primary PE's MMU configuration for use by secondary PEs. + This function reads TTBR0, TCR, MAIR, and SCTLR from the current EL + and stores them in a global structure that secondary PEs can access. + + @param None + @return None +**/ +STATIC +VOID +PalCaptureMmuConfig(VOID) +{ + UINT64 CurrentEl; + + /* Read current exception level */ + CurrentEl = (AA64ReadCurrentEL() >> 2) & 0x3; + gMmuConfig.current_el = (UINT32)CurrentEl; + + /* Read MMU configuration registers based on current EL */ + if (CurrentEl == 2) { + gMmuConfig.ttbr0 = AA64ReadTtbr0El2(); + gMmuConfig.tcr = AA64ReadTcr2(); + gMmuConfig.mair = AA64ReadMair2(); + gMmuConfig.sctlr = AA64ReadSctlr2(); + } else { + /* Assume EL1 */ + gMmuConfig.ttbr0 = AA64ReadTtbr0El1(); + gMmuConfig.tcr = AA64ReadTcr1(); + gMmuConfig.mair = AA64ReadMair1(); + gMmuConfig.sctlr = AA64ReadSctlr1(); + } + + acs_print(ACS_PRINT_INFO, L" MMU Config captured at EL%d\n", gMmuConfig.current_el); + acs_print(ACS_PRINT_DEBUG, L" TTBR0: 0x%lx\n", gMmuConfig.ttbr0); + acs_print(ACS_PRINT_DEBUG, L" TCR: 0x%lx\n", gMmuConfig.tcr); + acs_print(ACS_PRINT_DEBUG, L" MAIR: 0x%lx\n", gMmuConfig.mair); + acs_print(ACS_PRINT_DEBUG, L" SCTLR: 0x%lx\n", gMmuConfig.sctlr); + + /* Clean cache to ensure secondary PEs see the config */ + pal_pe_data_cache_ops_by_va((UINT64)&gMmuConfig, CLEAN_AND_INVALIDATE); +} + +/** + @brief Returns the address of the MMU configuration structure. + This function is called by secondary PE entry code to get + the primary PE's MMU configuration. + + @param None + @return Address of PE_MMU_CONFIG structure +**/ +UINT64 +PalGetMmuConfigAddr(VOID) +{ + return (UINT64)&gMmuConfig; +} + /** @brief Allocate memory region for secondary PE stack use. SIZE of stack for each PE is a #define @@ -697,5 +771,8 @@ pal_pe_create_info_table_dt(PE_INFO_TABLE *PeTable) pal_pe_data_cache_ops_by_va((UINT64)&gMpidrMax, CLEAN_AND_INVALIDATE); PalAllocateSecondaryStack(gMpidrMax); + /* Capture primary PE's MMU configuration for secondary PE initialization */ + PalCaptureMmuConfig(); + dt_dump_pe_table(PeTable); } diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index f1b36eb0..dc1cd9dd 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -184,7 +184,21 @@ typedef struct { uint32_t tg_size_log2:5; }PE_TCR_BF; +/** + @brief MMU configuration structure for secondary PE initialization + This structure holds the primary PE's MMU configuration which + is used to enable MMU/caches on secondary PEs. +**/ +typedef struct { + uint64_t ttbr0; ///< Translation Table Base Register 0 + uint64_t tcr; ///< Translation Control Register + uint64_t mair; ///< Memory Attribute Indirection Register + uint64_t sctlr; ///< System Control Register + uint32_t current_el; ///< Current Exception Level (1 or 2) +} PE_MMU_CONFIG; + void pal_pe_create_info_table(PE_INFO_TABLE *pe_info_table); +uint64_t PalGetMmuConfigAddr(void); /** @brief Structure to Pass SMC arguments. Return data is also filled into diff --git a/val/src/AArch64/PeRegSysSupport.S b/val/src/AArch64/PeRegSysSupport.S index f3d7095a..01e5c974 100644 --- a/val/src/AArch64/PeRegSysSupport.S +++ b/val/src/AArch64/PeRegSysSupport.S @@ -728,5 +728,70 @@ ASM_PFX(AA64ReadTrbPtrEl1): ret ASM_PFX(AA64IssueISB): + isb + ret + +// MMU register write functions for secondary PE initialization + +GCC_ASM_EXPORT (AA64WriteMair1) +GCC_ASM_EXPORT (AA64WriteMair2) +GCC_ASM_EXPORT (AA64WriteTcr1) +GCC_ASM_EXPORT (AA64WriteTcr2) +GCC_ASM_EXPORT (AA64WriteTtbr0El1) +GCC_ASM_EXPORT (AA64WriteTtbr0El2) +GCC_ASM_EXPORT (AA64WriteSctlr1) +GCC_ASM_EXPORT (AA64WriteSctlr2) +GCC_ASM_EXPORT (AA64TlbiVmalle1) +GCC_ASM_EXPORT (AA64TlbiAlle2) + +ASM_PFX(AA64WriteMair1): + msr mair_el1, x0 // write EL1 MAIR + isb + ret + +ASM_PFX(AA64WriteMair2): + msr mair_el2, x0 // write EL2 MAIR + isb + ret + +ASM_PFX(AA64WriteTcr1): + msr tcr_el1, x0 // write EL1 TCR + isb + ret + +ASM_PFX(AA64WriteTcr2): + msr tcr_el2, x0 // write EL2 TCR + isb + ret + +ASM_PFX(AA64WriteTtbr0El1): + msr ttbr0_el1, x0 // write EL1 TTBR0 + isb + ret + +ASM_PFX(AA64WriteTtbr0El2): + msr ttbr0_el2, x0 // write EL2 TTBR0 + isb + ret + +ASM_PFX(AA64WriteSctlr1): + msr sctlr_el1, x0 // write EL1 SCTLR + isb + ret + +ASM_PFX(AA64WriteSctlr2): + msr sctlr_el2, x0 // write EL2 SCTLR + isb + ret + +ASM_PFX(AA64TlbiVmalle1): + tlbi vmalle1 // Invalidate all EL1 TLB entries + dsb sy + isb + ret + +ASM_PFX(AA64TlbiAlle2): + tlbi alle2 // Invalidate all EL2 TLB entries + dsb sy isb ret \ No newline at end of file diff --git a/val/src/acs_pe_infra.c b/val/src/acs_pe_infra.c index 23cd0ca4..dc808578 100644 --- a/val/src/acs_pe_infra.c +++ b/val/src/acs_pe_infra.c @@ -223,6 +223,7 @@ val_pe_get_index_mpid(uint64_t mpid) Uses PSCI_CPU_OFF to switch off PE after payload execution. 1. Caller - PAL code 2. Prerequisite - Stack pointer for this PE is setup by PAL + MMU/caches enabled by ModuleEntryPoint @param None @return None **/ From e5e787f31bd24d2598f1083b5339673015aec96c Mon Sep 17 00:00:00 2001 From: Srikar Josyula Date: Wed, 4 Feb 2026 17:55:32 +0530 Subject: [PATCH 2/2] chore: copyright update to modified files - updated copyright year to 2026 for the modified files. Signed-off-by: Srikar Josyula --- pal/uefi_acpi/include/pal_uefi.h | 2 +- pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S | 2 +- pal/uefi_acpi/src/pal_pe.c | 2 +- pal/uefi_dt/include/pal_uefi.h | 2 +- pal/uefi_dt/src/AArch64/ModuleEntryPoint.S | 2 +- pal/uefi_dt/src/pal_pe.c | 2 +- val/src/acs_pe_infra.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/pal/uefi_acpi/include/pal_uefi.h b/pal/uefi_acpi/include/pal_uefi.h index a8739043..3a11f5fb 100644 --- a/pal/uefi_acpi/include/pal_uefi.h +++ b/pal/uefi_acpi/include/pal_uefi.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S b/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S index ee6e1189..52a72fc7 100644 --- a/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S +++ b/pal/uefi_acpi/src/AArch64/ModuleEntryPoint.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2018,2024-2025, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2018,2024-2026, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/pal/uefi_acpi/src/pal_pe.c b/pal/uefi_acpi/src/pal_pe.c index 55ab63c5..62e7a498 100644 --- a/pal/uefi_acpi/src/pal_pe.c +++ b/pal/uefi_acpi/src/pal_pe.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/pal/uefi_dt/include/pal_uefi.h b/pal/uefi_dt/include/pal_uefi.h index a2040b35..83064801 100644 --- a/pal/uefi_dt/include/pal_uefi.h +++ b/pal/uefi_dt/include/pal_uefi.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S b/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S index ee6e1189..52a72fc7 100644 --- a/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S +++ b/pal/uefi_dt/src/AArch64/ModuleEntryPoint.S @@ -1,5 +1,5 @@ #/** @file -# Copyright (c) 2016-2018,2024-2025, Arm Limited or its affiliates. All rights reserved. +# Copyright (c) 2016-2018,2024-2026, Arm Limited or its affiliates. All rights reserved. # SPDX-License-Identifier : Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/pal/uefi_dt/src/pal_pe.c b/pal/uefi_dt/src/pal_pe.c index 8f8f9a21..939c7975 100644 --- a/pal/uefi_dt/src/pal_pe.c +++ b/pal/uefi_dt/src/pal_pe.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2021, 2023-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2021, 2023-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); diff --git a/val/src/acs_pe_infra.c b/val/src/acs_pe_infra.c index dc808578..c0825e4b 100644 --- a/val/src/acs_pe_infra.c +++ b/val/src/acs_pe_infra.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2016-2018, 2020-2021,2023-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2016-2018, 2020-2021,2023-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License");