From 78d5396fa023b3f2f06686749f8e172719589d97 Mon Sep 17 00:00:00 2001 From: Sujana M Date: Mon, 14 Jul 2025 00:07:58 +0530 Subject: [PATCH] enhancement(pmu): add node_index to PMU event info - Extend pal_pmu_get_event_info to use node_index for more granular event ID resolution across PMU nodes. - Update event_list entries, signatures, and related logic in PAL and VAL layers in UEFI and BM to support the enhancement. - Remove the hardcoded PMU `event_list` array from PAL implementations and instead declare it as a shared `PLATFORM_OVERRIDE_EVENT_DETAILS` array per platform (e.g., RDN2, RDV3, RDV3CFG1). This enables platform-specific configuration of PMU events. - Update `pal_pmu_get_event_info()` to use `node_index` for precise event ID lookup, supporting cases with multiple PMU nodes of the same type. - Delete unused `pal_pmu.h` from baremetal and unify the `event_details` struct definition across PAL layers. Signed-off-by: Sujana M Change-Id: I37350362942878c8621809ae940999aab5ca3efe --- pal/baremetal/base/include/pal_pmu.h | 52 -------------- pal/baremetal/base/src/pal_pmu.c | 50 +++---------- .../RDN2/include/platform_override_struct.h | 37 +++++++++- .../target/RDN2/src/platform_cfg_fvp.c | 34 ++++++++- .../RDV3/include/platform_override_struct.h | 37 +++++++++- .../target/RDV3/src/platform_cfg_fvp.c | 34 ++++++++- .../include/platform_override_struct.h | 37 +++++++++- .../target/RDV3CFG1/src/platform_cfg_fvp.c | 34 ++++++++- pal/uefi_acpi/include/pal_pmu.h | 9 ++- pal/uefi_acpi/src/pal_pmu.c | 70 +++++++++---------- val/include/pal_interface.h | 11 +-- val/src/acs_pmu.c | 4 +- 12 files changed, 265 insertions(+), 144 deletions(-) delete mode 100644 pal/baremetal/base/include/pal_pmu.h diff --git a/pal/baremetal/base/include/pal_pmu.h b/pal/baremetal/base/include/pal_pmu.h deleted file mode 100644 index 568ef1eb..00000000 --- a/pal/baremetal/base/include/pal_pmu.h +++ /dev/null @@ -1,52 +0,0 @@ -/** @file - * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. - * SPDX-License-Identifier : Apache-2.0 - - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. -**/ - -#ifndef __PAL_SBSA_PMU_H__ -#define __PAL_SBSA_PMU_H__ - -/* Not defined APMT related structures and defines in EDK2, - * Remove this header once EDK2 supports APMT */ - -typedef enum { - PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */ - PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */ - PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */ - PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */ - PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */ - PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */ - PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */ - PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */ - PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */ - PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */ - PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */ - PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */ - PMU_EVENT_ALL_BW, /* All traffic bandwidth */ - PMU_EVENT_TRAFFIC_1, /* traffic type 1 */ - PMU_EVENT_TRAFFIC_2 /* traffic type 2 */ -} PMU_EVENT_TYPE_e; - -typedef enum { - PMU_NODE_MEM_CNTR, - PMU_NODE_SMMU, - PMU_NODE_PCIE_RC, - PMU_NODE_ACPI_DEVICE, - PMU_NODE_PE_CACHE -} PMU_NODE_INFO_TYPE; - -#define PMU_EVENT_INVALID 0xFFFFFFFF - -#endif diff --git a/pal/baremetal/base/src/pal_pmu.c b/pal/baremetal/base/src/pal_pmu.c index 245e87bf..ec2c60cd 100644 --- a/pal/baremetal/base/src/pal_pmu.c +++ b/pal/baremetal/base/src/pal_pmu.c @@ -16,10 +16,10 @@ **/ #include "platform_override_struct.h" -#include "pal_pmu.h" #include "pal_common_support.h" extern PLATFORM_OVERRIDE_PMU_INFO_TABLE platform_pmu_cfg; +extern PLATFORM_OVERRIDE_EVENT_DETAILS event_list[]; /** @brief Display PMU info table details @@ -98,49 +98,12 @@ pal_pmu_create_info_table(PMU_INFO_TABLE *PmuTable) } } -typedef struct{ - PMU_NODE_INFO_TYPE node_type; - PMU_EVENT_TYPE_e event_desc; - uint32_t event_id; -}event_details; - -/* Array containing the details of implementation defined system PMU events */ -event_details event_list[] = { - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID}, - {PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID} -}; - /** @brief This API returns the event ID to be filled into PMEVTYPER register. Prerequisite - event_list array. This API should be called after filling the required event IDs into event_list array. + @param node_index - Index of PMU node. @param event_type - Type of the event. @param node_type - PMU Node type @@ -148,11 +111,14 @@ event_details event_list[] = { **/ uint32_t -pal_pmu_get_event_info(PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type) +pal_pmu_get_event_info(uint32_t node_index, PMU_EVENT_TYPE_e event_type, + PMU_NODE_INFO_TYPE node_type) { - uint32_t i=0; - while (event_list[i].node_type != node_type || event_list[i].event_desc != event_type) { + uint32_t i = 0; + while (event_list[i].node_index != node_index || event_list[i].node_type != node_type || + event_list[i].event_desc != event_type) { i++; } + return event_list[i].event_id; } diff --git a/pal/baremetal/target/RDN2/include/platform_override_struct.h b/pal/baremetal/target/RDN2/include/platform_override_struct.h index e4904262..ea952896 100644 --- a/pal/baremetal/target/RDN2/include/platform_override_struct.h +++ b/pal/baremetal/target/RDN2/include/platform_override_struct.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -497,3 +497,38 @@ typedef struct { uint64_t tpm_base; /* TPM MMIO base address */ uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */ } PLATFORM_OVERRIDE_TPM2_INFO_TABLE; + +typedef enum { + PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */ + PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */ + PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */ + PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */ + PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */ + PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */ + PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */ + PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */ + PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */ + PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */ + PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */ + PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */ + PMU_EVENT_ALL_BW, /* All traffic bandwidth */ + PMU_EVENT_TRAFFIC_1, /* traffic type 1 */ + PMU_EVENT_TRAFFIC_2 /* traffic type 2 */ +} PMU_EVENT_TYPE_e; + +typedef enum { + PMU_NODE_MEM_CNTR, + PMU_NODE_SMMU, + PMU_NODE_PCIE_RC, + PMU_NODE_ACPI_DEVICE, + PMU_NODE_PE_CACHE +} PMU_NODE_INFO_TYPE; + +#define PMU_EVENT_INVALID 0xFFFFFFFF + +typedef struct{ + uint32_t node_index; + PMU_NODE_INFO_TYPE node_type; + PMU_EVENT_TYPE_e event_desc; + uint32_t event_id; +} PLATFORM_OVERRIDE_EVENT_DETAILS; diff --git a/pal/baremetal/target/RDN2/src/platform_cfg_fvp.c b/pal/baremetal/target/RDN2/src/platform_cfg_fvp.c index 866b7630..52ccb87c 100644 --- a/pal/baremetal/target/RDN2/src/platform_cfg_fvp.c +++ b/pal/baremetal/target/RDN2/src/platform_cfg_fvp.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -1623,3 +1623,35 @@ PLATFORM_OVERRIDE_TPM2_INFO_TABLE platform_tpm2_cfg = { .tpm_base = PLATFORM_TPM_BASE_ADDR, .tpm_interface_type = PLATFORM_TPM_INTERFACE_TYPE, }; + +/* Array containing the details of implementation defined system PMU events */ +PLATFORM_OVERRIDE_EVENT_DETAILS event_list[] = { + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID} +}; diff --git a/pal/baremetal/target/RDV3/include/platform_override_struct.h b/pal/baremetal/target/RDV3/include/platform_override_struct.h index e2877b25..71e11911 100644 --- a/pal/baremetal/target/RDV3/include/platform_override_struct.h +++ b/pal/baremetal/target/RDV3/include/platform_override_struct.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -496,3 +496,38 @@ typedef struct { uint64_t tpm_base; /* TPM MMIO base address */ uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */ } PLATFORM_OVERRIDE_TPM2_INFO_TABLE; + +typedef enum { + PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */ + PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */ + PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */ + PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */ + PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */ + PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */ + PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */ + PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */ + PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */ + PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */ + PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */ + PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */ + PMU_EVENT_ALL_BW, /* All traffic bandwidth */ + PMU_EVENT_TRAFFIC_1, /* traffic type 1 */ + PMU_EVENT_TRAFFIC_2 /* traffic type 2 */ +} PMU_EVENT_TYPE_e; + +typedef enum { + PMU_NODE_MEM_CNTR, + PMU_NODE_SMMU, + PMU_NODE_PCIE_RC, + PMU_NODE_ACPI_DEVICE, + PMU_NODE_PE_CACHE +} PMU_NODE_INFO_TYPE; + +#define PMU_EVENT_INVALID 0xFFFFFFFF + +typedef struct{ + uint32_t node_index; + PMU_NODE_INFO_TYPE node_type; + PMU_EVENT_TYPE_e event_desc; + uint32_t event_id; +} PLATFORM_OVERRIDE_EVENT_DETAILS; diff --git a/pal/baremetal/target/RDV3/src/platform_cfg_fvp.c b/pal/baremetal/target/RDV3/src/platform_cfg_fvp.c index a2355555..46c3aafe 100644 --- a/pal/baremetal/target/RDV3/src/platform_cfg_fvp.c +++ b/pal/baremetal/target/RDV3/src/platform_cfg_fvp.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -1465,3 +1465,35 @@ PLATFORM_OVERRIDE_TPM2_INFO_TABLE platform_tpm2_cfg = { .tpm_base = PLATFORM_TPM_BASE_ADDR, .tpm_interface_type = PLATFORM_TPM_INTERFACE_TYPE, }; + +/* Array containing the details of implementation defined system PMU events */ +PLATFORM_OVERRIDE_EVENT_DETAILS event_list[] = { + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID} +}; diff --git a/pal/baremetal/target/RDV3CFG1/include/platform_override_struct.h b/pal/baremetal/target/RDV3CFG1/include/platform_override_struct.h index e2877b25..71e11911 100644 --- a/pal/baremetal/target/RDV3CFG1/include/platform_override_struct.h +++ b/pal/baremetal/target/RDV3CFG1/include/platform_override_struct.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -496,3 +496,38 @@ typedef struct { uint64_t tpm_base; /* TPM MMIO base address */ uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */ } PLATFORM_OVERRIDE_TPM2_INFO_TABLE; + +typedef enum { + PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */ + PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */ + PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */ + PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */ + PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */ + PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */ + PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */ + PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */ + PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */ + PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */ + PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */ + PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */ + PMU_EVENT_ALL_BW, /* All traffic bandwidth */ + PMU_EVENT_TRAFFIC_1, /* traffic type 1 */ + PMU_EVENT_TRAFFIC_2 /* traffic type 2 */ +} PMU_EVENT_TYPE_e; + +typedef enum { + PMU_NODE_MEM_CNTR, + PMU_NODE_SMMU, + PMU_NODE_PCIE_RC, + PMU_NODE_ACPI_DEVICE, + PMU_NODE_PE_CACHE +} PMU_NODE_INFO_TYPE; + +#define PMU_EVENT_INVALID 0xFFFFFFFF + +typedef struct{ + uint32_t node_index; + PMU_NODE_INFO_TYPE node_type; + PMU_EVENT_TYPE_e event_desc; + uint32_t event_id; +} PLATFORM_OVERRIDE_EVENT_DETAILS; diff --git a/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c b/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c index 2dcccb2c..f1e59722 100644 --- a/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c +++ b/pal/baremetal/target/RDV3CFG1/src/platform_cfg_fvp.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -1240,3 +1240,35 @@ PLATFORM_OVERRIDE_TPM2_INFO_TABLE platform_tpm2_cfg = { .tpm_base = PLATFORM_TPM_BASE_ADDR, .tpm_interface_type = PLATFORM_TPM_INTERFACE_TYPE, }; + +/* Array containing the details of implementation defined system PMU events */ +PLATFORM_OVERRIDE_EVENT_DETAILS event_list[] = { + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID} +}; diff --git a/pal/uefi_acpi/include/pal_pmu.h b/pal/uefi_acpi/include/pal_pmu.h index f51d5c01..0fcfffab 100644 --- a/pal/uefi_acpi/include/pal_pmu.h +++ b/pal/uefi_acpi/include/pal_pmu.h @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -73,4 +73,11 @@ typedef struct { UINT32 implementation_id; } APMT_NODE; +typedef struct{ + UINT32 node_index; + PMU_NODE_INFO_TYPE node_type; + PMU_EVENT_TYPE_e event_desc; + UINT32 event_id; +} event_details; + #endif diff --git a/pal/uefi_acpi/src/pal_pmu.c b/pal/uefi_acpi/src/pal_pmu.c index d66e6aad..422ab706 100644 --- a/pal/uefi_acpi/src/pal_pmu.c +++ b/pal/uefi_acpi/src/pal_pmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -113,42 +113,36 @@ pal_pmu_create_info_table(PMU_INFO_TABLE *PmuTable) pal_pmu_dump_info_table(PmuTable); } -typedef struct{ - PMU_NODE_INFO_TYPE node_type; - PMU_EVENT_TYPE_e event_desc; - UINT32 event_id; -}event_details; - /* Array containing the details of implementation defined system PMU events */ event_details event_list[] = { - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, - {PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, - {PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID}, - {PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID} + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID}, + {0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID} }; /** @@ -156,6 +150,7 @@ event_details event_list[] = { Prerequisite - event_list array. This API should be called after filling the required event IDs into event_list array. + @param node_index - Index of PMU node. @param event_type - Type of the event. @param node_type - PMU Node type @@ -163,10 +158,11 @@ event_details event_list[] = { **/ UINT32 -pal_pmu_get_event_info(PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type) +pal_pmu_get_event_info(UINT32 node_index, PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type) { UINT32 i=0; - while (event_list[i].node_type != node_type || event_list[i].event_desc != event_type) { + while (event_list[i].node_index != node_index || event_list[i].node_type != node_type + || event_list[i].event_desc != event_type) { i++; } return event_list[i].event_id; diff --git a/val/include/pal_interface.h b/val/include/pal_interface.h index f1b36eb0..086b98fa 100644 --- a/val/include/pal_interface.h +++ b/val/include/pal_interface.h @@ -619,7 +619,7 @@ typedef struct { **/ typedef struct { PERIPHERAL_INFO_HDR header; - PERIPHERAL_INFO_BLOCK info[]; ///< Array of Information blocks - instantiated for each peripheral + PERIPHERAL_INFO_BLOCK info[]; ///< Array of Information blocks instantiated for each peripheral }PERIPHERAL_INFO_TABLE; void pal_peripheral_create_info_table(PERIPHERAL_INFO_TABLE *per_info_table); @@ -645,7 +645,8 @@ typedef struct PERIPHERAL_VECTOR_LIST_STRUCT struct PERIPHERAL_VECTOR_LIST_STRUCT *next; }PERIPHERAL_VECTOR_LIST; -uint32_t pal_get_msi_vectors (uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn, PERIPHERAL_VECTOR_LIST **mvector); +uint32_t pal_get_msi_vectors (uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn, + PERIPHERAL_VECTOR_LIST **mvector); #define LEGACY_PCI_IRQ_CNT 4 // Legacy PCI IRQ A, B, C. and D @@ -660,7 +661,8 @@ typedef struct { #define DEVCTL_SNOOP_BIT 11 // Device control register no snoop bit -uint32_t pal_pcie_get_legacy_irq_map(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn, PERIPHERAL_IRQ_MAP *irq_map); +uint32_t pal_pcie_get_legacy_irq_map(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn, + PERIPHERAL_IRQ_MAP *irq_map); uint32_t pal_pcie_get_root_port_bdf(uint32_t *seg, uint32_t *bus, uint32_t *dev, uint32_t *func); uint32_t pal_pcie_get_snoop_bit(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); uint32_t pal_pcie_get_dma_support(uint32_t seg, uint32_t bus, uint32_t dev, uint32_t fn); @@ -1040,7 +1042,8 @@ typedef enum { @return None **/ void pal_pmu_create_info_table(PMU_INFO_TABLE *PmuTable); -uint32_t pal_pmu_get_event_info(PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type); +uint32_t pal_pmu_get_event_info(uint32_t node_index, PMU_EVENT_TYPE_e event_type, + PMU_NODE_INFO_TYPE node_type); uint32_t pal_pmu_get_multi_traffic_support_interface(uint64_t *interface_acpiid, uint32_t *num_traffic_type_support); uint32_t pal_generate_traffic(uint64_t interface_acpiid, uint32_t pmu_node_index, diff --git a/val/src/acs_pmu.c b/val/src/acs_pmu.c index 3cff7aaf..3af235d2 100644 --- a/val/src/acs_pmu.c +++ b/val/src/acs_pmu.c @@ -1,5 +1,5 @@ /** @file - * Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved. + * Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved. * SPDX-License-Identifier : Apache-2.0 * Licensed under the Apache License, Version 2.0 (the "License"); @@ -431,7 +431,7 @@ val_pmu_configure_monitor(uint32_t node_index, PMU_EVENT_TYPE_e event_type, uint node_type = val_pmu_get_info(PMU_NODE_TYPE, node_index); /* Get event id details based on Implementation */ - data = pal_pmu_get_event_info(event_type, node_type); + data = pal_pmu_get_event_info(node_index, event_type, node_type); if (data == PMU_EVENT_INVALID) { return 1;