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enhancement(pmu): add node_index to PMU event info #227

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Merged
chetan-rathore merged 1 commit into from
Feb 3, 2026
Merged

enhancement(pmu): add node_index to PMU event info #227

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52 changes: 0 additions & 52 deletions pal/baremetal/base/include/pal_pmu.h
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50 changes: 8 additions & 42 deletions pal/baremetal/base/src/pal_pmu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -16,10 +16,10 @@
**/

#include "platform_override_struct.h"
#include "pal_pmu.h"
#include "pal_common_support.h"

extern PLATFORM_OVERRIDE_PMU_INFO_TABLE platform_pmu_cfg;
extern PLATFORM_OVERRIDE_EVENT_DETAILS event_list[];

/**
@brief Display PMU info table details
Expand Down Expand Up @@ -98,61 +98,27 @@ pal_pmu_create_info_table(PMU_INFO_TABLE *PmuTable)
}
}

typedef struct{
PMU_NODE_INFO_TYPE node_type;
PMU_EVENT_TYPE_e event_desc;
uint32_t event_id;
}event_details;

/* Array containing the details of implementation defined system PMU events */
event_details event_list[] = {
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
{PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
{PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
{PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID},
{PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID}
};

/**
@brief This API returns the event ID to be filled into PMEVTYPER register.
Prerequisite - event_list array. This API should be called after
filling the required event IDs into event_list array.

@param node_index - Index of PMU node.
@param event_type - Type of the event.
@param node_type - PMU Node type

@return Event ID

**/
uint32_t
pal_pmu_get_event_info(PMU_EVENT_TYPE_e event_type, PMU_NODE_INFO_TYPE node_type)
pal_pmu_get_event_info(uint32_t node_index, PMU_EVENT_TYPE_e event_type,
PMU_NODE_INFO_TYPE node_type)
{
uint32_t i=0;
while (event_list[i].node_type != node_type || event_list[i].event_desc != event_type) {
uint32_t i = 0;
while (event_list[i].node_index != node_index || event_list[i].node_type != node_type ||
event_list[i].event_desc != event_type) {
i++;
}

return event_list[i].event_id;
}
37 changes: 36 additions & 1 deletion pal/baremetal/target/RDN2/include/platform_override_struct.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2024-2025, Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2024-2026, Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0

* Licensed under the Apache License, Version 2.0 (the "License");
Expand Down Expand Up @@ -497,3 +497,38 @@ typedef struct {
uint64_t tpm_base; /* TPM MMIO base address */
uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */
} PLATFORM_OVERRIDE_TPM2_INFO_TABLE;

typedef enum {
PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */
PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */
PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */
PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */
PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */
PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */
PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */
PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */
PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */
PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */
PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */
PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */
PMU_EVENT_ALL_BW, /* All traffic bandwidth */
PMU_EVENT_TRAFFIC_1, /* traffic type 1 */
PMU_EVENT_TRAFFIC_2 /* traffic type 2 */
} PMU_EVENT_TYPE_e;

typedef enum {
PMU_NODE_MEM_CNTR,
PMU_NODE_SMMU,
PMU_NODE_PCIE_RC,
PMU_NODE_ACPI_DEVICE,
PMU_NODE_PE_CACHE
} PMU_NODE_INFO_TYPE;

#define PMU_EVENT_INVALID 0xFFFFFFFF

typedef struct{
uint32_t node_index;
PMU_NODE_INFO_TYPE node_type;
PMU_EVENT_TYPE_e event_desc;
uint32_t event_id;
} PLATFORM_OVERRIDE_EVENT_DETAILS;
34 changes: 33 additions & 1 deletion pal/baremetal/target/RDN2/src/platform_cfg_fvp.c
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0

* Licensed under the Apache License, Version 2.0 (the "License");
Expand Down Expand Up @@ -1623,3 +1623,35 @@ PLATFORM_OVERRIDE_TPM2_INFO_TABLE platform_tpm2_cfg = {
.tpm_base = PLATFORM_TPM_BASE_ADDR,
.tpm_interface_type = PLATFORM_TPM_INTERFACE_TYPE,
};

/* Array containing the details of implementation defined system PMU events */
PLATFORM_OVERRIDE_EVENT_DETAILS event_list[] = {
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID},
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID}
};
37 changes: 36 additions & 1 deletion pal/baremetal/target/RDV3/include/platform_override_struct.h
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0

* Licensed under the Apache License, Version 2.0 (the "License");
Expand Down Expand Up @@ -496,3 +496,38 @@ typedef struct {
uint64_t tpm_base; /* TPM MMIO base address */
uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */
} PLATFORM_OVERRIDE_TPM2_INFO_TABLE;

typedef enum {
PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */
PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */
PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */
PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */
PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */
PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */
PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */
PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */
PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */
PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */
PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */
PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */
PMU_EVENT_ALL_BW, /* All traffic bandwidth */
PMU_EVENT_TRAFFIC_1, /* traffic type 1 */
PMU_EVENT_TRAFFIC_2 /* traffic type 2 */
} PMU_EVENT_TYPE_e;

typedef enum {
PMU_NODE_MEM_CNTR,
PMU_NODE_SMMU,
PMU_NODE_PCIE_RC,
PMU_NODE_ACPI_DEVICE,
PMU_NODE_PE_CACHE
} PMU_NODE_INFO_TYPE;

#define PMU_EVENT_INVALID 0xFFFFFFFF

typedef struct{
uint32_t node_index;
PMU_NODE_INFO_TYPE node_type;
PMU_EVENT_TYPE_e event_desc;
uint32_t event_id;
} PLATFORM_OVERRIDE_EVENT_DETAILS;
34 changes: 33 additions & 1 deletion pal/baremetal/target/RDV3/src/platform_cfg_fvp.c
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Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0

* Licensed under the Apache License, Version 2.0 (the "License");
Expand Down Expand Up @@ -1465,3 +1465,35 @@ PLATFORM_OVERRIDE_TPM2_INFO_TABLE platform_tpm2_cfg = {
.tpm_base = PLATFORM_TPM_BASE_ADDR,
.tpm_interface_type = PLATFORM_TPM_INTERFACE_TYPE,
};

/* Array containing the details of implementation defined system PMU events */
PLATFORM_OVERRIDE_EVENT_DETAILS event_list[] = {
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_MEM_CNTR, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_READ_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_WRITE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_IB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_OPEN_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_OB_TOTAL_TXN, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_LOCAL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_REMOTE_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_PCIE_RC, PMU_EVENT_ALL_BW, PMU_EVENT_INVALID},
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_1, PMU_EVENT_INVALID},
{0, PMU_NODE_ACPI_DEVICE, PMU_EVENT_TRAFFIC_2, PMU_EVENT_INVALID}
};
37 changes: 36 additions & 1 deletion pal/baremetal/target/RDV3CFG1/include/platform_override_struct.h
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
/** @file
* Copyright (c) 2025, Arm Limited or its affiliates. All rights reserved.
* Copyright (c) 2025-2026, Arm Limited or its affiliates. All rights reserved.
* SPDX-License-Identifier : Apache-2.0

* Licensed under the Apache License, Version 2.0 (the "License");
Expand Down Expand Up @@ -496,3 +496,38 @@ typedef struct {
uint64_t tpm_base; /* TPM MMIO base address */
uint64_t tpm_interface_type; /* StartMethod (6=TIS,7=CRB,...) */
} PLATFORM_OVERRIDE_TPM2_INFO_TABLE;

typedef enum {
PMU_EVENT_IB_TOTAL_BW, /* Inbound total bandwidth */
PMU_EVENT_OB_TOTAL_BW, /* Outbound total bandwidth */
PMU_EVENT_IB_READ_BW, /* Inbound read bandwidth */
PMU_EVENT_IB_WRITE_BW, /* Inbound write bandwidth */
PMU_EVENT_OB_READ_BW, /* Outbound read bandwidth */
PMU_EVENT_OB_WRITE_BW, /* Outbound write bandwidth */
PMU_EVENT_IB_OPEN_TXN, /* Inbound open transactions */
PMU_EVENT_IB_TOTAL_TXN, /* Inbound total transactions */
PMU_EVENT_OB_OPEN_TXN, /* Outbound open transactions */
PMU_EVENT_OB_TOTAL_TXN, /* Outbound total transactions */
PMU_EVENT_LOCAL_BW, /* Local traffic bandwidth */
PMU_EVENT_REMOTE_BW, /* Remote traffic bandwidth */
PMU_EVENT_ALL_BW, /* All traffic bandwidth */
PMU_EVENT_TRAFFIC_1, /* traffic type 1 */
PMU_EVENT_TRAFFIC_2 /* traffic type 2 */
} PMU_EVENT_TYPE_e;

typedef enum {
PMU_NODE_MEM_CNTR,
PMU_NODE_SMMU,
PMU_NODE_PCIE_RC,
PMU_NODE_ACPI_DEVICE,
PMU_NODE_PE_CACHE
} PMU_NODE_INFO_TYPE;

#define PMU_EVENT_INVALID 0xFFFFFFFF

typedef struct{
uint32_t node_index;
PMU_NODE_INFO_TYPE node_type;
PMU_EVENT_TYPE_e event_desc;
uint32_t event_id;
} PLATFORM_OVERRIDE_EVENT_DETAILS;
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