From 1837a516314fa49b96fd5b62e9b1a3caf0485cf4 Mon Sep 17 00:00:00 2001 From: YRabbit Date: Wed, 19 Nov 2025 14:40:39 +1000 Subject: [PATCH] Gowin. Misc fixes. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Correcting syntax in the constraints file. Also, using the -setundef flag during synthesis—it forces unused primitive pins to be explicitly connected to 0. Signed-off-by: YRabbit --- .../FROM_BLINKER_TO_RISCV/BOARDS/run_tangnano9k.sh | 2 +- .../FROM_BLINKER_TO_RISCV/BOARDS/tangnano9k.cst | 12 ++++++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/run_tangnano9k.sh b/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/run_tangnano9k.sh index d752721e..c2b76c5a 100755 --- a/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/run_tangnano9k.sh +++ b/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/run_tangnano9k.sh @@ -7,7 +7,7 @@ FPGA_FAMILY=GW1N-9C FPGA_DEVICE=GW1NR-LV9QN88PC6/I5 VERILOGS=$1 -$FPGA_ROOT/yosys -q -DTANGNANO9K -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "synth_gowin -top $PROJECTNAME -json $PROJECTNAME.json" $VERILOGS || exit +$FPGA_ROOT/yosys -q -DTANGNANO9K -DBOARD_FREQ=$BOARD_FREQ -DCPU_FREQ=$CPU_FREQ -p "synth_gowin -setundef -top $PROJECTNAME -json $PROJECTNAME.json" $VERILOGS || exit $FPGA_ROOT/nextpnr-himbaechel --force --timing-allow-fail --json $PROJECTNAME.json --vopt cst=BOARDS/$BOARD.cst --write pnr_$PROJECTNAME.json --device $FPGA_DEVICE --vopt family=$FPGA_FAMILY || exit gowin_pack -d $FPGA_FAMILY -o $PROJECTNAME.fs pnr_$PROJECTNAME.json || exit /usr/bin/openFPGALoader -b $BOARD $PROJECTNAME.fs diff --git a/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/tangnano9k.cst b/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/tangnano9k.cst index fcacc492..a4a9ee42 100644 --- a/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/tangnano9k.cst +++ b/FemtoRV/TUTORIALS/FROM_BLINKER_TO_RISCV/BOARDS/tangnano9k.cst @@ -25,19 +25,19 @@ IO_LOC "RESET" 3; IO_PORT "RESET" IO_TYPE=LVCMOS18 PULL_MODE=UP; IO_LOC "SPIFLASH_CLK" 59; -IO_PORT "SPIFLASH_CLK" LVCMOS33; +IO_PORT "SPIFLASH_CLK" IO_TYPE=LVCMOS33; IO_LOC "SPIFLASH_CS_N" 60; -IO_PORT "SPIFLASH_CS_N" LVCMOS33; +IO_PORT "SPIFLASH_CS_N" IO_TYPE=LVCMOS33; IO_LOC "SPIFLASH_MOSI" 61; -IO_PORT "SPIFLASH_MOSI" LVCMOS33; +IO_PORT "SPIFLASH_MOSI" IO_TYPE=LVCMOS33; IO_LOC "SPIFLASH_MISO" 62; -IO_PORT "SPIFLASH_MISO" LVCMOS33; +IO_PORT "SPIFLASH_MISO" IO_TYPE=LVCMOS33; IO_LOC "SPIFLASH_IO[0]" 61; -IO_PORT "SPIFLASH_IO[0]" LVCMOS33; +IO_PORT "SPIFLASH_IO[0]" IO_TYPE=LVCMOS33; IO_LOC "SPIFLASH_IO[1]" 62; -IO_PORT "SPIFLASH_IO[1]" LVCMOS33; +IO_PORT "SPIFLASH_IO[1]" IO_TYPE=LVCMOS33;