Hi Charlotte
I found your work on the Frontiers website. This is something that interests us. I just wanted to ask - if you have a simulator for ODIN and/or MorphIC - where we can test our SNN algorithms, and then use the HDL source to burn an FPGA if everything goes well...
I was a bit confused with this statement in the paper - "Both ODIN and MorphIC follow a standard synchronous digital implementation, which allows their operation to be predicted with one-to-one accuracy by custom Python-based chip simulators" - do you mean that the chips can be simulated using any python chip simulator, and we can test the SNNs on top of that?
Regards
Arijit
Hi Charlotte
I found your work on the Frontiers website. This is something that interests us. I just wanted to ask - if you have a simulator for ODIN and/or MorphIC - where we can test our SNN algorithms, and then use the HDL source to burn an FPGA if everything goes well...
I was a bit confused with this statement in the paper - "Both ODIN and MorphIC follow a standard synchronous digital implementation, which allows their operation to be predicted with one-to-one accuracy by custom Python-based chip simulators" - do you mean that the chips can be simulated using any python chip simulator, and we can test the SNNs on top of that?
Regards
Arijit