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| 1 | +2025-10-29 Jeff Law <jlaw@ventanamicro.com> |
| 2 | + |
| 3 | + Revert: |
| 4 | + 2025-10-29 Jeff Law <jlaw@ventanamicro.com> |
| 5 | + |
| 6 | + PR target/116662 |
| 7 | + * config/riscv/riscv.cc (riscv_option_override): Override |
| 8 | + default value for destructive interference size. |
| 9 | + |
| 10 | +2025-10-29 Jeff Law <jlaw@ventanamicro.com> |
| 11 | + |
| 12 | + Revert: |
| 13 | + 2025-10-29 Jeff Law <jlaw@ventanamicro.com> |
| 14 | + |
| 15 | + PR target/116662 |
| 16 | + * config/riscv/riscv.cc (riscv_option_override): Apply correct version |
| 17 | + of the patch. |
| 18 | + |
| 19 | +2025-10-29 Jeff Law <jlaw@ventanamicro.com> |
| 20 | + |
| 21 | + PR target/116662 |
| 22 | + * config/riscv/riscv.cc (riscv_option_override): Apply correct version |
| 23 | + of the patch. |
| 24 | + |
| 25 | +2025-10-29 Jeff Law <jlaw@ventanamicro.com> |
| 26 | + |
| 27 | + PR target/116662 |
| 28 | + * config/riscv/riscv.cc (riscv_option_override): Override |
| 29 | + default value for destructive interference size. |
| 30 | + |
| 31 | +2025-10-29 Andrew MacLeod <amacleod@redhat.com> |
| 32 | + |
| 33 | + PR tree-optimization/91191 |
| 34 | + * gimple-range-op.cc (gimple_range_op_handler): Descend one |
| 35 | + operand lower for a VIEW_CONVERT_EXPR. |
| 36 | + * range-op-mixed.h (class operator_view): New. |
| 37 | + * range-op.cc (range_op_table): Add VIEW_CONVERT_EXPR case. |
| 38 | + (operator_view::fold_range): New. |
| 39 | + (operator_view::op1_range): New. |
| 40 | + (operator_view::update_bitmask): New. |
| 41 | + |
| 42 | +2025-10-29 Richard Biener <rguenther@suse.de> |
| 43 | + |
| 44 | + * tree-vect-slp.cc (vect_analyze_slp): Mark stmts in BB roots |
| 45 | + as released after vect_build_slp_instance. |
| 46 | + (vect_build_slp_instance): Release scalar_stmts when exiting |
| 47 | + early. |
| 48 | + |
| 49 | +2025-10-29 Lulu Cheng <chenglulu@loongson.cn> |
| 50 | + |
| 51 | + PR target/122097 |
| 52 | + * config/loongarch/loongarch.cc |
| 53 | + (loongarch_const_vector_bitimm_set_p): Add support for vector float. |
| 54 | + (loongarch_const_vector_bitimm_clr_p): Likewise. |
| 55 | + (loongarch_print_operand): Likewise. |
| 56 | + * config/loongarch/simd.md (and<mode>3): Likewise. |
| 57 | + |
| 58 | +2025-10-29 Lulu Cheng <chenglulu@loongson.cn> |
| 59 | + |
| 60 | + * config/loongarch/lasx.md (xor<mode>3): Delete. |
| 61 | + (ior<mode>3): Delete. |
| 62 | + (and<mode>3): Delete. |
| 63 | + * config/loongarch/lsx.md (xor<mode>3): Delete. |
| 64 | + (ior<mode>3): Delete. |
| 65 | + (and<mode>3): Delete. |
| 66 | + * config/loongarch/simd.md (xor<mode>3): Define. |
| 67 | + (ior<mode>3): Likewise. |
| 68 | + (and<mode>3): Likewise. |
| 69 | + |
| 70 | +2025-10-29 Xi Ruoyao <xry111@xry111.site> |
| 71 | + |
| 72 | + * config/loongarch/genopts/loongarch.opt.in (-mbreak-code=): |
| 73 | + New. |
| 74 | + * config/loongarch/loongarch.opt: Regenerate. |
| 75 | + * config/loongarch/loongarch.md (trap): Separate to a |
| 76 | + define_insn and a define_expand which takes la_break_code. |
| 77 | + * doc/invoke.texi (-mbreak-code=): Document. |
| 78 | + * config/loongarch/loongarch.opt.urls: Regenerate. |
| 79 | + |
1 | 80 | 2025-10-28 Richard Biener <rguenther@suse.de> |
2 | 81 |
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3 | 82 | * tree-vect-loop-manip.cc (vect_update_ivs_after_vectorizer): |
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