consistency with timeloop

[ywlywl6]

May I ask whether the results of factor-flow remain fully consistent with those of the timeloop-model when mapping any algorithm onto any (not too complex) hardware architecture, assuming the dataflow is exactly the same?

[EMJzero]

For a fixed, and equivalent mapping, kernel, and hardware model, FactorFlow and Timeloop should indeed be equivalent. For good measure, however, I would lay down two further assumptions:

• it is possible to fully write the architecture's model in both FactorFlow and Timeloop, whose feature-sets slightly differ
• no setting in FactorFlow is altered as of the current repository state, since they can enable features that don't have a counterpart in Timeloop

Additionally, you may want to manually move energy and latency data from Timeloop's output over to the FactorFlow model, otherwise you would need to rely on a local installation of Accelergy and use this model, where you would need to also manually port the Accelergy model underlying Timeloop's.

Apologies for the late reply.