Inconsistent presence of buffers in mux units in VHDL/SMV/Verilog

[Basmet0]

The mux unit of VHDL contains a slot (one_slot_break_r), whereas the mux unit of Verilog only contains the state of which input to select, and in SMV, there is no internal state at all.

Similarly, the VHDL and Verilog merge units contain a slot, whereas in SMV there is again no internal state.