diff --git a/data/rtl-config-smv.json b/data/rtl-config-smv.json index 0bf2d456f5..84edb6e0e1 100644 --- a/data/rtl-config-smv.json +++ b/data/rtl-config-smv.json @@ -6,14 +6,18 @@ }, { "name": "handshake.buffer", - "parameters": [ - {"name": "NUM_SLOTS", "type": "unsigned"}, - { - "name": "BUFFER_TYPE", - "type": "string" - } - ], - "generator": "python $DYNAMATIC/experimental/tools/unit-generators/smv/smv-unit-generator.py -n $MODULE_NAME -o $OUTPUT_DIR/$MODULE_NAME.smv -t buffer -p num_slots=$NUM_SLOTS bitwidth=$BITWIDTH buffer_type='\"$BUFFER_TYPE\"'", + "parameters": [ + {"name": "NUM_SLOTS", "type": "unsigned"}, + { + "name": "BUFFER_TYPE", + "type": "string" + }, + { + "name": "DEBUG_COUNTER", + "type": "boolean" + } + ], + "generator": "python $DYNAMATIC/experimental/tools/unit-generators/smv/smv-unit-generator.py -n $MODULE_NAME -o $OUTPUT_DIR/$MODULE_NAME.smv -t buffer -p num_slots=$NUM_SLOTS bitwidth=$BITWIDTH buffer_type='\"$BUFFER_TYPE\"' debug_counter=$DEBUG_COUNTER", "hdl": "smv" }, { diff --git a/data/rtl-config-vhdl-beta.json b/data/rtl-config-vhdl-beta.json index 1752744f7e..90e97dbe3a 100644 --- a/data/rtl-config-vhdl-beta.json +++ b/data/rtl-config-vhdl-beta.json @@ -92,9 +92,13 @@ { "name": "BUFFER_TYPE", "type": "string" + }, + { + "name": "DEBUG_COUNTER", + "type": "boolean" } ], - "generator": "python $DYNAMATIC/experimental/tools/unit-generators/vhdl/vhdl-unit-generator.py -n $MODULE_NAME -o $OUTPUT_DIR/$MODULE_NAME.vhd -t buffer -p num_slots=$NUM_SLOTS bitwidth=$BITWIDTH buffer_type='\"$BUFFER_TYPE\"' extra_signals=$EXTRA_SIGNALS" + "generator": "python $DYNAMATIC/experimental/tools/unit-generators/vhdl/vhdl-unit-generator.py -n $MODULE_NAME -o $OUTPUT_DIR/$MODULE_NAME.vhd -t buffer -p num_slots=$NUM_SLOTS bitwidth=$BITWIDTH buffer_type='\"$BUFFER_TYPE\"' extra_signals=$EXTRA_SIGNALS debug_counter=$DEBUG_COUNTER" }, { "name": "handshake.fork", diff --git a/experimental/tools/unit-generators/smv/generators/handshake/buffer.py b/experimental/tools/unit-generators/smv/generators/handshake/buffer.py index 3ae80e520c..9153531ec4 100644 --- a/experimental/tools/unit-generators/smv/generators/handshake/buffer.py +++ b/experimental/tools/unit-generators/smv/generators/handshake/buffer.py @@ -22,25 +22,26 @@ class BufferType(Enum): def generate_buffer(name, params): slots = params[ATTR_SLOTS] bitwidth = params[ATTR_BITWIDTH] + debug_counter = params.get(ATTR_DEBUG_COUNTER, False) buffer_type = try_enum_cast(params[ATTR_BUFFER_TYPE], BufferType) match buffer_type: case BufferType.ONE_SLOT_BREAK_R: - return generate_one_slot_break_r(name, {ATTR_BITWIDTH: bitwidth}) + return generate_one_slot_break_r(name, {ATTR_BITWIDTH: bitwidth, ATTR_DEBUG_COUNTER: debug_counter}) case BufferType.FIFO_BREAK_NONE: - return generate_fifo_break_none(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth}) + return generate_fifo_break_none(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth, ATTR_DEBUG_COUNTER: debug_counter}) case BufferType.ONE_SLOT_BREAK_DV: - return generate_one_slot_break_dv(name, {ATTR_BITWIDTH: bitwidth}) + return generate_one_slot_break_dv(name, {ATTR_BITWIDTH: bitwidth, ATTR_DEBUG_COUNTER: debug_counter}) case BufferType.FIFO_BREAK_DV: - return generate_fifo_break_dv(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth}) + return generate_fifo_break_dv(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth, ATTR_DEBUG_COUNTER: debug_counter}) case BufferType.ONE_SLOT_BREAK_DVR: # this is wrong # but it is what was being generated based on the previous code - return generate_one_slot_break_dv(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth}) + return generate_one_slot_break_dv(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth, ATTR_DEBUG_COUNTER: debug_counter}) case BufferType.SHIFT_REG_BREAK_DV: # this is wrong # but it is what was being generated based on the previous code - return generate_ofifo(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth}) + return generate_ofifo(name, {ATTR_SLOTS: slots, ATTR_BITWIDTH: bitwidth, ATTR_DEBUG_COUNTER: debug_counter}) case _: raise ValueError(f"Unhandled buffer type: {buffer_type}") diff --git a/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_dv.py b/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_dv.py index ab6352e0ff..a672687572 100644 --- a/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_dv.py +++ b/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_dv.py @@ -1,22 +1,24 @@ from generators.support.utils import * from generators.handshake.buffers.fifo_break_none import generate_fifo_break_none from generators.handshake.buffers.one_slot_break_dv import generate_one_slot_break_dv +from generators.support.buffer_counter import generate_buffer_counter def generate_fifo_break_dv(name, params): slots = params[ATTR_SLOTS] if ATTR_SLOTS in params else 1 data_type = SmvScalarType(params[ATTR_BITWIDTH]) + debug_counter = params.get(ATTR_DEBUG_COUNTER, False) if slots == 1: - return generate_one_slot_break_dv(name, {ATTR_BITWIDTH: params[ATTR_BITWIDTH]}) + return generate_one_slot_break_dv(name, {ATTR_BITWIDTH: params[ATTR_BITWIDTH], ATTR_DEBUG_COUNTER: debug_counter}) if data_type.bitwidth == 0: - return _generate_fifo_break_dv_dataless(name, slots) + return _generate_fifo_break_dv_dataless(name, slots, debug_counter) else: - return _generate_fifo_break_dv(name, slots, data_type) + return _generate_fifo_break_dv(name, slots, data_type, debug_counter) -def _generate_fifo_break_dv_dataless(name, slots): +def _generate_fifo_break_dv_dataless(name, slots, debug_counter): fifo_name = f"{name}__fifo" one_slot_name = f"{name}__break_dv" return f""" @@ -24,6 +26,7 @@ def _generate_fifo_break_dv_dataless(name, slots): VAR fifo : {fifo_name}(ins_valid, break_dv_ready); break_dv : {one_slot_name}(fifo_valid, outs_ready); + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} DEFINE fifo_valid := fifo.outs_valid; @@ -34,10 +37,11 @@ def _generate_fifo_break_dv_dataless(name, slots): {generate_fifo_break_none(fifo_name, {ATTR_SLOTS: slots - 1, ATTR_BITWIDTH: 0})} {generate_one_slot_break_dv(one_slot_name, {ATTR_BITWIDTH: 0})} +{generate_buffer_counter(f"{name}__debug_counter", slots) if debug_counter else ""} """ -def _generate_fifo_break_dv(name, slots, data_type): +def _generate_fifo_break_dv(name, slots, data_type, debug_counter): fifo_name = f"{name}__fifo" one_slot_name = f"{name}__break_dv" return f""" @@ -45,6 +49,7 @@ def _generate_fifo_break_dv(name, slots, data_type): VAR fifo : {fifo_name}(ins, ins_valid, break_dv_ready); break_dv : {one_slot_name}(fifo_data, fifo_valid, outs_ready); + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} DEFINE fifo_data := fifo.outs; @@ -57,4 +62,5 @@ def _generate_fifo_break_dv(name, slots, data_type): {generate_fifo_break_none(fifo_name, {ATTR_SLOTS: slots - 1, ATTR_BITWIDTH: data_type.bitwidth})} {generate_one_slot_break_dv(one_slot_name, {ATTR_BITWIDTH: data_type.bitwidth})} +{generate_buffer_counter(f"{name}__debug_counter", slots) if debug_counter else ""} """ diff --git a/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_none.py b/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_none.py index e653fec01f..86d1af6d92 100644 --- a/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_none.py +++ b/experimental/tools/unit-generators/smv/generators/handshake/buffers/fifo_break_none.py @@ -1,27 +1,30 @@ from generators.support.utils import * +from generators.support.buffer_counter import generate_buffer_counter def generate_fifo_break_none(name, params): slots = params[ATTR_SLOTS] data_type = SmvScalarType(params[ATTR_BITWIDTH]) + debug_counter = params.get(ATTR_DEBUG_COUNTER, False) if data_type.bitwidth == 0: if slots == 1: - return _generate_one_slot_break_none_dataless(name) + return _generate_one_slot_break_none_dataless(name, debug_counter) else: - return _generate_fifo_break_none_dataless(name, slots) + return _generate_fifo_break_none_dataless(name, slots, debug_counter) else: if slots == 1: - return _generate_one_slot_break_none(name, data_type) + return _generate_one_slot_break_none(name, data_type, debug_counter) else: - return _generate_fifo_break_none(name, slots, data_type) + return _generate_fifo_break_none(name, slots, data_type, debug_counter) -def _generate_one_slot_break_none_dataless(name): +def _generate_one_slot_break_none_dataless(name, debug_counter): return f""" MODULE {name}(ins_valid, outs_ready) VAR full : boolean; + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} ASSIGN init(full) := FALSE; @@ -31,15 +34,17 @@ def _generate_one_slot_break_none_dataless(name): DEFINE outs_valid := full | ins_valid; ins_ready := (!full) | outs_ready; +{generate_buffer_counter(f"{name}__debug_counter", 1) if debug_counter else ""} """ -def _generate_one_slot_break_none(name, data_type): +def _generate_one_slot_break_none(name, data_type, debug_counter): return f""" MODULE {name}(ins, ins_valid, outs_ready) VAR reg : {data_type}; full : boolean; + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} ASSIGN init(reg) := {data_type.format_constant(0)}; @@ -52,36 +57,45 @@ def _generate_one_slot_break_none(name, data_type): outs := full ? reg : ins; outs_valid := full | ins_valid; ins_ready := (!full) | outs_ready; +{generate_buffer_counter(f"{name}__debug_counter", 1) if debug_counter else ""} """ -def _generate_fifo_break_none_dataless(name, slots): +def _generate_fifo_break_none_dataless(name, slots, debug_counter): # fifo generated as chain of fully transparent slots for faster model checking - slots_valid = ["ins_valid"] + [f"b{i}.outs_valid" for i in range(slots - 1)] - slots_ready = [f"b{i + 1}.ins_ready" for i in range(slots - 1)] + ["outs_ready"] + slots_valid = ["ins_valid"] + \ + [f"b{i}.outs_valid" for i in range(slots - 1)] + slots_ready = [ + f"b{i + 1}.ins_ready" for i in range(slots - 1)] + ["outs_ready"] return f""" MODULE {name}(ins_valid, outs_ready) {"\n ".join([f"VAR b{n} : {name}_tslot({valid}, {ready});" for n, (valid, ready) in enumerate(zip(slots_valid, slots_ready))])} + {f"VAR debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} -- outputs DEFINE outs_valid := b{slots - 1}.outs_valid; DEFINE ins_ready := b0.ins_ready; -{_generate_one_slot_break_none_dataless(f"{name}_tslot")} +{_generate_one_slot_break_none_dataless(f"{name}_tslot", False)} +{generate_buffer_counter(f"{name}__debug_counter", slots) if debug_counter else ""} """ -def _generate_fifo_break_none(name, slots, data_type): +def _generate_fifo_break_none(name, slots, data_type, debug_counter): # fifo generated as chain of fully transparent slots for faster model checking slots_data = ["ins"] + [f"b{i}.outs" for i in range(slots)] - slots_valid = ["ins_valid"] + [f"b{i}.outs_valid" for i in range(slots - 1)] - slots_ready = [f"b{i + 1}.ins_ready" for i in range(slots - 1)] + ["outs_ready"] + slots_valid = ["ins_valid"] + \ + [f"b{i}.outs_valid" for i in range(slots - 1)] + slots_ready = [ + f"b{i + 1}.ins_ready" for i in range(slots - 1)] + ["outs_ready"] return f""" MODULE {name}(ins, ins_valid, outs_ready) {"\n ".join([f"VAR b{n} : {name}_tslot({data}, {valid}, {ready});" for n, (data, valid, ready) in enumerate(zip(slots_data, slots_valid, slots_ready))])} + {f"VAR debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} -- output DEFINE outs := b{slots - 1}.outs; DEFINE outs_valid := b{slots - 1}.outs_valid; DEFINE ins_ready := b0.ins_ready; -{_generate_one_slot_break_none(f"{name}_tslot", data_type)} +{_generate_one_slot_break_none(f"{name}_tslot", data_type, False)} +{generate_buffer_counter(f"{name}__debug_counter", slots) if debug_counter else ""} """ diff --git a/experimental/tools/unit-generators/smv/generators/handshake/buffers/ofifo.py b/experimental/tools/unit-generators/smv/generators/handshake/buffers/ofifo.py index 5a579683ed..42a22f4f78 100644 --- a/experimental/tools/unit-generators/smv/generators/handshake/buffers/ofifo.py +++ b/experimental/tools/unit-generators/smv/generators/handshake/buffers/ofifo.py @@ -1,24 +1,27 @@ from generators.support.utils import * from generators.handshake.buffers.fifo_break_dv import generate_fifo_break_dv from generators.handshake.buffers.one_slot_break_r import generate_one_slot_break_r +from generators.support.buffer_counter import generate_buffer_counter def generate_ofifo(name, params): slots = params[ATTR_SLOTS] data_type = SmvScalarType(params[ATTR_BITWIDTH]) + debug_counter = params.get(ATTR_DEBUG_COUNTER, False) if data_type.bitwidth == 0: - return _generate_ofifo_dataless(name, slots) + return _generate_ofifo_dataless(name, slots, debug_counter) else: - return _generate_ofifo(name, slots, data_type) + return _generate_ofifo(name, slots, data_type, debug_counter) -def _generate_ofifo_dataless(name, slots): +def _generate_ofifo_dataless(name, slots, debug_counter): return f""" MODULE {name} (ins_valid, outs_ready) VAR inner_tehb : {name}__tehb_dataless(ins_valid, inner_elastic_fifo.ins_ready); inner_elastic_fifo : {name}__elastic_fifo_inner_dataless(inner_tehb.outs_valid, outs_ready); + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} -- output DEFINE @@ -27,15 +30,17 @@ def _generate_ofifo_dataless(name, slots): {generate_one_slot_break_r(f"{name}__tehb_dataless", {ATTR_BITWIDTH: 0})} {generate_fifo_break_dv(f"{name}__elastic_fifo_inner_dataless", {ATTR_SLOTS: slots, ATTR_BITWIDTH: 0})} +{generate_buffer_counter(f"{name}__debug_counter", slots) if debug_counter else ""} """ -def _generate_ofifo(name, slots, data_type): +def _generate_ofifo(name, slots, data_type, debug_counter): return f""" MODULE {name} (ins, ins_valid, outs_ready) VAR inner_tehb : {name}__tehb(ins, ins_valid, inner_elastic_fifo.ins_ready); inner_elastic_fifo : {name}__elastic_fifo_inner(inner_tehb.outs, inner_tehb.outs_valid, outs_ready); + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} -- output DEFINE @@ -45,4 +50,5 @@ def _generate_ofifo(name, slots, data_type): {generate_one_slot_break_r(f"{name}__tehb", {ATTR_BITWIDTH: data_type.bitwidth})} {generate_fifo_break_dv(f"{name}__elastic_fifo_inner", {ATTR_SLOTS: slots, ATTR_BITWIDTH: data_type.bitwidth})} +{generate_buffer_counter(f"{name}__debug_counter", slots) if debug_counter else ""} """ diff --git a/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_dv.py b/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_dv.py index 4d349bff8f..a9e1b375dd 100644 --- a/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_dv.py +++ b/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_dv.py @@ -1,20 +1,23 @@ from generators.support.utils import * +from generators.support.buffer_counter import generate_buffer_counter def generate_one_slot_break_dv(name, params): data_type = SmvScalarType(params[ATTR_BITWIDTH]) + debug_counter = params.get(ATTR_DEBUG_COUNTER, False) if data_type.bitwidth == 0: - return _generate_one_slot_break_dv_dataless(name) + return _generate_one_slot_break_dv_dataless(name, debug_counter) else: - return _generate_one_slot_break_dv(name, data_type) + return _generate_one_slot_break_dv(name, data_type, debug_counter) -def _generate_one_slot_break_dv_dataless(name): +def _generate_one_slot_break_dv_dataless(name, debug_counter): return f""" MODULE {name} (ins_valid, outs_ready) VAR outs_valid_i : boolean; + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} ASSIGN init(outs_valid_i) := FALSE; @@ -24,15 +27,17 @@ def _generate_one_slot_break_dv_dataless(name): DEFINE ins_ready := !outs_valid_i | outs_ready; outs_valid := outs_valid_i; +{generate_buffer_counter(f"{name}__debug_counter", 1) if debug_counter else ""} """ -def _generate_one_slot_break_dv(name, data_type): +def _generate_one_slot_break_dv(name, data_type, debug_counter): return f""" MODULE {name} (ins, ins_valid, outs_ready) VAR inner_one_slot_break_dv : {name}__one_slot_break_dv_dataless(ins_valid, outs_ready); data : {data_type}; + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} ASSIGN init(data) := {data_type.format_constant(0)}; @@ -47,5 +52,6 @@ def _generate_one_slot_break_dv(name, data_type): outs_valid := inner_one_slot_break_dv.outs_valid; outs := data; -{_generate_one_slot_break_dv_dataless(f"{name}__one_slot_break_dv_dataless")} +{_generate_one_slot_break_dv_dataless(f"{name}__one_slot_break_dv_dataless", False)} +{generate_buffer_counter(f"{name}__debug_counter", 1) if debug_counter else ""} """ diff --git a/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_r.py b/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_r.py index 772c81d3c2..1b7a6435b0 100644 --- a/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_r.py +++ b/experimental/tools/unit-generators/smv/generators/handshake/buffers/one_slot_break_r.py @@ -1,20 +1,23 @@ from generators.support.utils import * +from generators.support.buffer_counter import generate_buffer_counter def generate_one_slot_break_r(name, params): data_type = SmvScalarType(params[ATTR_BITWIDTH]) + debug_counter = params.get(ATTR_DEBUG_COUNTER, False) if data_type.bitwidth == 0: - return _generate_one_slot_break_r_dataless(name) + return _generate_one_slot_break_r_dataless(name, debug_counter) else: - return _generate_one_slot_break_r(name, data_type) + return _generate_one_slot_break_r(name, data_type, debug_counter) -def _generate_one_slot_break_r_dataless(name): +def _generate_one_slot_break_r_dataless(name, debug_counter): return f""" MODULE {name}(ins_valid, outs_ready) VAR full : boolean; + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} ASSIGN init(full) := FALSE; @@ -24,15 +27,17 @@ def _generate_one_slot_break_r_dataless(name): DEFINE ins_ready := !full; outs_valid := ins_valid | full; +{generate_buffer_counter(f"{name}__debug_counter", 1) if debug_counter else ""} """ -def _generate_one_slot_break_r(name, data_type): +def _generate_one_slot_break_r(name, data_type, debug_counter): return f""" MODULE {name}(ins, ins_valid, outs_ready) VAR inner_one_slot_break_r : {name}__one_slot_break_r_dataless(ins_valid, outs_ready); data : {data_type}; + {f"debug_counter : {name}__debug_counter(ins_valid, ins_ready, outs_valid, outs_ready);" if debug_counter else ""} ASSIGN init(data) := {data_type.format_constant(0)}; @@ -44,5 +49,6 @@ def _generate_one_slot_break_r(name, data_type): outs_valid := inner_one_slot_break_r.outs_valid; outs := inner_one_slot_break_r.full ? data : ins; -{_generate_one_slot_break_r_dataless(f"{name}__one_slot_break_r_dataless")} +{_generate_one_slot_break_r_dataless(f"{name}__one_slot_break_r_dataless", False)} +{generate_buffer_counter(f"{name}__debug_counter", 1) if debug_counter else ""} """ diff --git a/experimental/tools/unit-generators/smv/generators/support/buffer_counter.py b/experimental/tools/unit-generators/smv/generators/support/buffer_counter.py new file mode 100644 index 0000000000..8f194d5a28 --- /dev/null +++ b/experimental/tools/unit-generators/smv/generators/support/buffer_counter.py @@ -0,0 +1,25 @@ +def generate_buffer_counter(name, slots): + return f""" +MODULE {name}(ins_valid, ins_ready, outs_valid, outs_ready) + VAR + counter : 0..{slots}; + error : boolean; + DEFINE + write_en := ins_valid & ins_ready; + read_en := outs_valid & outs_ready; + ASSIGN + init(counter) := 0; + next(counter) := case + write_en & read_en : counter; + write_en & (counter < {slots}) : counter + 1; + read_en & (counter > 0) : counter - 1; + TRUE : counter; + esac; + init(error) := FALSE; + next(error) := case + write_en & read_en : error; + write_en & (counter = {slots}) : TRUE; + read_en & (counter = 0) : TRUE; + TRUE : error; + esac; +""" diff --git a/experimental/tools/unit-generators/smv/generators/support/utils.py b/experimental/tools/unit-generators/smv/generators/support/utils.py index 9d887a9055..dc6706df66 100644 --- a/experimental/tools/unit-generators/smv/generators/support/utils.py +++ b/experimental/tools/unit-generators/smv/generators/support/utils.py @@ -5,6 +5,7 @@ ATTR_SLOTS = "num_slots" ATTR_TRANSPARENT = "transparent" ATTR_BUFFER_TYPE = "buffer_type" +ATTR_DEBUG_COUNTER = "debug_counter" ATTR_VALUE = "value" ATTR_LATENCY = "latency" ATTR_PREDICATE = "predicate" diff --git a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_dv.py b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_dv.py index bf851f2525..194244ded3 100644 --- a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_dv.py +++ b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_dv.py @@ -1,24 +1,31 @@ from generators.support.signal_manager import generate_concat_signal_manager from generators.support.signal_manager.utils.concat import get_concat_extra_signals_bitwidth +from generators.support.buffer_counter import generate_buffer_counter, generate_buffer_counter_embedding from generators.handshake.buffers.one_slot_break_dv import generate_one_slot_break_dv + def generate_fifo_break_dv(name, params): bitwidth = params["bitwidth"] num_slots = params["num_slots"] extra_signals = params.get("extra_signals", None) + debug_counter = params.get("debug_counter", False) if num_slots == 1: return generate_one_slot_break_dv(name, params) if extra_signals: - return _generate_fifo_break_dv_signal_manager(name, num_slots, bitwidth, extra_signals) + return _generate_fifo_break_dv_signal_manager(name, num_slots, bitwidth, extra_signals, debug_counter) elif bitwidth == 0: - return _generate_fifo_break_dv_dataless(name, num_slots) + return _generate_fifo_break_dv_dataless(name, num_slots, debug_counter) else: - return _generate_fifo_break_dv(name, num_slots, bitwidth) + return _generate_fifo_break_dv(name, num_slots, bitwidth, debug_counter) + +def _generate_fifo_break_dv_dataless(name, num_slots, debug_counter): + debug_counter_name = f"{name}_debug_counter" + dependencies = generate_buffer_counter( + debug_counter_name, num_slots) if debug_counter else "" -def _generate_fifo_break_dv_dataless(name, num_slots): entity = f""" library ieee; @@ -156,14 +163,19 @@ def _generate_fifo_break_dv_dataless(name, num_slots): end if; end if; end process; + + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ - return entity + architecture + return dependencies + entity + architecture +def _generate_fifo_break_dv(name, num_slots, bitwidth, debug_counter): + debug_counter_name = f"{name}_debug_counter" + dependencies = generate_buffer_counter( + debug_counter_name, num_slots) if debug_counter else "" -def _generate_fifo_break_dv(name, num_slots, bitwidth): entity = f""" library ieee; use ieee.std_logic_1164.all; @@ -318,13 +330,15 @@ def _generate_fifo_break_dv(name, num_slots, bitwidth): end if; end if; end process; + + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ - return entity + architecture + return dependencies + entity + architecture -def _generate_fifo_break_dv_signal_manager(name, size, bitwidth, extra_signals): +def _generate_fifo_break_dv_signal_manager(name, size, bitwidth, extra_signals, debug_counter): extra_signals_bitwidth = get_concat_extra_signals_bitwidth(extra_signals) return generate_concat_signal_manager( name, @@ -339,4 +353,4 @@ def _generate_fifo_break_dv_signal_manager(name, size, bitwidth, extra_signals): "extra_signals": extra_signals }], extra_signals, - lambda name: _generate_fifo_break_dv(name, size, bitwidth + extra_signals_bitwidth)) + lambda name: _generate_fifo_break_dv(name, size, bitwidth + extra_signals_bitwidth, debug_counter)) diff --git a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_none.py b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_none.py index ef718c94bf..759326f7fe 100644 --- a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_none.py +++ b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/fifo_break_none.py @@ -1,22 +1,24 @@ from generators.handshake.buffers.fifo_break_dv import generate_fifo_break_dv from generators.support.signal_manager import generate_concat_signal_manager from generators.support.signal_manager.utils.concat import get_concat_extra_signals_bitwidth +from generators.support.buffer_counter import generate_buffer_counter, generate_buffer_counter_embedding def generate_fifo_break_none(name, params): bitwidth = params["bitwidth"] num_slots = params["num_slots"] extra_signals = params.get("extra_signals", None) + debug_counter = params.get("debug_counter", False) if extra_signals: - return _generate_fifo_break_none_signal_manager(name, num_slots, bitwidth, extra_signals) + return _generate_fifo_break_none_signal_manager(name, num_slots, bitwidth, extra_signals, debug_counter) elif bitwidth == 0: - return _generate_fifo_break_none_dataless(name, num_slots) + return _generate_fifo_break_none_dataless(name, num_slots, debug_counter) else: - return _generate_fifo_break_none(name, num_slots, bitwidth) + return _generate_fifo_break_none(name, num_slots, bitwidth, debug_counter) -def _generate_fifo_break_none(name, num_slots, bitwidth): +def _generate_fifo_break_none(name, num_slots, bitwidth, debug_counter): fifo_inner_name = f"{name}_fifo" dependencies = \ generate_fifo_break_dv(fifo_inner_name, @@ -25,6 +27,10 @@ def _generate_fifo_break_none(name, num_slots, bitwidth): "bitwidth": bitwidth, }) + debug_counter_name = f"{name}_debug_counter" + dependencies += generate_buffer_counter( + debug_counter_name, num_slots) if debug_counter else "" + entity = f""" library ieee; use ieee.std_logic_1164.all; @@ -86,18 +92,24 @@ def _generate_fifo_break_none(name, num_slots, bitwidth): outs_valid => fifo_valid, ins_ready => fifo_ready ); + + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ return dependencies + entity + architecture -def _generate_fifo_break_none_dataless(name, num_slots): +def _generate_fifo_break_none_dataless(name, num_slots, debug_counter): fifo_inner_name = f"{name}_fifo" dependencies = generate_fifo_break_dv( fifo_inner_name, {"num_slots": num_slots, - "bitwdith": 0}) + "bitwidth": 0}) + + debug_counter_name = f"{name}_debug_counter" + dependencies += generate_buffer_counter( + debug_counter_name, num_slots) if debug_counter else "" entity = f""" library ieee; @@ -143,13 +155,15 @@ def _generate_fifo_break_none_dataless(name, num_slots): outs_valid => fifo_valid, ins_ready => fifo_ready ); + + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ return dependencies + entity + architecture -def _generate_fifo_break_none_signal_manager(name, size, bitwidth, extra_signals): +def _generate_fifo_break_none_signal_manager(name, size, bitwidth, extra_signals, debug_counter): extra_signals_bitwidth = get_concat_extra_signals_bitwidth(extra_signals) return generate_concat_signal_manager( name, @@ -164,4 +178,4 @@ def _generate_fifo_break_none_signal_manager(name, size, bitwidth, extra_signals "extra_signals": extra_signals }], extra_signals, - lambda name: _generate_fifo_break_none(name, size, bitwidth + extra_signals_bitwidth)) + lambda name: _generate_fifo_break_none(name, size, bitwidth + extra_signals_bitwidth, debug_counter)) diff --git a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dv.py b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dv.py index afe03d6635..3f60b54ace 100644 --- a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dv.py +++ b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dv.py @@ -1,20 +1,26 @@ from generators.support.signal_manager import generate_concat_signal_manager from generators.support.signal_manager.utils.concat import get_concat_extra_signals_bitwidth +from generators.support.buffer_counter import generate_buffer_counter, generate_buffer_counter_embedding def generate_one_slot_break_dv(name, params): bitwidth = params["bitwidth"] extra_signals = params.get("extra_signals", None) + debug_counter = params.get("debug_counter", False) if extra_signals: - return _generate_one_slot_break_dv_signal_manager(name, bitwidth, extra_signals) + return _generate_one_slot_break_dv_signal_manager(name, bitwidth, extra_signals, debug_counter) if bitwidth == 0: - return _generate_one_slot_break_dv_dataless(name) + return _generate_one_slot_break_dv_dataless(name, debug_counter) else: - return _generate_one_slot_break_dv(name, bitwidth) + return _generate_one_slot_break_dv(name, bitwidth, debug_counter) -def _generate_one_slot_break_dv_dataless(name): +def _generate_one_slot_break_dv_dataless(name, debug_counter): + debug_counter_name = f"{name}_debug_counter" + dependencies = generate_buffer_counter( + debug_counter_name, 1) if debug_counter else "" + entity = f""" library ieee; use ieee.std_logic_1164.all; @@ -53,16 +59,21 @@ def _generate_one_slot_break_dv_dataless(name): ins_ready <= not outputValid or outs_ready; outs_valid <= outputValid; + + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ - return entity + architecture + return dependencies + entity + architecture -def _generate_one_slot_break_dv(name, bitwidth): +def _generate_one_slot_break_dv(name, bitwidth, debug_counter): inner_name = f"{name}_inner" + dependencies = _generate_one_slot_break_dv_dataless(inner_name, False) - dependencies = _generate_one_slot_break_dv_dataless(inner_name) + debug_counter_name = f"{name}_debug_counter" + dependencies += generate_buffer_counter( + debug_counter_name, 1) if debug_counter else "" entity = f""" library ieee; @@ -115,13 +126,15 @@ def _generate_one_slot_break_dv(name, bitwidth): ins_ready <= inputReady; regEn <= inputReady and ins_valid; + + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ return dependencies + entity + architecture -def _generate_one_slot_break_dv_signal_manager(name, bitwidth, extra_signals): +def _generate_one_slot_break_dv_signal_manager(name, bitwidth, extra_signals, debug_counter): extra_signals_bitwidth = get_concat_extra_signals_bitwidth(extra_signals) return generate_concat_signal_manager( name, @@ -136,4 +149,4 @@ def _generate_one_slot_break_dv_signal_manager(name, bitwidth, extra_signals): "extra_signals": extra_signals }], extra_signals, - lambda name: _generate_one_slot_break_dv(name, bitwidth + extra_signals_bitwidth)) + lambda name: _generate_one_slot_break_dv(name, bitwidth + extra_signals_bitwidth, debug_counter)) diff --git a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dvr.py b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dvr.py index 0746aa1ebc..75b1b11c90 100644 --- a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dvr.py +++ b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_dvr.py @@ -1,21 +1,26 @@ - from generators.support.signal_manager import generate_concat_signal_manager from generators.support.signal_manager.utils.concat import get_concat_extra_signals_bitwidth +from generators.support.buffer_counter import generate_buffer_counter, generate_buffer_counter_embedding def generate_one_slot_break_dvr(name, params): bitwidth = params["bitwidth"] extra_signals = params.get("extra_signals", None) + debug_counter = params.get("debug_counter", False) if extra_signals: - return _generate_one_slot_break_dvr_signal_manager(name, bitwidth, extra_signals) + return _generate_one_slot_break_dvr_signal_manager(name, bitwidth, extra_signals, debug_counter) if bitwidth == 0: - return _generate_one_slot_break_dvr_dataless(name) + return _generate_one_slot_break_dvr_dataless(name, debug_counter) else: - return _generate_one_slot_break_dvr(name, bitwidth) + return _generate_one_slot_break_dvr(name, bitwidth, debug_counter) + +def _generate_one_slot_break_dvr_dataless(name, debug_counter): + debug_counter_name = f"{name}_debug_counter" + dependencies = generate_buffer_counter( + debug_counter_name, 1) if debug_counter else "" -def _generate_one_slot_break_dvr_dataless(name): entity = f""" library ieee; use ieee.std_logic_1164.all; @@ -71,18 +76,21 @@ def _generate_one_slot_break_dvr_dataless(name): ins_ready <= inputReady; outs_valid <= outputValid; + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; - """ - return entity + architecture + return dependencies + entity + architecture -def _generate_one_slot_break_dvr(name, bitwidth): +def _generate_one_slot_break_dvr(name, bitwidth, debug_counter): inner_name = f"{name}_inner" - dependencies = _generate_one_slot_break_dvr_dataless(inner_name) + debug_counter_name = f"{name}_debug_counter" + dependencies += generate_buffer_counter( + debug_counter_name, 1) if debug_counter else "" + entity = f""" library ieee; use ieee.std_logic_1164.all; @@ -136,13 +144,14 @@ def _generate_one_slot_break_dvr(name, bitwidth): enable <= ins_valid and inputReady; outs <= dataReg; + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ return dependencies + entity + architecture -def _generate_one_slot_break_dvr_signal_manager(name, bitwidth, extra_signals): +def _generate_one_slot_break_dvr_signal_manager(name, bitwidth, extra_signals, debug_counter): extra_signals_bitwidth = get_concat_extra_signals_bitwidth(extra_signals) return generate_concat_signal_manager( name, @@ -157,4 +166,4 @@ def _generate_one_slot_break_dvr_signal_manager(name, bitwidth, extra_signals): "extra_signals": extra_signals }], extra_signals, - lambda name: _generate_one_slot_break_dvr(name, bitwidth + extra_signals_bitwidth)) + lambda name: _generate_one_slot_break_dvr(name, bitwidth + extra_signals_bitwidth, debug_counter)) diff --git a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_r.py b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_r.py index 8651a19ce4..18fcb3a237 100644 --- a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_r.py +++ b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/one_slot_break_r.py @@ -1,20 +1,26 @@ from generators.support.signal_manager import generate_concat_signal_manager from generators.support.signal_manager.utils.concat import get_concat_extra_signals_bitwidth +from generators.support.buffer_counter import generate_buffer_counter, generate_buffer_counter_embedding def generate_one_slot_break_r(name, params): bitwidth = params["bitwidth"] extra_signals = params.get("extra_signals", None) + debug_counter = params.get("debug_counter", False) if extra_signals: - return _generate_one_slot_break_r_signal_manager(name, bitwidth, extra_signals) + return _generate_one_slot_break_r_signal_manager(name, bitwidth, extra_signals, debug_counter) elif bitwidth == 0: - return _generate_one_slot_break_r_dataless(name) + return _generate_one_slot_break_r_dataless(name, debug_counter) else: - return _generate_one_slot_break_r(name, bitwidth) + return _generate_one_slot_break_r(name, bitwidth, debug_counter) -def _generate_one_slot_break_r_dataless(name): +def _generate_one_slot_break_r_dataless(name, debug_counter): + debug_counter_name = f"{name}_debug_counter" + dependencies = generate_buffer_counter( + debug_counter_name, 1) if debug_counter else "" + entity = f""" library ieee; use ieee.std_logic_1164.all; @@ -55,16 +61,22 @@ def _generate_one_slot_break_r_dataless(name): ins_ready <= not fullReg; outs_valid <= outputValid; + + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ - return entity + architecture + return dependencies + entity + architecture -def _generate_one_slot_break_r(name, bitwidth): +def _generate_one_slot_break_r(name, bitwidth, debug_counter): one_slot_break_r_dataless_name = f"{name}_dataless" + dependencies = _generate_one_slot_break_r_dataless( + one_slot_break_r_dataless_name, False) - dependencies = _generate_one_slot_break_r_dataless(one_slot_break_r_dataless_name) + debug_counter_name = f"{name}_debug_counter" + dependencies += generate_buffer_counter( + debug_counter_name, 1) if debug_counter else "" entity = f""" library ieee; @@ -128,13 +140,14 @@ def _generate_one_slot_break_r(name, bitwidth): ins_ready <= regNotFull; + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} end architecture; """ return dependencies + entity + architecture -def _generate_one_slot_break_r_signal_manager(name, bitwidth, extra_signals): +def _generate_one_slot_break_r_signal_manager(name, bitwidth, extra_signals, debug_counter): extra_signals_bitwidth = get_concat_extra_signals_bitwidth(extra_signals) return generate_concat_signal_manager( name, @@ -149,4 +162,4 @@ def _generate_one_slot_break_r_signal_manager(name, bitwidth, extra_signals): "extra_signals": extra_signals }], extra_signals, - lambda name: _generate_one_slot_break_r(name, bitwidth + extra_signals_bitwidth)) + lambda name: _generate_one_slot_break_r(name, bitwidth + extra_signals_bitwidth, debug_counter)) diff --git a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/shift_reg_break_dvr.py b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/shift_reg_break_dvr.py index e04f339beb..e9bd37d8f8 100644 --- a/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/shift_reg_break_dvr.py +++ b/experimental/tools/unit-generators/vhdl/generators/handshake/buffers/shift_reg_break_dvr.py @@ -1,23 +1,27 @@ - from generators.support.signal_manager import generate_concat_signal_manager from generators.support.signal_manager.utils.concat import get_concat_extra_signals_bitwidth +from generators.support.buffer_counter import generate_buffer_counter, generate_buffer_counter_embedding def generate_shift_reg_break_dv(name, params): bitwidth = params["bitwidth"] num_slots = params["num_slots"] - extra_signals = params.get("extra_signals", None) + debug_counter = params.get("debug_counter", False) if extra_signals: - return _generate_shift_reg_break_dv_signal_manager(name, num_slots, bitwidth, extra_signals) + return _generate_shift_reg_break_dv_signal_manager(name, num_slots, bitwidth, extra_signals, debug_counter) if bitwidth == 0: - return _generate_shift_reg_break_dv_dataless(name, num_slots) + return _generate_shift_reg_break_dv_dataless(name, num_slots, debug_counter) else: - return _generate_shift_reg_break_dv(name, num_slots, bitwidth) + return _generate_shift_reg_break_dv(name, num_slots, bitwidth, debug_counter) + +def _generate_shift_reg_break_dv_dataless(name, num_slots, debug_counter): + debug_counter_name = f"{name}_debug_counter" + dependencies = generate_buffer_counter( + debug_counter_name, num_slots) if debug_counter else "" -def _generate_shift_reg_break_dv_dataless(name, num_slots): entity = f""" library ieee; use ieee.std_logic_1164.all; @@ -38,8 +42,8 @@ def _generate_shift_reg_break_dv_dataless(name, num_slots): """ architecture = f""" - -- Architecture of shift_reg_break_dv_dataless - architecture arch of {name} is +-- Architecture of shift_reg_break_dv_dataless +architecture arch of {name} is signal regEn : std_logic; type REG_VALID is array (0 to {num_slots} - 1) of std_logic; @@ -62,24 +66,29 @@ def _generate_shift_reg_break_dv_dataless(name, num_slots): valid_reg(i) <= valid_reg(i - 1); end loop; valid_reg(0) <= ins_valid; - end if; + end if; end if; end if; - end process; + end process; outs_valid <= valid_reg({num_slots} - 1); regEn <= not outs_valid or outs_ready; ins_ready <= regEn; - end architecture; - """ - return entity + architecture + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} +end architecture; +""" + return dependencies + entity + architecture -def _generate_shift_reg_break_dv(name, num_slots, bitwidth): + +def _generate_shift_reg_break_dv(name, num_slots, bitwidth, debug_counter): inner_name = f"{name}_inner" + dependencies = _generate_shift_reg_break_dv_dataless(inner_name, False) - dependencies = _generate_shift_reg_break_dv_dataless(inner_name) + debug_counter_name = f"{name}_debug_counter" + dependencies += generate_buffer_counter( + debug_counter_name, num_slots) if debug_counter else "" entity = f""" @@ -153,13 +162,15 @@ def _generate_shift_reg_break_dv(name, num_slots, bitwidth): ins_ready <= inputReady; outs <= Memory({num_slots} - 1); + {generate_buffer_counter_embedding(debug_counter_name) if debug_counter else ""} + end architecture; """ return dependencies + entity + architecture -def _generate_shift_reg_break_dv_signal_manager(name, num_slots, bitwidth, extra_signals): +def _generate_shift_reg_break_dv_signal_manager(name, num_slots, bitwidth, extra_signals, debug_counter): extra_signals_bitwidth = get_concat_extra_signals_bitwidth(extra_signals) return generate_concat_signal_manager( name, @@ -174,4 +185,4 @@ def _generate_shift_reg_break_dv_signal_manager(name, num_slots, bitwidth, extra "extra_signals": extra_signals }], extra_signals, - lambda name: _generate_shift_reg_break_dv(name, num_slots, bitwidth + extra_signals_bitwidth)) + lambda name: _generate_shift_reg_break_dv(name, num_slots, bitwidth + extra_signals_bitwidth, debug_counter)) diff --git a/experimental/tools/unit-generators/vhdl/generators/support/buffer_counter.py b/experimental/tools/unit-generators/vhdl/generators/support/buffer_counter.py new file mode 100644 index 0000000000..45b83b9426 --- /dev/null +++ b/experimental/tools/unit-generators/vhdl/generators/support/buffer_counter.py @@ -0,0 +1,72 @@ +def generate_buffer_counter(name, slots): + return f""" +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; +use ieee.math_real.all; + +-- Entity of buffer_counter +entity {name} is + port ( + clk, rst : in std_logic; + ins_valid : in std_logic; + ins_ready : in std_logic; + outs_valid : in std_logic; + outs_ready : in std_logic + ); +end entity; + +-- Architecture of buffer_counter +architecture arch of {name} is + constant counter_width : integer := integer(ceil(log2(real(1 + {slots})))); + signal counter : std_logic_vector(counter_width - 1 downto 0); + signal error : std_logic; + signal write_en, read_en : std_logic; +begin + write_en <= ins_valid and ins_ready; + read_en <= outs_valid and outs_ready; + + counter_proc : process(clk, rst) + begin + if rst = '1' then + counter <= "0"; + elsif rising_edge(clk) then + if write_en = '1' and read_en = '1' then + counter <= counter; + elsif write_en = '1' and unsigned(counter) < {slots} then + counter <= std_logic_vector(unsigned(counter) + 1); + elsif read_en = '1' and unsigned(counter) > 0 then + counter <= std_logic_vector(unsigned(counter) - 1); + end if; + end if; + end process; + error_proc : process(clk, rst) + begin + if rst = '1' then + error <= '0'; + elsif rising_edge(clk) then + if write_en = '1' and read_en = '1' then + error <= error; + elsif write_en = '1' and unsigned(counter) = {slots} then + error <= '1'; + elsif read_en = '1' and unsigned(counter) = 0 then + error <= '1'; + end if; + end if; + end process; +end architecture; +""" + + +def generate_buffer_counter_embedding(name): + return f""" + debug_counter : entity work.{name}(arch) + port map( + clk => clk, + rst => rst, + ins_valid => ins_valid, + ins_ready => ins_ready, + outs_valid => outs_valid, + outs_ready => outs_ready + ); +""".lstrip() diff --git a/include/dynamatic/Dialect/Handshake/HandshakeOps.td b/include/dynamatic/Dialect/Handshake/HandshakeOps.td index a68af2eb0b..fec05d1809 100644 --- a/include/dynamatic/Dialect/Handshake/HandshakeOps.td +++ b/include/dynamatic/Dialect/Handshake/HandshakeOps.td @@ -225,7 +225,8 @@ def BufferOp : Handshake_Op<"buffer", [ let arguments = (ins HandshakeType:$operand, Handshake_BufferTypeAttr:$bufferType, - ConfinedAttr]>:$numSlots + ConfinedAttr]>:$numSlots, + BoolAttr:$debugCounter ); let results = (outs HandshakeType:$result); @@ -274,6 +275,7 @@ def BufferOp : Handshake_Op<"buffer", [ $_state.addTypes(operand.getType()); $_state.addAttribute("bufferType", ::dynamatic::handshake::BufferTypeAttr::get($_builder.getContext(), bufferType)); $_state.addAttribute("numSlots", $_builder.getI64IntegerAttr(numSlots)); + $_state.addAttribute("debugCounter", $_builder.getBoolAttr(false)); }]> ]; diff --git a/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp b/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp index 2093537ded..59309352ae 100644 --- a/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp +++ b/lib/Conversion/HandshakeToHW/HandshakeToHW.cpp @@ -552,6 +552,7 @@ ModuleDiscriminator::ModuleDiscriminator(Operation *op) { addUnsigned("NUM_SLOTS", bufferOp.getNumSlots()); addString("BUFFER_TYPE", stringifyEnum(bufferOp.getBufferType())); + addBoolean("DEBUG_COUNTER", bufferOp.getDebugCounter()); }) .Case( [&](handshake::ConditionalBranchOp cbrOp) { diff --git a/test/Transforms/HandshakeOptimizeBitwidths/handshake-backward.mlir b/test/Transforms/HandshakeOptimizeBitwidths/handshake-backward.mlir index 868863c2be..9c09c5bcf3 100644 --- a/test/Transforms/HandshakeOptimizeBitwidths/handshake-backward.mlir +++ b/test/Transforms/HandshakeOptimizeBitwidths/handshake-backward.mlir @@ -122,11 +122,11 @@ handshake.func @condBrBW(%arg0: !handshake.channel, %cond: !handshake.chann // CHECK-SAME: %[[VAL_0:.*]]: !handshake.channel, // CHECK-SAME: %[[VAL_1:.*]]: !handshake.control<>, ...) -> !handshake.channel attributes {argNames = ["arg0", "start"], resNames = ["out0"]} { // CHECK: %[[VAL_2:.*]] = trunci %[[VAL_0]] {handshake.bb = 0 : ui32} : to -// CHECK: %[[VAL_3:.*]] = buffer %[[VAL_2]], bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 : +// CHECK: %[[VAL_3:.*]] = buffer %[[VAL_2]], bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 {debugCounter = false} : // CHECK: end %[[VAL_3]] : // CHECK: } handshake.func @bufferBW(%arg0: !handshake.channel, %start: !handshake.control<>) -> !handshake.channel { - %buf = buffer %arg0, bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 : + %buf = buffer %arg0, bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 {debugCounter = false} : %trunc = trunci %buf : to end %trunc : } diff --git a/test/Transforms/HandshakeOptimizeBitwidths/handshake-forward.mlir b/test/Transforms/HandshakeOptimizeBitwidths/handshake-forward.mlir index c2775d5d10..27c7d76226 100644 --- a/test/Transforms/HandshakeOptimizeBitwidths/handshake-forward.mlir +++ b/test/Transforms/HandshakeOptimizeBitwidths/handshake-forward.mlir @@ -120,12 +120,12 @@ handshake.func @condBrFw(%arg0: !handshake.channel, %cond: !handshake.chann // CHECK-LABEL: handshake.func @bufferFW( // CHECK-SAME: %[[VAL_0:.*]]: !handshake.channel, // CHECK-SAME: %[[VAL_1:.*]]: !handshake.control<>, ...) -> !handshake.channel attributes {argNames = ["arg0", "start"], resNames = ["out0"]} { -// CHECK: %[[VAL_2:.*]] = buffer %[[VAL_0]], bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 : +// CHECK: %[[VAL_2:.*]] = buffer %[[VAL_0]], bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 {debugCounter = false} : // CHECK: %[[VAL_3:.*]] = extsi %[[VAL_2]] : to // CHECK: end %[[VAL_3]] : // CHECK: } handshake.func @bufferFW(%arg0: !handshake.channel, %start: !handshake.control<>) -> !handshake.channel { %ext0 = extsi %arg0 : to - %buf = buffer %ext0, bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 : + %buf = buffer %ext0, bufferType = ONE_SLOT_BREAK_DV, numSlots = 1 {debugCounter = false} : end %buf : }