Skip to content

Commit 4a35c97

Browse files
chinglee-iotaggarg
chinglee-iot
and
aggarg
authored
Remove __NVIC_PRIO_BITS and configPRIO_BITS check in port (#683)
* Remove __NVIC_PRIO_BITS and configPRIO_BITS check in CM3, CM4 and ARMv8. * Add hardware not implemented bits check. These bits should be zero. --------- Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>
1 parent d3c289f commit 4a35c97

File tree

37 files changed

+148
-961
lines changed

37 files changed

+148
-961
lines changed

‎portable/ARMv8M/non_secure/port.c‎

Lines changed: 4 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11281128
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
11291129
configASSERT( ucMaxSysCallPriority );
11301130

1131+
/* Check that the bits not implemented bits in hardware are zero in
1132+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
1133+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
1134+
11311135
/* Calculate the maximum acceptable priority group value for the number
11321136
* of bits read back. */
11331137

@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11641168
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
11651169
}
11661170

1167-
/* The interrupt priority bits are not modelled in QEMU and the assert that
1168-
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
1169-
* Therefore, this assert is not adding any value for QEMU targets. The config
1170-
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
1171-
* `FreeRTOSConfig.h` for QEMU targets. */
1172-
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
1173-
{
1174-
#ifdef __NVIC_PRIO_BITS
1175-
{
1176-
/*
1177-
* Check that the number of implemented priority bits queried from
1178-
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
1179-
*/
1180-
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
1181-
}
1182-
#endif /* __NVIC_PRIO_BITS */
1183-
1184-
#ifdef configPRIO_BITS
1185-
{
1186-
/*
1187-
* Check that the number of implemented priority bits queried from
1188-
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
1189-
*/
1190-
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
1191-
}
1192-
#endif /* configPRIO_BITS */
1193-
}
1194-
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
1195-
11961171
/* Shift the priority group value back to its position within the AIRCR
11971172
* register. */
11981173
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

‎portable/CCS/ARM_CM3/port.c‎

Lines changed: 4 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -249,6 +249,10 @@ BaseType_t xPortStartScheduler( void )
249249
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
250250
configASSERT( ucMaxSysCallPriority );
251251

252+
/* Check that the bits not implemented bits in hardware are zero in
253+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
254+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
255+
252256
/* Calculate the maximum acceptable priority group value for the number
253257
* of bits read back. */
254258

@@ -285,28 +289,6 @@ BaseType_t xPortStartScheduler( void )
285289
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
286290
}
287291

288-
#ifdef __NVIC_PRIO_BITS
289-
{
290-
/*
291-
* Check that the number of implemented priority bits queried from
292-
* hardware is at least as many as specified in the CMSIS
293-
* __NVIC_PRIO_BITS configuration macro.
294-
*/
295-
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
296-
}
297-
#endif
298-
299-
#ifdef configPRIO_BITS
300-
{
301-
/*
302-
* Check that the number of implemented priority bits queried from
303-
* hardware is at least as many as specified in the FreeRTOS
304-
* configPRIO_BITS configuration macro.
305-
*/
306-
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
307-
}
308-
#endif
309-
310292
/* Shift the priority group value back to its position within the AIRCR
311293
* register. */
312294
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

‎portable/CCS/ARM_CM4F/port.c‎

Lines changed: 4 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -268,6 +268,10 @@ BaseType_t xPortStartScheduler( void )
268268
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
269269
configASSERT( ucMaxSysCallPriority );
270270

271+
/* Check that the bits not implemented bits in hardware are zero in
272+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
273+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
274+
271275
/* Calculate the maximum acceptable priority group value for the number
272276
* of bits read back. */
273277

@@ -304,28 +308,6 @@ BaseType_t xPortStartScheduler( void )
304308
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
305309
}
306310

307-
#ifdef __NVIC_PRIO_BITS
308-
{
309-
/*
310-
* Check that the number of implemented priority bits queried from
311-
* hardware is at least as many as specified in the CMSIS
312-
* __NVIC_PRIO_BITS configuration macro.
313-
*/
314-
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
315-
}
316-
#endif
317-
318-
#ifdef configPRIO_BITS
319-
{
320-
/*
321-
* Check that the number of implemented priority bits queried from
322-
* hardware is at least as many as specified in the FreeRTOS
323-
* configPRIO_BITS configuration macro.
324-
*/
325-
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
326-
}
327-
#endif
328-
329311
/* Shift the priority group value back to its position within the AIRCR
330312
* register. */
331313
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

‎portable/GCC/ARM_CM23/non_secure/port.c‎

Lines changed: 4 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11281128
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
11291129
configASSERT( ucMaxSysCallPriority );
11301130

1131+
/* Check that the bits not implemented bits in hardware are zero in
1132+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
1133+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
1134+
11311135
/* Calculate the maximum acceptable priority group value for the number
11321136
* of bits read back. */
11331137

@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11641168
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
11651169
}
11661170

1167-
/* The interrupt priority bits are not modelled in QEMU and the assert that
1168-
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
1169-
* Therefore, this assert is not adding any value for QEMU targets. The config
1170-
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
1171-
* `FreeRTOSConfig.h` for QEMU targets. */
1172-
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
1173-
{
1174-
#ifdef __NVIC_PRIO_BITS
1175-
{
1176-
/*
1177-
* Check that the number of implemented priority bits queried from
1178-
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
1179-
*/
1180-
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
1181-
}
1182-
#endif /* __NVIC_PRIO_BITS */
1183-
1184-
#ifdef configPRIO_BITS
1185-
{
1186-
/*
1187-
* Check that the number of implemented priority bits queried from
1188-
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
1189-
*/
1190-
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
1191-
}
1192-
#endif /* configPRIO_BITS */
1193-
}
1194-
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
1195-
11961171
/* Shift the priority group value back to its position within the AIRCR
11971172
* register. */
11981173
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

‎portable/GCC/ARM_CM23_NTZ/non_secure/port.c‎

Lines changed: 4 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11281128
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
11291129
configASSERT( ucMaxSysCallPriority );
11301130

1131+
/* Check that the bits not implemented bits in hardware are zero in
1132+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
1133+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
1134+
11311135
/* Calculate the maximum acceptable priority group value for the number
11321136
* of bits read back. */
11331137

@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11641168
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
11651169
}
11661170

1167-
/* The interrupt priority bits are not modelled in QEMU and the assert that
1168-
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
1169-
* Therefore, this assert is not adding any value for QEMU targets. The config
1170-
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
1171-
* `FreeRTOSConfig.h` for QEMU targets. */
1172-
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
1173-
{
1174-
#ifdef __NVIC_PRIO_BITS
1175-
{
1176-
/*
1177-
* Check that the number of implemented priority bits queried from
1178-
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
1179-
*/
1180-
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
1181-
}
1182-
#endif /* __NVIC_PRIO_BITS */
1183-
1184-
#ifdef configPRIO_BITS
1185-
{
1186-
/*
1187-
* Check that the number of implemented priority bits queried from
1188-
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
1189-
*/
1190-
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
1191-
}
1192-
#endif /* configPRIO_BITS */
1193-
}
1194-
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
1195-
11961171
/* Shift the priority group value back to its position within the AIRCR
11971172
* register. */
11981173
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

‎portable/GCC/ARM_CM3/port.c‎

Lines changed: 4 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -292,6 +292,10 @@ BaseType_t xPortStartScheduler( void )
292292
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
293293
configASSERT( ucMaxSysCallPriority );
294294

295+
/* Check that the bits not implemented bits in hardware are zero in
296+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
297+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
298+
295299
/* Calculate the maximum acceptable priority group value for the number
296300
* of bits read back. */
297301

@@ -328,28 +332,6 @@ BaseType_t xPortStartScheduler( void )
328332
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
329333
}
330334

331-
#ifdef __NVIC_PRIO_BITS
332-
{
333-
/*
334-
* Check that the number of implemented priority bits queried from
335-
* hardware is at least as many as specified in the CMSIS
336-
* __NVIC_PRIO_BITS configuration macro.
337-
*/
338-
configASSERT( ulImplementedPrioBits >= __NVIC_PRIO_BITS );
339-
}
340-
#endif
341-
342-
#ifdef configPRIO_BITS
343-
{
344-
/*
345-
* Check that the number of implemented priority bits queried from
346-
* hardware is at least as many as specified in the FreeRTOS
347-
* configPRIO_BITS configuration macro.
348-
*/
349-
configASSERT( ulImplementedPrioBits >= configPRIO_BITS );
350-
}
351-
#endif
352-
353335
/* Shift the priority group value back to its position within the AIRCR
354336
* register. */
355337
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

‎portable/GCC/ARM_CM33/non_secure/port.c‎

Lines changed: 4 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11281128
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
11291129
configASSERT( ucMaxSysCallPriority );
11301130

1131+
/* Check that the bits not implemented bits in hardware are zero in
1132+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
1133+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
1134+
11311135
/* Calculate the maximum acceptable priority group value for the number
11321136
* of bits read back. */
11331137

@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11641168
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
11651169
}
11661170

1167-
/* The interrupt priority bits are not modelled in QEMU and the assert that
1168-
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
1169-
* Therefore, this assert is not adding any value for QEMU targets. The config
1170-
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
1171-
* `FreeRTOSConfig.h` for QEMU targets. */
1172-
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
1173-
{
1174-
#ifdef __NVIC_PRIO_BITS
1175-
{
1176-
/*
1177-
* Check that the number of implemented priority bits queried from
1178-
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
1179-
*/
1180-
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
1181-
}
1182-
#endif /* __NVIC_PRIO_BITS */
1183-
1184-
#ifdef configPRIO_BITS
1185-
{
1186-
/*
1187-
* Check that the number of implemented priority bits queried from
1188-
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
1189-
*/
1190-
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
1191-
}
1192-
#endif /* configPRIO_BITS */
1193-
}
1194-
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
1195-
11961171
/* Shift the priority group value back to its position within the AIRCR
11971172
* register. */
11981173
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

‎portable/GCC/ARM_CM33_NTZ/non_secure/port.c‎

Lines changed: 4 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -1128,6 +1128,10 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11281128
* See https://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
11291129
configASSERT( ucMaxSysCallPriority );
11301130

1131+
/* Check that the bits not implemented bits in hardware are zero in
1132+
* configMAX_SYSCALL_INTERRUPT_PRIORITY. */
1133+
configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY & ( ~ucMaxPriorityValue ) ) == 0U );
1134+
11311135
/* Calculate the maximum acceptable priority group value for the number
11321136
* of bits read back. */
11331137

@@ -1164,35 +1168,6 @@ BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
11641168
ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS - ulImplementedPrioBits;
11651169
}
11661170

1167-
/* The interrupt priority bits are not modelled in QEMU and the assert that
1168-
* checks the number of implemented bits and __NVIC_PRIO_BITS will always fail.
1169-
* Therefore, this assert is not adding any value for QEMU targets. The config
1170-
* option `configDISABLE_INTERRUPT_PRIO_BITS_CHECK` should be defined in the
1171-
* `FreeRTOSConfig.h` for QEMU targets. */
1172-
#ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK
1173-
{
1174-
#ifdef __NVIC_PRIO_BITS
1175-
{
1176-
/*
1177-
* Check that the number of implemented priority bits queried from
1178-
* hardware is equal to the CMSIS __NVIC_PRIO_BITS configuration macro.
1179-
*/
1180-
configASSERT( ulImplementedPrioBits == __NVIC_PRIO_BITS );
1181-
}
1182-
#endif /* __NVIC_PRIO_BITS */
1183-
1184-
#ifdef configPRIO_BITS
1185-
{
1186-
/*
1187-
* Check that the number of implemented priority bits queried from
1188-
* hardware is equal to the FreeRTOS configPRIO_BITS configuration macro.
1189-
*/
1190-
configASSERT( ulImplementedPrioBits == configPRIO_BITS );
1191-
}
1192-
#endif /* configPRIO_BITS */
1193-
}
1194-
#endif /* #ifndef configDISABLE_INTERRUPT_PRIO_BITS_CHECK */
1195-
11961171
/* Shift the priority group value back to its position within the AIRCR
11971172
* register. */
11981173
ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;

0 commit comments

Comments
 (0)