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cpu_threaded.c
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3508 lines (3372 loc) · 255 KB
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/* gameplaySP
*
* Copyright (C) 2006 Exophase <exophase@gmail.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
*/
// Not-so-important todo:
// - stm reglist writeback when base is in the list needs adjustment
// - block memory needs psr swapping and user mode reg swapping
#include "common.h"
u8 rom_translation_cache[ROM_TRANSLATION_CACHE_SIZE];
u8 *rom_translation_ptr = rom_translation_cache;
u8 ram_translation_cache[RAM_TRANSLATION_CACHE_SIZE];
u8 *ram_translation_ptr = ram_translation_cache;
u32 iwram_code_min = 0xFFFFFFFF;
u32 iwram_code_max = 0xFFFFFFFF;
u32 ewram_code_min = 0xFFFFFFFF;
u32 ewram_code_max = 0xFFFFFFFF;
u8 bios_translation_cache[BIOS_TRANSLATION_CACHE_SIZE];
u8 *bios_translation_ptr = bios_translation_cache;
u32 *rom_branch_hash[ROM_BRANCH_HASH_SIZE];
// Default
u32 idle_loop_target_pc = 0xFFFFFFFF;
u32 force_pc_update_target = 0xFFFFFFFF;
u32 translation_gate_target_pc[MAX_TRANSLATION_GATES];
u32 translation_gate_targets = 0;
u32 iwram_stack_optimize = 1;
u32 allow_smc_ram_u8 = 1;
u32 allow_smc_ram_u16 = 1;
u32 allow_smc_ram_u32 = 1;
typedef struct
{
u8 *block_offset;
u16 flag_data;
u8 condition;
u8 update_cycles;
} block_data_type;
typedef struct
{
u32 branch_target;
u8 *branch_source;
} block_exit_type;
extern u8 bit_count[256];
#define arm_decode_data_proc_reg() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_data_proc_imm() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 imm = opcode & 0xFF; \
u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \
#define arm_decode_psr_reg() \
u32 psr_field = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_psr_imm() \
u32 psr_field = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 imm = opcode & 0xFF; \
u32 imm_ror = ((opcode >> 8) & 0x0F) * 2 \
#define arm_decode_branchx() \
u32 rn = opcode & 0x0F \
#define arm_decode_multiply() \
u32 rd = (opcode >> 16) & 0x0F; \
u32 rn = (opcode >> 12) & 0x0F; \
u32 rs = (opcode >> 8) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_multiply_long() \
u32 rdhi = (opcode >> 16) & 0x0F; \
u32 rdlo = (opcode >> 12) & 0x0F; \
u32 rs = (opcode >> 8) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_swap() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_half_trans_r() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_half_trans_of() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 offset = ((opcode >> 4) & 0xF0) | (opcode & 0x0F) \
#define arm_decode_data_trans_imm() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 offset = opcode & 0x0FFF \
#define arm_decode_data_trans_reg() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 rd = (opcode >> 12) & 0x0F; \
u32 rm = opcode & 0x0F \
#define arm_decode_block_trans() \
u32 rn = (opcode >> 16) & 0x0F; \
u32 reg_list = opcode & 0xFFFF \
#define arm_decode_branch() \
s32 offset = ((s32)(opcode & 0xFFFFFF) << 8) >> 6 \
#define thumb_decode_shift() \
u32 imm = (opcode >> 6) & 0x1F; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_add_sub() \
u32 rn = (opcode >> 6) & 0x07; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_add_sub_imm() \
u32 imm = (opcode >> 6) & 0x07; \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_imm() \
u32 imm = opcode & 0xFF \
#define thumb_decode_alu_op() \
u32 rs = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_hireg_op() \
u32 rs = (opcode >> 3) & 0x0F; \
u32 rd = ((opcode >> 4) & 0x08) | (opcode & 0x07) \
#define thumb_decode_mem_reg() \
u32 ro = (opcode >> 6) & 0x07; \
u32 rb = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_mem_imm() \
u32 imm = (opcode >> 6) & 0x1F; \
u32 rb = (opcode >> 3) & 0x07; \
u32 rd = opcode & 0x07 \
#define thumb_decode_add_sp() \
u32 imm = opcode & 0x7F \
#define thumb_decode_rlist() \
u32 reg_list = opcode & 0xFF \
#define thumb_decode_branch_cond() \
s32 offset = (s8)(opcode & 0xFF) \
#define thumb_decode_swi() \
u32 comment = opcode & 0xFF \
#define thumb_decode_branch() \
u32 offset = opcode & 0x07FF \
#ifdef PSP_BUILD
#include "psp/mips_emit.h"
#elif defined(ARM_ARCH)
#include "arm/arm_emit.h"
#else
#include "x86/x86_emit.h"
#endif
#define check_pc_region(pc) \
new_pc_region = (pc >> 15); \
if(new_pc_region != pc_region) \
{ \
pc_region = new_pc_region; \
pc_address_block = memory_map_read[new_pc_region]; \
\
if(pc_address_block == NULL) \
pc_address_block = load_gamepak_page(pc_region & 0x3FF); \
} \
#define translate_arm_instruction() \
check_pc_region(pc); \
opcode = address32(pc_address_block, (pc & 0x7FFF)); \
condition = block_data[block_data_position].condition; \
\
if((condition != last_condition) || (condition >= 0x20)) \
{ \
if((last_condition & 0x0F) != 0x0E) \
{ \
generate_branch_patch_conditional(backpatch_address, translation_ptr); \
} \
\
last_condition = condition; \
\
condition &= 0x0F; \
\
if(condition != 0x0E) \
{ \
arm_conditional_block_header(); \
} \
} \
\
switch((opcode >> 20) & 0xFF) \
{ \
case 0x00: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], -rm */ \
arm_access_memory(store, down, post, u16, half_reg); \
} \
else \
{ \
/* MUL rd, rm, rs */ \
arm_multiply(no, no); \
} \
} \
else \
{ \
/* AND rd, rn, reg_op */ \
arm_data_proc(and, reg, no_flags); \
} \
break; \
\
case 0x01: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* MULS rd, rm, rs */ \
arm_multiply(no, yes); \
break; \
\
case 1: \
/* LDRH rd, [rn], -rm */ \
arm_access_memory(load, down, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -rm */ \
arm_access_memory(load, down, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -rm */ \
arm_access_memory(load, down, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ANDS rd, rn, reg_op */ \
arm_data_proc(ands, reg_flags, flags); \
} \
break; \
\
case 0x02: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], -rm */ \
arm_access_memory(store, down, post, u16, half_reg); \
} \
else \
{ \
/* MLA rd, rm, rs, rn */ \
arm_multiply(yes, no); \
} \
} \
else \
{ \
/* EOR rd, rn, reg_op */ \
arm_data_proc(eor, reg, no_flags); \
} \
break; \
\
case 0x03: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* MLAS rd, rm, rs, rn */ \
arm_multiply(yes, yes); \
break; \
\
case 1: \
/* LDRH rd, [rn], -rm */ \
arm_access_memory(load, down, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -rm */ \
arm_access_memory(load, down, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -rm */ \
arm_access_memory(load, down, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* EORS rd, rn, reg_op */ \
arm_data_proc(eors, reg_flags, flags); \
} \
break; \
\
case 0x04: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn], -imm */ \
arm_access_memory(store, down, post, u16, half_imm); \
} \
else \
{ \
/* SUB rd, rn, reg_op */ \
arm_data_proc(sub, reg, no_flags); \
} \
break; \
\
case 0x05: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn], -imm */ \
arm_access_memory(load, down, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -imm */ \
arm_access_memory(load, down, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -imm */ \
arm_access_memory(load, down, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* SUBS rd, rn, reg_op */ \
arm_data_proc(subs, reg, flags); \
} \
break; \
\
case 0x06: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn], -imm */ \
arm_access_memory(store, down, post, u16, half_imm); \
} \
else \
{ \
/* RSB rd, rn, reg_op */ \
arm_data_proc(rsb, reg, no_flags); \
} \
break; \
\
case 0x07: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn], -imm */ \
arm_access_memory(load, down, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], -imm */ \
arm_access_memory(load, down, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], -imm */ \
arm_access_memory(load, down, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* RSBS rd, rn, reg_op */ \
arm_data_proc(rsbs, reg, flags); \
} \
break; \
\
case 0x08: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +rm */ \
arm_access_memory(store, up, post, u16, half_reg); \
} \
else \
{ \
/* UMULL rd, rm, rs */ \
arm_multiply_long(u64, no, no); \
} \
} \
else \
{ \
/* ADD rd, rn, reg_op */ \
arm_data_proc(add, reg, no_flags); \
} \
break; \
\
case 0x09: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* UMULLS rdlo, rdhi, rm, rs */ \
arm_multiply_long(u64, no, yes); \
break; \
\
case 1: \
/* LDRH rd, [rn], +rm */ \
arm_access_memory(load, up, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +rm */ \
arm_access_memory(load, up, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +rm */ \
arm_access_memory(load, up, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ADDS rd, rn, reg_op */ \
arm_data_proc(adds, reg, flags); \
} \
break; \
\
case 0x0A: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +rm */ \
arm_access_memory(store, up, post, u16, half_reg); \
} \
else \
{ \
/* UMLAL rd, rm, rs */ \
arm_multiply_long(u64_add, yes, no); \
} \
} \
else \
{ \
/* ADC rd, rn, reg_op */ \
arm_data_proc(adc, reg, no_flags); \
} \
break; \
\
case 0x0B: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* UMLALS rdlo, rdhi, rm, rs */ \
arm_multiply_long(u64_add, yes, yes); \
break; \
\
case 1: \
/* LDRH rd, [rn], +rm */ \
arm_access_memory(load, up, post, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +rm */ \
arm_access_memory(load, up, post, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +rm */ \
arm_access_memory(load, up, post, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ADCS rd, rn, reg_op */ \
arm_data_proc(adcs, reg, flags); \
} \
break; \
\
case 0x0C: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +imm */ \
arm_access_memory(store, up, post, u16, half_imm); \
} \
else \
{ \
/* SMULL rd, rm, rs */ \
arm_multiply_long(s64, no, no); \
} \
} \
else \
{ \
/* SBC rd, rn, reg_op */ \
arm_data_proc(sbc, reg, no_flags); \
} \
break; \
\
case 0x0D: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* SMULLS rdlo, rdhi, rm, rs */ \
arm_multiply_long(s64, no, yes); \
break; \
\
case 1: \
/* LDRH rd, [rn], +imm */ \
arm_access_memory(load, up, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +imm */ \
arm_access_memory(load, up, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +imm */ \
arm_access_memory(load, up, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* SBCS rd, rn, reg_op */ \
arm_data_proc(sbcs, reg, flags); \
} \
break; \
\
case 0x0E: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn], +imm */ \
arm_access_memory(store, up, post, u16, half_imm); \
} \
else \
{ \
/* SMLAL rd, rm, rs */ \
arm_multiply_long(s64_add, yes, no); \
} \
} \
else \
{ \
/* RSC rd, rn, reg_op */ \
arm_data_proc(rsc, reg, no_flags); \
} \
break; \
\
case 0x0F: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 0: \
/* SMLALS rdlo, rdhi, rm, rs */ \
arm_multiply_long(s64_add, yes, yes); \
break; \
\
case 1: \
/* LDRH rd, [rn], +imm */ \
arm_access_memory(load, up, post, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn], +imm */ \
arm_access_memory(load, up, post, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn], +imm */ \
arm_access_memory(load, up, post, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* RSCS rd, rn, reg_op */ \
arm_data_proc(rscs, reg, flags); \
} \
break; \
\
case 0x10: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn - rm] */ \
arm_access_memory(store, down, pre, u16, half_reg); \
} \
else \
{ \
/* SWP rd, rm, [rn] */ \
arm_swap(u32); \
} \
} \
else \
{ \
/* MRS rd, cpsr */ \
arm_psr(reg, read, cpsr); \
} \
break; \
\
case 0x11: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - rm] */ \
arm_access_memory(load, down, pre, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn - rm] */ \
arm_access_memory(load, down, pre, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn - rm] */ \
arm_access_memory(load, down, pre, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* TST rd, rn, reg_op */ \
arm_data_proc_test(tst, reg_flags); \
} \
break; \
\
case 0x12: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn - rm]! */ \
arm_access_memory(store, down, pre_wb, u16, half_reg); \
} \
else \
{ \
if(opcode & 0x10) \
{ \
/* BX rn */ \
arm_bx(); \
} \
else \
{ \
/* MSR cpsr, rm */ \
arm_psr(reg, store, cpsr); \
} \
} \
break; \
\
case 0x13: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - rm]! */ \
arm_access_memory(load, down, pre_wb, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn - rm]! */ \
arm_access_memory(load, down, pre_wb, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn - rm]! */ \
arm_access_memory(load, down, pre_wb, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* TEQ rd, rn, reg_op */ \
arm_data_proc_test(teq, reg_flags); \
} \
break; \
\
case 0x14: \
if((opcode & 0x90) == 0x90) \
{ \
if(opcode & 0x20) \
{ \
/* STRH rd, [rn - imm] */ \
arm_access_memory(store, down, pre, u16, half_imm); \
} \
else \
{ \
/* SWPB rd, rm, [rn] */ \
arm_swap(u8); \
} \
} \
else \
{ \
/* MRS rd, spsr */ \
arm_psr(reg, read, spsr); \
} \
break; \
\
case 0x15: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - imm] */ \
arm_access_memory(load, down, pre, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn - imm] */ \
arm_access_memory(load, down, pre, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn - imm] */ \
arm_access_memory(load, down, pre, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* CMP rn, reg_op */ \
arm_data_proc_test(cmp, reg); \
} \
break; \
\
case 0x16: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn - imm]! */ \
arm_access_memory(store, down, pre_wb, u16, half_imm); \
} \
else \
{ \
/* MSR spsr, rm */ \
arm_psr(reg, store, spsr); \
} \
break; \
\
case 0x17: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn - imm]! */ \
arm_access_memory(load, down, pre_wb, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn - imm]! */ \
arm_access_memory(load, down, pre_wb, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn - imm]! */ \
arm_access_memory(load, down, pre_wb, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* CMN rd, rn, reg_op */ \
arm_data_proc_test(cmn, reg); \
} \
break; \
\
case 0x18: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn + rm] */ \
arm_access_memory(store, up, pre, u16, half_reg); \
} \
else \
{ \
/* ORR rd, rn, reg_op */ \
arm_data_proc(orr, reg, no_flags); \
} \
break; \
\
case 0x19: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn + rm] */ \
arm_access_memory(load, up, pre, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn + rm] */ \
arm_access_memory(load, up, pre, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn + rm] */ \
arm_access_memory(load, up, pre, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* ORRS rd, rn, reg_op */ \
arm_data_proc(orrs, reg_flags, flags); \
} \
break; \
\
case 0x1A: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn + rm]! */ \
arm_access_memory(store, up, pre_wb, u16, half_reg); \
} \
else \
{ \
/* MOV rd, reg_op */ \
arm_data_proc_unary(mov, reg, no_flags); \
} \
break; \
\
case 0x1B: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn + rm]! */ \
arm_access_memory(load, up, pre_wb, u16, half_reg); \
break; \
\
case 2: \
/* LDRSB rd, [rn + rm]! */ \
arm_access_memory(load, up, pre_wb, s8, half_reg); \
break; \
\
case 3: \
/* LDRSH rd, [rn + rm]! */ \
arm_access_memory(load, up, pre_wb, s16, half_reg); \
break; \
} \
} \
else \
{ \
/* MOVS rd, reg_op */ \
arm_data_proc_unary(movs, reg_flags, flags); \
} \
break; \
\
case 0x1C: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn + imm] */ \
arm_access_memory(store, up, pre, u16, half_imm); \
} \
else \
{ \
/* BIC rd, rn, reg_op */ \
arm_data_proc(bic, reg, no_flags); \
} \
break; \
\
case 0x1D: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn + imm] */ \
arm_access_memory(load, up, pre, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn + imm] */ \
arm_access_memory(load, up, pre, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn + imm] */ \
arm_access_memory(load, up, pre, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* BICS rd, rn, reg_op */ \
arm_data_proc(bics, reg_flags, flags); \
} \
break; \
\
case 0x1E: \
if((opcode & 0x90) == 0x90) \
{ \
/* STRH rd, [rn + imm]! */ \
arm_access_memory(store, up, pre_wb, u16, half_imm); \
} \
else \
{ \
/* MVN rd, reg_op */ \
arm_data_proc_unary(mvn, reg, no_flags); \
} \
break; \
\
case 0x1F: \
if((opcode & 0x90) == 0x90) \
{ \
switch((opcode >> 5) & 0x03) \
{ \
case 1: \
/* LDRH rd, [rn + imm]! */ \
arm_access_memory(load, up, pre_wb, u16, half_imm); \
break; \
\
case 2: \
/* LDRSB rd, [rn + imm]! */ \
arm_access_memory(load, up, pre_wb, s8, half_imm); \
break; \
\
case 3: \
/* LDRSH rd, [rn + imm]! */ \
arm_access_memory(load, up, pre_wb, s16, half_imm); \
break; \
} \
} \
else \
{ \
/* MVNS rd, rn, reg_op */ \
arm_data_proc_unary(mvns, reg_flags, flags); \
} \
break; \
\
case 0x20: \
/* AND rd, rn, imm */ \
arm_data_proc(and, imm, no_flags); \
break; \
\