diff --git a/README b/README index 0dc88f5..db4dad4 100644 --- a/README +++ b/README @@ -1,3 +1,7 @@ +*io.cc, extio.h/cc were modified to output Cacti IO values +io.cc - output_data_csv() to output CACTI IO +extio.h/cc - to return values rather than just print + ----------------------------------------------------------- diff --git a/cacti.mk b/cacti.mk index b675d75..97181b5 100644 --- a/cacti.mk +++ b/cacti.mk @@ -13,7 +13,7 @@ INCS = -lm ifeq ($(TAG),dbg) DBG = -Wall - OPT = -ggdb -g -O0 -DNTHREADS=1 -gstabs+ + OPT = -ggdb -g -O0 -DNTHREADS=1 else DBG = OPT = -g -msse2 -mfpmath=sse -DNTHREADS=$(NTHREADS) @@ -21,8 +21,8 @@ endif #CXXFLAGS = -Wall -Wno-unknown-pragmas -Winline $(DBG) $(OPT) CXXFLAGS = -Wno-unknown-pragmas $(DBG) $(OPT) -CXX = g++ -m64 -CC = gcc -m64 +CXX = g++-13 -m64 +CC = gcc-13 -m64 SRCS = area.cc bank.cc mat.cc main.cc Ucache.cc io.cc technology.cc basic_circuit.cc parameter.cc \ decoder.cc component.cc uca.cc subarray.cc wire.cc htree2.cc extio.cc extio_technology.cc \ @@ -48,6 +48,4 @@ obj_$(TAG)/%.o : %.cc $(CXX) $(CXXFLAGS) -c $< -o $@ clean: - -rm -f *.o _cacti.so cacti.py $(TARGET) - - + -rm -f *.o _cacti.so cacti.py $(TARGET) \ No newline at end of file diff --git a/extio.cc b/extio.cc index 382a7a0..577f893 100644 --- a/extio.cc +++ b/extio.cc @@ -8,7 +8,7 @@ io_param(iot){} //External IO AREA. Does not include PHY or decap, includes only IO active circuit. More details can be found in the CACTI-IO technical report (), Chapter 2.3. -void Extio::extio_area() +double Extio::extio_area() { //Area per IO, assuming drive stage and ODT are shared @@ -35,12 +35,12 @@ void Extio::extio_area() printf("IO Area (sq.mm) = "); cout << io_area << endl; - + return io_area; } //External IO Termination Power. More details can be found in the CACTI-IO technical report (), Chapter 2.1. -void Extio::extio_power_term() +double Extio::extio_power_term() { //IO Termination and Bias Power @@ -128,12 +128,13 @@ void Extio::extio_power_term() printf("IO Termination and Bias Power (mW) = "); cout << io_power_term << endl; + return io_power_term; } //External PHY Power and Wakeup Times. More details can be found in the CACTI-IO technical report (), Chapter 2.1. -void Extio::extio_power_phy () +double Extio::extio_power_phy () { @@ -179,13 +180,13 @@ void Extio::extio_power_phy () cout << phy_power << " "; printf("PHY Wakeup Time (us) = "); cout << phy_wtime << endl; - + return phy_power; } //External IO Dynamic Power. Does not include termination or PHY. More details can be found in the CACTI-IO technical report (), Chapter 2.1. -void Extio::extio_power_dynamic() +double Extio::extio_power_dynamic() { if (io_param->io_type == Serial) @@ -345,12 +346,13 @@ void Extio::extio_power_dynamic() printf("IO Dynamic Power (mW) = "); cout << io_power_dynamic << " "; + return io_power_dynamic; } //External IO Timing and Voltage Margins. More details can be found in the CACTI-IO technical report (), Chapter 2.2. -void Extio::extio_eye() +double Extio::extio_eye() { if (io_param->io_type == Serial) @@ -502,5 +504,5 @@ void Extio::extio_eye() cout << io_tmargin < + +/* This file contains configuration parameters, including + * default configuration for DDR3, LPDDR2 and WIDEIO. The configuration + * parameters include technology parameters - voltage, load capacitances, IO + * area coefficients, timing parameters, as well as external io configuration parameters - + * termination values, voltage noise coefficients and voltage/timing noise + * sensitivity parameters. More details can be found in the CACTI-IO technical + * report (), especially Chapters 2 and 3. The user can define new dram types here. */ + + + +///////////// DDR3 /////////////////// + + const double rtt1_wr_lrdimm_ddr3[8][4] = +{ + {INF,INF,120,120}, + {INF,INF,120,120}, + {INF,120,120,80}, + {120,120,120,60}, + {120,120,120,60}, + {120,80,80,60}, + {120,80,80,60}, + {120,80,60,40} +}; + + const double rtt2_wr_lrdimm_ddr3[8][4] = +{ + {INF,INF,INF,INF},//1 + {INF,INF,120,120},//2 + {120,120,120,80}, //3 + {120,120,80,60}, //4 + {120,120,80,60}, + {120,80,60,40}, //6 + {120,80,60,40}, + {80,80,40,30}//8 +}; + + const double rtt1_rd_lrdimm_ddr3[8][4] = +{ + {INF,INF,120,120},//1 + {INF,INF,120,120},//2 + {INF,120,120,80}, //3 + {120,120,120,60}, //4 + {120,120,120,60}, + {120,80,80,60}, //6 + {120,80,80,60}, + {120,80,60,40}//8 +}; + + const double rtt2_rd_lrdimm_ddr3[8][4] = +{ + {INF,INF,INF,INF},//1 + {INF,120,80,60},//2 + {120,80,80,40}, //3 + {120,80,60,40}, //4 + {120,80,60,40}, + {80,60,60,30}, //6 + {80,60,60,30}, + {80,60,40,20}//8 +}; + + + const double rtt1_wr_host_dimm_ddr3[3][4]= +{ + {120,120,120,60}, + {120,80,80,60}, + {120,80,60,40} +}; + +const double rtt2_wr_host_dimm_ddr3[3][4]= +{ + {120,120,80,60}, + {120,80,60,40}, + {80,80,40,30} +}; + + const double rtt1_rd_host_dimm_ddr3[3][4]= +{ + {120,120,120,60}, + {120,80,80,60}, + {120,80,60,40} +}; + + const double rtt2_rd_host_dimm_ddr3[3][4]= +{ + {120,80,60,40}, + {80,60,60,30}, + {80,60,40,20} +}; + + + const double rtt1_wr_bob_dimm_ddr3[3][4]= +{ + {INF,120,120,80}, + {120,120,120,60}, + {120,80,80,60} +}; + + const double rtt2_wr_bob_dimm_ddr3[3][4]= +{ + {120,120,120,80}, + {120,120,80,60}, + {120,80,60,40} +}; + + const double rtt1_rd_bob_dimm_ddr3[3][4]= +{ + {INF,120,120,80}, + {120,120,120,60}, + {120,80,80,60} +}; + + const double rtt2_rd_bob_dimm_ddr3[3][4]= +{ + {120,80,80,40}, + {120,80,60,40}, + {80,60,60,30} +}; + + +///////////// DDR4 /////////////////// + + const double rtt1_wr_lrdimm_ddr4[8][4] = +{ + {120,120,80,80},//1 + {120,120,80,80},//2 + {120,80,80,60}, //3 + {80,60,60,60}, //4 + {80,60,60,60}, + {60,60,60,40}, //6 + {60,60,60,40}, + {40,40,40,40}//8 +}; + + const double rtt2_wr_lrdimm_ddr4[8][4] = +{ + {INF,INF,INF,INF},//1 + {120,120,120,80},//2 + {120,80,80,80},//3 + {80,80,80,60},//4 + {80,80,80,60}, + {60,60,60,40},//6 + {60,60,60,40}, + {60,40,40,30}//8 +}; + + const double rtt1_rd_lrdimm_ddr4[8][4] = +{ + {120,120,80,80},//1 + {120,120,80,60},//2 + {120,80,80,60}, //3 + {120,60,60,60}, //4 + {120,60,60,60}, + {80,60,60,40}, //6 + {80,60,60,40}, + {60,40,40,30}//8 +}; + + const double rtt2_rd_lrdimm_ddr4[8][4] = +{ + {INF,INF,INF,INF},//1 + {80,60,60,60},//2 + {60,60,40,40}, //3 + {60,40,40,40}, //4 + {60,40,40,40}, + {40,40,40,30}, //6 + {40,40,40,30}, + {40,30,30,20}//8 +}; + + + + const double rtt1_wr_host_dimm_ddr4[3][4]= +{ + {80,60,60,60}, + {60,60,60,60}, + {40,40,40,40} +}; + + const double rtt2_wr_host_dimm_ddr4[3][4]= +{ + {80,80,80,60}, + {60,60,60,40}, + {60,40,40,30} +}; + + const double rtt1_rd_host_dimm_ddr4[3][4]= +{ + {120,60,60,60}, + {80,60,60,40}, + {60,40,40,30} +}; + + const double rtt2_rd_host_dimm_ddr4[3][4]= +{ + {60,40,40,40}, + {40,40,40,30}, + {40,30,30,20} +}; + + + const double rtt1_wr_bob_dimm_ddr4[3][4]= +{ + {120,80,80,60}, + {80,60,60,60}, + {60,60,60,40} +}; + + const double rtt2_wr_bob_dimm_ddr4[3][4]= +{ + {120,80,80,80}, + {80,80,80,60}, + {60,60,60,40} +}; + + const double rtt1_rd_bob_dimm_ddr4[3][4]= +{ + {120,80,80,60}, + {120,60,60,60}, + {80,60,60,40} +}; + + const double rtt2_rd_bob_dimm_ddr4[3][4]= +{ + {60,60,40,40}, + {60,40,40,40}, + {40,40,40,30} +}; + + +///////////////////////////////////////////// + +int IOTechParam::frequnecy_index(Mem_IO_type type) +{ + if(type==DDR3) + { + if(frequency<=400) + return 0; + else if(frequency<=533) + return 1; + else if(frequency<=667) + return 2; + else + return 3; + } + else if(type==DDR4) + { + if(frequency<=800) + return 0; + else if(frequency<=933) + return 1; + else if(frequency<=1066) + return 2; + else + return 3; + } + else + { + assert(false); + } + return 0; +} + + + +IOTechParam::IOTechParam(InputParameter * g_ip) +{ + num_mem_ca = g_ip->num_mem_dq * (g_ip->num_dq/g_ip->mem_data_width); + num_mem_clk = g_ip->num_mem_dq * + (g_ip->num_dq/g_ip->mem_data_width)/(g_ip->num_clk/2); + + + if (g_ip->io_type == LPDDR2) { //LPDDR + //Technology Parameters + + vdd_io = 1.2; + v_sw_clk = 1; + + // Loading paramters + c_int = 1.5; + c_tx = 2; + c_data = 1.5; + c_addr = 0.75; + i_bias = 5; + i_leak = 1000; + + // IO Area coefficients + + ioarea_c = 0.01; + ioarea_k0 = 0.5; + ioarea_k1 = 0.00008; + ioarea_k2 = 0.000000030; + ioarea_k3 = 0.000000000008; + + // Timing parameters (ps) + t_ds = 250; + t_is = 250; + t_dh = 250; + t_ih = 250; + t_dcd_soc = 50; + t_dcd_dram = 50; + t_error_soc = 50; + t_skew_setup = 50; + t_skew_hold = 50; + t_dqsq = 250; + t_soc_setup = 50; + t_soc_hold = 50; + t_jitter_setup = 200; + t_jitter_hold = 200; + t_jitter_addr_setup = 200; + t_jitter_addr_hold = 200; + t_cor_margin = 40; + + //External IO Configuration Parameters + + r_diff_term = 480; + rtt1_dq_read = 100000; + rtt2_dq_read = 100000; + rtt1_dq_write = 100000; + rtt2_dq_write = 100000; + rtt_ca = 240; + rs1_dq = 0; + rs2_dq = 0; + r_stub_ca = 0; + r_on = 50; + r_on_ca = 50; + z0 = 50; + t_flight = 0.5; + t_flight_ca = 0.5; + + // Voltage noise coeffecients + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + +/* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/34 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/34 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/100 - 1) + + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/34 - 1) + + 0.3*(g_ip->num_mem_dq/2 - 1)); + t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/34 - 1) + + 0.3*(g_ip->num_mem_dq/2 - 1)); + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/100 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/100 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + + phy_datapath_s = 0; + phy_phase_rotator_s = 5; + phy_clock_tree_s = 0; + phy_rx_s = 3; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 2; + + + // PHY Dynamic Power Coefficients (mW/Gbps) + + phy_datapath_d = 0.3; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.4; + phy_rx_d = 0.2; + phy_dcc_d = 0; + phy_deskew_d = 0; + phy_leveling_d = 0; + phy_pll_d = 0.05; + + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0; + phy_vrefgen_wtime = 0; + + + } + else if (g_ip->io_type == WideIO) { //WIDEIO + //Technology Parameters + vdd_io = 1.2; + v_sw_clk = 1.2; + + // Loading parameters + c_int = 0.5; + c_tx = 0.5; + c_data = 0.5; + c_addr = 0.35; + i_bias = 0; + i_leak = 500; + + // IO Area coefficients + ioarea_c = 0.003; + ioarea_k0 = 0.2; + ioarea_k1 = 0.00004; + ioarea_k2 = 0.000000020; + ioarea_k3 = 0.000000000004; + + // Timing parameters (ps) + t_ds = 250; + t_is = 250; + t_dh = 250; + t_ih = 250; + t_dcd_soc = 50; + t_dcd_dram = 50; + t_error_soc = 50; + t_skew_setup = 50; + t_skew_hold = 50; + t_dqsq = 250; + t_soc_setup = 50; + t_soc_hold = 50; + t_jitter_setup = 200; + t_jitter_hold = 200; + t_jitter_addr_setup = 200; + t_jitter_addr_hold = 200; + t_cor_margin = 50; + + //External IO Configuration Parameters + + r_diff_term = 100000; + rtt1_dq_read = 100000; + rtt2_dq_read = 100000; + rtt1_dq_write = 100000; + rtt2_dq_write = 100000; + rtt_ca = 100000; + rs1_dq = 0; + rs2_dq = 0; + r_stub_ca = 0; + r_on = 75; + r_on_ca = 75; + z0 = 50; + t_flight = 0.05; + t_flight_ca = 0.05; + + // Voltage noise coeffecients + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + + /* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/50 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/50 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + k_noise_addr_sen = k_noise_addr * (1 + 0.2*(r_on/50 - 1) + + 0.2*(num_mem_ca/16 - 1)); + + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/50 - 1) + + 0.3*(g_ip->num_mem_dq/2 - 1)); + t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/50 - 1) + + 0.3*(g_ip->num_mem_dq/2 - 1)); + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.1*(r_on/50 - 1) + + 0.4*(num_mem_ca/16 - 1)); + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.1*(r_on/50 - 1) + + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 1; + phy_clock_tree_s = 0; + phy_rx_s = 0; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 0; + + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.3; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.2; + phy_rx_d = 0.1; + phy_dcc_d = 0; + phy_deskew_d = 0; + phy_leveling_d = 0; + phy_pll_d = 0; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 0; + phy_rx_wtime = 0; + phy_bandgap_wtime = 0; + phy_deskew_wtime = 0; + phy_vrefgen_wtime = 0; + + + } + else if (g_ip->io_type == DDR3) + { //Default parameters for DDR3 + // IO Supply voltage (V) + vdd_io = 1.5; + v_sw_clk = 0.75; + + // Loading parameters + c_int = 1.5; + c_tx = 2; + c_data = 1.5; + c_addr = 0.75; + i_bias = 15; + i_leak = 1000; + + // IO Area coefficients + ioarea_c = 0.01; + ioarea_k0 = 0.5; + ioarea_k1 = 0.00015; + ioarea_k2 = 0.000000045; + ioarea_k3 = 0.000000000015; + + // Timing parameters (ps) + t_ds = 150; + t_is = 150; + t_dh = 150; + t_ih = 150; + t_dcd_soc = 50; + t_dcd_dram = 50; + t_error_soc = 25; + t_skew_setup = 25; + t_skew_hold = 25; + t_dqsq = 100; + t_soc_setup = 50; + t_soc_hold = 50; + t_jitter_setup = 100; + t_jitter_hold = 100; + t_jitter_addr_setup = 100; + t_jitter_addr_hold = 100; + t_cor_margin = 30; + + + //External IO Configuration Parameters + + r_diff_term = 100; + rtt1_dq_read = g_ip->rtt_value; + rtt2_dq_read = g_ip->rtt_value; + rtt1_dq_write = g_ip->rtt_value; + rtt2_dq_write = g_ip->rtt_value; + rtt_ca = 50; + rs1_dq = 15; + rs2_dq = 15; + r_stub_ca = 0; + r_on = g_ip->ron_value; + r_on_ca = 50; + z0 = 50; + t_flight = g_ip->tflight_value; + t_flight_ca = 2; + + // Voltage noise coeffecients + + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + + /* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + + k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + + k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); + + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + + 0.3*(g_ip->num_mem_dq/2 - 1)); + + t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + + 0.1*(r_on/34 - 1) + 0.3*(g_ip->num_mem_dq/2 - 1)); + + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 10; + phy_clock_tree_s = 0; + phy_rx_s = 10; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 10; + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.5; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.5; + phy_rx_d = 0.5; + phy_dcc_d = 0.05; + phy_deskew_d = 0.1; + phy_leveling_d = 0.05; + phy_pll_d = 0.05; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0.003; + phy_vrefgen_wtime = 0.5; + + + } + else if (g_ip->io_type == DDR4) + { //Default parameters for DDR4 + // IO Supply voltage (V) + vdd_io = 1.2; + v_sw_clk = 0.6; + + // Loading parameters + c_int = 1.5; + c_tx = 2; + c_data = 1; + c_addr = 0.75; + i_bias = 15; + i_leak = 1000; + + // IO Area coefficients + ioarea_c = 0.01; + ioarea_k0 = 0.35; + ioarea_k1 = 0.00008; + ioarea_k2 = 0.000000035; + ioarea_k3 = 0.000000000010; + + // Timing parameters (ps) + t_ds = 30; + t_is = 60; + t_dh = 30; + t_ih = 60; + t_dcd_soc = 20; + t_dcd_dram = 20; + t_error_soc = 15; + t_skew_setup = 15; + t_skew_hold = 15; + t_dqsq = 50; + t_soc_setup = 20; + t_soc_hold = 10; + t_jitter_setup = 30; + t_jitter_hold = 30; + t_jitter_addr_setup = 60; + t_jitter_addr_hold = 60; + t_cor_margin = 10; + + + //External IO Configuration Parameters + + r_diff_term = 100; + rtt1_dq_read = g_ip->rtt_value; + rtt2_dq_read = g_ip->rtt_value; + rtt1_dq_write = g_ip->rtt_value; + rtt2_dq_write = g_ip->rtt_value; + rtt_ca = 50; + rs1_dq = 15; + rs2_dq = 15; + r_stub_ca = 0; + r_on = g_ip->ron_value; + r_on_ca = 50; + z0 = 50; + t_flight = g_ip->tflight_value; + t_flight_ca = 2; + + // Voltage noise coeffecients + + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + + /* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + + k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(g_ip->num_mem_dq/2 - 1)); + + k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); + + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + + 0.3*(g_ip->num_mem_dq/2 - 1)); + + t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + + 0.1*(r_on/34 - 1) + 0.3*(g_ip->num_mem_dq/2 - 1)); + + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 10; + phy_clock_tree_s = 0; + phy_rx_s = 10; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 10; + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.5; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.5; + phy_rx_d = 0.5; + phy_dcc_d = 0.05; + phy_deskew_d = 0.1; + phy_leveling_d = 0.05; + phy_pll_d = 0.05; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0.003; + phy_vrefgen_wtime = 0.5; + + + } + else if (g_ip->io_type == Serial) + { //Default parameters for Serial + // IO Supply voltage (V) + vdd_io = 1.2; + v_sw_clk = 0.75; + + // IO Area coefficients + ioarea_c = 0.01; + ioarea_k0 = 0.15; + ioarea_k1 = 0.00005; + ioarea_k2 = 0.000000025; + ioarea_k3 = 0.000000000005; + + // Timing parameters (ps) + t_ds = 15; + t_dh = 15; + t_dcd_soc = 10; + t_dcd_dram = 10; + t_soc_setup = 10; + t_soc_hold = 10; + t_jitter_setup = 20; + t_jitter_hold = 20; + + //External IO Configuration Parameters + + r_diff_term = 100; + + + t_jitter_setup_sen = t_jitter_setup; + + t_jitter_hold_sen = t_jitter_hold; + + t_jitter_addr_setup_sen = t_jitter_addr_setup; + + t_jitter_addr_hold_sen = t_jitter_addr_hold; + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 10; + phy_clock_tree_s = 0; + phy_rx_s = 10; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 10; + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.5; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.5; + phy_rx_d = 0.5; + phy_dcc_d = 0.05; + phy_deskew_d = 0.1; + phy_leveling_d = 0.05; + phy_pll_d = 0.05; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0.003; + phy_vrefgen_wtime = 0.5; + + + } + else + { + cout << "Not Yet supported" << endl; + exit(1); + } + + + //SWING AND TERMINATION CALCULATIONS + + //R|| calculation + rpar_write =(rtt1_dq_write + rs1_dq)*(rtt2_dq_write + rs2_dq)/ + (rtt1_dq_write + rs1_dq + rtt2_dq_write + rs2_dq); + rpar_read =(rtt1_dq_read)*(rtt2_dq_read + rs2_dq)/ + (rtt1_dq_read + rtt2_dq_read + rs2_dq); + + //Swing calculation + v_sw_data_read_load1 =vdd_io * (rtt1_dq_read)*(rtt2_dq_read + rs2_dq) / + ((rtt1_dq_read + rtt2_dq_read + rs2_dq)*(r_on + rs1_dq + rpar_read)); + v_sw_data_read_load2 =vdd_io * (rtt1_dq_read)*(rtt2_dq_read) / + ((rtt1_dq_read + rtt2_dq_read + rs2_dq)*(r_on + rs1_dq + rpar_read)); + v_sw_data_read_line =vdd_io * rpar_read / (r_on + rs1_dq + rpar_read); + v_sw_addr =vdd_io * rtt_ca / (50 + rtt_ca); + v_sw_data_write_load1 =vdd_io * (rtt1_dq_write)*(rtt2_dq_write + rs2_dq) / + ((rtt1_dq_write + rs1_dq + rtt2_dq_write + rs2_dq)*(r_on + rpar_write)); + v_sw_data_write_load2 =vdd_io * (rtt2_dq_write)*(rtt1_dq_write + rs1_dq) / + ((rtt1_dq_write + rs1_dq + rtt2_dq_write + rs2_dq)*(r_on + rpar_write)); + v_sw_data_write_line =vdd_io * rpar_write / (r_on + rpar_write); + +} + +// This constructor recieves most of the input from g_ip. +// however it is possible to customize other some of the paremeters, +// that are mentioned as inputs. +// connection: 0 bob-dimm, 1 host-dimm, 2 lrdimm + + +IOTechParam::IOTechParam(InputParameter * g_ip, Mem_IO_type io_type1, int num_mem_dq, int mem_data_width + , int num_dq, int connection, int num_loads, double freq) +{ + num_mem_ca = num_mem_dq * (mem_data_width); + num_mem_clk = num_mem_dq * + (num_dq/mem_data_width)/(g_ip->num_clk/2); + + io_type = io_type1; + frequency = freq; + + + + + if (io_type == LPDDR2) { //LPDDR + //Technology Parameters + + vdd_io = 1.2; + v_sw_clk = 1; + + // Loading paramters + c_int = 1.5; + c_tx = 2; + c_data = 1.5; + c_addr = 0.75; + i_bias = 5; + i_leak = 1000; + + // IO Area coefficients + + ioarea_c = 0.01; + ioarea_k0 = 0.5; + ioarea_k1 = 0.00008; + ioarea_k2 = 0.000000030; + ioarea_k3 = 0.000000000008; + + // Timing parameters (ps) + t_ds = 250; + t_is = 250; + t_dh = 250; + t_ih = 250; + t_dcd_soc = 50; + t_dcd_dram = 50; + t_error_soc = 50; + t_skew_setup = 50; + t_skew_hold = 50; + t_dqsq = 250; + t_soc_setup = 50; + t_soc_hold = 50; + t_jitter_setup = 200; + t_jitter_hold = 200; + t_jitter_addr_setup = 200; + t_jitter_addr_hold = 200; + t_cor_margin = 40; + + //External IO Configuration Parameters + + r_diff_term = 480; + rtt1_dq_read = 100000; + rtt2_dq_read = 100000; + rtt1_dq_write = 100000; + rtt2_dq_write = 100000; + rtt_ca = 240; + rs1_dq = 0; + rs2_dq = 0; + r_stub_ca = 0; + r_on = 50; + r_on_ca = 50; + z0 = 50; + t_flight = 0.5; + t_flight_ca = 0.5; + + // Voltage noise coeffecients + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + +/* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/34 - 1) + + 0.2*(num_mem_dq/2 - 1)); + k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/34 - 1) + + 0.2*(num_mem_dq/2 - 1)); + k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/100 - 1) + + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/34 - 1) + + 0.3*(num_mem_dq/2 - 1)); + t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/34 - 1) + + 0.3*(num_mem_dq/2 - 1)); + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/100 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/100 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + + phy_datapath_s = 0; + phy_phase_rotator_s = 5; + phy_clock_tree_s = 0; + phy_rx_s = 3; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 2; + + + // PHY Dynamic Power Coefficients (mW/Gbps) + + phy_datapath_d = 0.3; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.4; + phy_rx_d = 0.2; + phy_dcc_d = 0; + phy_deskew_d = 0; + phy_leveling_d = 0; + phy_pll_d = 0.05; + + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0; + phy_vrefgen_wtime = 0; + + + } + else if (io_type == WideIO) { //WIDEIO + //Technology Parameters + vdd_io = 1.2; + v_sw_clk = 1.2; + + // Loading parameters + c_int = 0.5; + c_tx = 0.5; + c_data = 0.5; + c_addr = 0.35; + i_bias = 0; + i_leak = 500; + + // IO Area coefficients + ioarea_c = 0.003; + ioarea_k0 = 0.2; + ioarea_k1 = 0.00004; + ioarea_k2 = 0.000000020; + ioarea_k3 = 0.000000000004; + + // Timing parameters (ps) + t_ds = 250; + t_is = 250; + t_dh = 250; + t_ih = 250; + t_dcd_soc = 50; + t_dcd_dram = 50; + t_error_soc = 50; + t_skew_setup = 50; + t_skew_hold = 50; + t_dqsq = 250; + t_soc_setup = 50; + t_soc_hold = 50; + t_jitter_setup = 200; + t_jitter_hold = 200; + t_jitter_addr_setup = 200; + t_jitter_addr_hold = 200; + t_cor_margin = 50; + + //External IO Configuration Parameters + + r_diff_term = 100000; + rtt1_dq_read = 100000; + rtt2_dq_read = 100000; + rtt1_dq_write = 100000; + rtt2_dq_write = 100000; + rtt_ca = 100000; + rs1_dq = 0; + rs2_dq = 0; + r_stub_ca = 0; + r_on = 75; + r_on_ca = 75; + z0 = 50; + t_flight = 0.05; + t_flight_ca = 0.05; + + // Voltage noise coeffecients + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + + /* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.2*(r_on/50 - 1) + + 0.2*(num_mem_dq/2 - 1)); + k_noise_read_sen = k_noise_read * (1 + 0.2*(r_on/50 - 1) + + 0.2*(num_mem_dq/2 - 1)); + k_noise_addr_sen = k_noise_addr * (1 + 0.2*(r_on/50 - 1) + + 0.2*(num_mem_ca/16 - 1)); + + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.1*(r_on/50 - 1) + + 0.3*(num_mem_dq/2 - 1)); + t_jitter_hold_sen = t_jitter_hold * (1 + 0.1*(r_on/50 - 1) + + 0.3*(num_mem_dq/2 - 1)); + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.1*(r_on/50 - 1) + + 0.4*(num_mem_ca/16 - 1)); + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.1*(r_on/50 - 1) + + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 1; + phy_clock_tree_s = 0; + phy_rx_s = 0; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 0; + + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.3; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.2; + phy_rx_d = 0.1; + phy_dcc_d = 0; + phy_deskew_d = 0; + phy_leveling_d = 0; + phy_pll_d = 0; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 0; + phy_rx_wtime = 0; + phy_bandgap_wtime = 0; + phy_deskew_wtime = 0; + phy_vrefgen_wtime = 0; + + + } + else if (io_type == DDR3) + { //Default parameters for DDR3 + // IO Supply voltage (V) + vdd_io = 1.5; + v_sw_clk = 0.75; + + // Loading parameters + c_int = 1.5; + c_tx = 2; + c_data = 1.5; + c_addr = 0.75; + i_bias = 15; + i_leak = 1000; + + // IO Area coefficients + ioarea_c = 0.01; + ioarea_k0 = 0.5; + ioarea_k1 = 0.00015; + ioarea_k2 = 0.000000045; + ioarea_k3 = 0.000000000015; + + // Timing parameters (ps) + t_ds = 150; + t_is = 150; + t_dh = 150; + t_ih = 150; + t_dcd_soc = 50; + t_dcd_dram = 50; + t_error_soc = 25; + t_skew_setup = 25; + t_skew_hold = 25; + t_dqsq = 100; + t_soc_setup = 50; + t_soc_hold = 50; + t_jitter_setup = 100; + t_jitter_hold = 100; + t_jitter_addr_setup = 100; + t_jitter_addr_hold = 100; + t_cor_margin = 30; + + + //External IO Configuration Parameters + + r_diff_term = 100; + + /* + rtt1_dq_read = g_ip->rtt_value; + rtt2_dq_read = g_ip->rtt_value; + rtt1_dq_write = g_ip->rtt_value; + rtt2_dq_write = g_ip->rtt_value; + */ + switch(connection) + { + case(0): + rtt1_dq_write = rtt1_wr_bob_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_write = rtt2_wr_bob_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt1_dq_read = rtt1_rd_bob_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_read = rtt2_rd_bob_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + break; + case(1): + rtt1_dq_write = rtt1_wr_host_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_write = rtt2_wr_host_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt1_dq_read = rtt1_rd_host_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_read = rtt2_rd_host_dimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + break; + case(2): + rtt1_dq_write = rtt1_wr_lrdimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_write = rtt2_wr_lrdimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt1_dq_read = rtt1_rd_lrdimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_read = rtt2_rd_lrdimm_ddr3[num_loads-1][frequnecy_index(io_type)]; + break; + default: + break; + } + + + rtt_ca = 50; + rs1_dq = 15; + rs2_dq = 15; + r_stub_ca = 0; + r_on = g_ip->ron_value; + r_on_ca = 50; + z0 = 50; + t_flight = g_ip->tflight_value; + t_flight_ca = 2; + + // Voltage noise coeffecients + + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + + /* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(num_mem_dq/2 - 1)); + + k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(num_mem_dq/2 - 1)); + + k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); + + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + + 0.3*(num_mem_dq/2 - 1)); + + t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + + 0.1*(r_on/34 - 1) + 0.3*(num_mem_dq/2 - 1)); + + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 10; + phy_clock_tree_s = 0; + phy_rx_s = 10; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 10; + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.5; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.5; + phy_rx_d = 0.5; + phy_dcc_d = 0.05; + phy_deskew_d = 0.1; + phy_leveling_d = 0.05; + phy_pll_d = 0.05; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0.003; + phy_vrefgen_wtime = 0.5; + + + } + else if (io_type == DDR4) + { //Default parameters for DDR4 + // IO Supply voltage (V) + vdd_io = 1.2; + v_sw_clk = 0.6; + + // Loading parameters + c_int = 1.5; + c_tx = 2; + c_data = 1; + c_addr = 0.75; + i_bias = 15; + i_leak = 1000; + + // IO Area coefficients + ioarea_c = 0.01; + ioarea_k0 = 0.35; + ioarea_k1 = 0.00008; + ioarea_k2 = 0.000000035; + ioarea_k3 = 0.000000000010; + + // Timing parameters (ps) + t_ds = 30; + t_is = 60; + t_dh = 30; + t_ih = 60; + t_dcd_soc = 20; + t_dcd_dram = 20; + t_error_soc = 15; + t_skew_setup = 15; + t_skew_hold = 15; + t_dqsq = 50; + t_soc_setup = 20; + t_soc_hold = 10; + t_jitter_setup = 30; + t_jitter_hold = 30; + t_jitter_addr_setup = 60; + t_jitter_addr_hold = 60; + t_cor_margin = 10; + + + //External IO Configuration Parameters + + r_diff_term = 100; + /* + rtt1_dq_read = g_ip->rtt_value; + rtt2_dq_read = g_ip->rtt_value; + rtt1_dq_write = g_ip->rtt_value; + rtt2_dq_write = g_ip->rtt_value; + */ + + switch(connection) + { + case(0): + rtt1_dq_write = rtt1_wr_bob_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_write = rtt2_wr_bob_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt1_dq_read = rtt1_rd_bob_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_read = rtt2_rd_bob_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + break; + case(1): + rtt1_dq_write = rtt1_wr_host_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_write = rtt2_wr_host_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt1_dq_read = rtt1_rd_host_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_read = rtt2_rd_host_dimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + break; + case(2): + rtt1_dq_write = rtt1_wr_lrdimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_write = rtt2_wr_lrdimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt1_dq_read = rtt1_rd_lrdimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + rtt2_dq_read = rtt2_rd_lrdimm_ddr4[num_loads-1][frequnecy_index(io_type)]; + break; + default: + break; + } + + rtt_ca = 50; + rs1_dq = 15; + rs2_dq = 15; + r_stub_ca = 0; + r_on = g_ip->ron_value; + r_on_ca = 50; + z0 = 50; + t_flight = g_ip->tflight_value; + t_flight_ca = 2; + + // Voltage noise coeffecients + + k_noise_write = 0.2; + k_noise_read = 0.2; + k_noise_addr = 0.2; + v_noise_independent_write = 0.1; + v_noise_independent_read = 0.1; + v_noise_independent_addr = 0.1; + + //SENSITIVITY INPUTS FOR TIMING AND VOLTAGE NOISE + + /* This is a user-defined section that depends on the channel sensitivity + * to IO and DRAM parameters. The t_jitter_* and k_noise_* are the + * parameters that are impacted based on the channel analysis. The user + * can define any relationship between the termination, loading and + * configuration parameters AND the t_jitter/k_noise parameters. E.g. a + * linear relationship, a non-linear analytical relationship or a lookup + * table. The sensitivity coefficients are based on channel analysis + * performed on the channel of interest.Given below is an example of such + * a sensitivity relationship. + * Such a linear fit can be found efficiently using an orthogonal design + * of experiments method shown in the technical report (), in Chapter 2.2. */ + + k_noise_write_sen = k_noise_write * (1 + 0.1*(rtt1_dq_write/60 - 1) + + 0.2*(rtt2_dq_write/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(num_mem_dq/2 - 1)); + + k_noise_read_sen = k_noise_read * (1 + 0.1*(rtt1_dq_read/60 - 1) + + 0.2*(rtt2_dq_read/60 - 1) + 0.2*(r_on/34 - 1) + + 0.2*(num_mem_dq/2 - 1)); + + k_noise_addr_sen = k_noise_addr * (1 + 0.1*(rtt_ca/50 - 1) + + 0.2*(r_on/34 - 1) + 0.2*(num_mem_ca/16 - 1)); + + + t_jitter_setup_sen = t_jitter_setup * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + 0.1*(r_on/34 - 1) + + 0.3*(num_mem_dq/2 - 1)); + + t_jitter_hold_sen = t_jitter_hold * (1 + 0.2*(rtt1_dq_write/60 - 1) + + 0.3*(rtt2_dq_write/60 - 1) + + 0.1*(r_on/34 - 1) + 0.3*(num_mem_dq/2 - 1)); + + t_jitter_addr_setup_sen = t_jitter_addr_setup * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + t_jitter_addr_hold_sen = t_jitter_addr_hold * (1 + 0.2*(rtt_ca/50 - 1) + + 0.1*(r_on/34 - 1) + 0.4*(num_mem_ca/16 - 1)); + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 10; + phy_clock_tree_s = 0; + phy_rx_s = 10; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 10; + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.5; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.5; + phy_rx_d = 0.5; + phy_dcc_d = 0.05; + phy_deskew_d = 0.1; + phy_leveling_d = 0.05; + phy_pll_d = 0.05; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0.003; + phy_vrefgen_wtime = 0.5; + + + } + else if (io_type == Serial) + { //Default parameters for Serial + // IO Supply voltage (V) + vdd_io = 1.2; + v_sw_clk = 0.75; + + // IO Area coefficients + ioarea_c = 0.01; + ioarea_k0 = 0.15; + ioarea_k1 = 0.00005; + ioarea_k2 = 0.000000025; + ioarea_k3 = 0.000000000005; + + // Timing parameters (ps) + t_ds = 15; + t_dh = 15; + t_dcd_soc = 10; + t_dcd_dram = 10; + t_soc_setup = 10; + t_soc_hold = 10; + t_jitter_setup = 20; + t_jitter_hold = 20; + + //External IO Configuration Parameters + + r_diff_term = 100; + + + t_jitter_setup_sen = t_jitter_setup; + + t_jitter_hold_sen = t_jitter_hold; + + t_jitter_addr_setup_sen = t_jitter_addr_setup; + + t_jitter_addr_hold_sen = t_jitter_addr_hold; + + // PHY Static Power Coefficients (mW) + phy_datapath_s = 0; + phy_phase_rotator_s = 10; + phy_clock_tree_s = 0; + phy_rx_s = 10; + phy_dcc_s = 0; + phy_deskew_s = 0; + phy_leveling_s = 0; + phy_pll_s = 10; + + // PHY Dynamic Power Coefficients (mW/Gbps) + phy_datapath_d = 0.5; + phy_phase_rotator_d = 0.01; + phy_clock_tree_d = 0.5; + phy_rx_d = 0.5; + phy_dcc_d = 0.05; + phy_deskew_d = 0.1; + phy_leveling_d = 0.05; + phy_pll_d = 0.05; + + //PHY Wakeup Times (Sleep to Active) (microseconds) + + phy_pll_wtime = 10; + phy_phase_rotator_wtime = 5; + phy_rx_wtime = 2; + phy_bandgap_wtime = 10; + phy_deskew_wtime = 0.003; + phy_vrefgen_wtime = 0.5; + + + } + else + { + cout << "Not Yet supported" << endl; + exit(1); + } + + + //SWING AND TERMINATION CALCULATIONS + + //R|| calculation + rpar_write =(rtt1_dq_write + rs1_dq)*(rtt2_dq_write + rs2_dq)/ + (rtt1_dq_write + rs1_dq + rtt2_dq_write + rs2_dq); + rpar_read =(rtt1_dq_read)*(rtt2_dq_read + rs2_dq)/ + (rtt1_dq_read + rtt2_dq_read + rs2_dq); + + + + //Swing calculation + v_sw_data_read_load1 =vdd_io * (rtt1_dq_read)*(rtt2_dq_read + rs2_dq) / + ((rtt1_dq_read + rtt2_dq_read + rs2_dq)*(r_on + rs1_dq + rpar_read)); + v_sw_data_read_load2 =vdd_io * (rtt1_dq_read)*(rtt2_dq_read) / + ((rtt1_dq_read + rtt2_dq_read + rs2_dq)*(r_on + rs1_dq + rpar_read)); + v_sw_data_read_line =vdd_io * rpar_read / (r_on + rs1_dq + rpar_read); + v_sw_addr =vdd_io * rtt_ca / (50 + rtt_ca); + v_sw_data_write_load1 =vdd_io * (rtt1_dq_write)*(rtt2_dq_write + rs2_dq) / + ((rtt1_dq_write + rs1_dq + rtt2_dq_write + rs2_dq)*(r_on + rpar_write)); + v_sw_data_write_load2 =vdd_io * (rtt2_dq_write)*(rtt1_dq_write + rs1_dq) / + ((rtt1_dq_write + rs1_dq + rtt2_dq_write + rs2_dq)*(r_on + rpar_write)); + v_sw_data_write_line =vdd_io * rpar_write / (r_on + rpar_write); + +} + + + +IOTechParam::~IOTechParam() +{} diff --git a/io.cc b/io.cc index 3a798aa..bcfeac4 100644 --- a/io.cc +++ b/io.cc @@ -2543,6 +2543,11 @@ void output_data_csv(const uca_org_t & fin_res, string fn) } else { + // MODIFIED to output CACTI IO metrics + IOTechParam iot(g_ip, g_ip->io_type, g_ip->num_mem_dq, g_ip->mem_data_width, g_ip->num_dq,g_ip->dram_dimm, 1,g_ip->bus_freq ); + Extio testextio(&iot); + // MODIFIED end + if (print_index == true) { file << "Tech node (nm), "; @@ -2587,6 +2592,14 @@ void output_data_csv(const uca_org_t & fin_res, string fn) file << "Ntsam_level_2, "; file << "Tag arrary area efficiency %, "; + // MODIFIED to output CACTI IO metrics + file << "IO area, "; + file << "IO timing, "; + file << "IO power dynamic, "; + file << "IO power PHY, "; + file << "IO power termination and bias, "; + // MODIFIED end + // file << "Resistance per unit micron (ohm-micron), "; // file << "Capacitance per unit micron (fF per micron), "; // file << "Unit-length wire delay (ps), "; @@ -2700,6 +2713,14 @@ void output_data_csv(const uca_org_t & fin_res, string fn) file << "N/A" << ", "; } + // MODIFIED to output CACTI IO metrics + file << testextio.extio_area() << ", "; + file << testextio.extio_eye() << ", "; + file << testextio.extio_power_dynamic() << ", "; + file << testextio.extio_power_phy() << ", "; + file << testextio.extio_power_term() << ", "; + // MODIFIED end + // file << g_tp.wire_inside_mat.R_per_um << ", "; // file << g_tp.wire_inside_mat.C_per_um / 1e-15 << ", "; // file << g_tp.unit_len_wire_del / 1e-12 << ", "; diff --git a/iocc_parsing.py b/iocc_parsing.py new file mode 100644 index 0000000..d2437f5 --- /dev/null +++ b/iocc_parsing.py @@ -0,0 +1,152 @@ +import pandas as pd +import os +import time + +def substring_after(s, delim): + return s.partition(delim)[2] + +def substring_before(s, delim): + return s.partition(delim)[0] + + +def clean(string): + tmp = string.replace(" ", "") + tmp = tmp.replace(";", "") + tmp = tmp.replace("\n", "") + return tmp + +def removeTab(string): + return string.replace("\t", "") + +def removeDecimal(string): + return string.replace(".", "") + +def check(line): + if "LPDDR2" in line: + return "LPDDR2" + if "WideIO" in line: + return "WideIO" + if "DDR3" in line: + return "DDR3" + if "DDR4" in line: + return "DDR4" + if "Serial" in line: + return "Serial" + else: + return None + + +file = open("extio_technology_control.txt") +lines = file.readlines() + +varList = [] +outputs = ["IO Area", "IO Dynamic Power", "IO Termination and Bias Power"] + + +function = '1' +functionType = "LPDDR2" + +result = pd.DataFrame(index= [1], columns= outputs) +for x in range(len(lines)): + var = None + val = None + + if check(lines[x]) != None: + functionType = check(lines[x]) + + + if " frequency = freq;" in lines[x]: + function = '2' + + directory = "iocc_results/" + functionType + "_" + function + if not os.path.isdir(directory): + os.makedirs(directory) + if not os.path.isdir("debug"): + os.makedirs("debug") + + + if "=" in lines[x]: #and function =="2" and functionType == "DDR3" + text = lines[x].split(" = ") + if len(text) > 1: + var = clean(text[0]) + val = clean(text[1]) + # print (removeDecimal(val).isnumeric()) + if removeDecimal(val).isnumeric(): + # print(val) + controlLine = "\t" + var + " = " + str(val) + ";" + "\n" + varSpec = var + "_" + function + "_" + functionType + + varList.append(removeTab(varSpec)) + if val == "0": + val = 1 + elif "." in val: + val = float(val)*1000 + else: + val = int(val)*1000 + + # print (val) + print (var + " = " + str(val)) + lines[x] = "\t" + var + " = " + str(val) + ";" +"\n" + + with open("extio_technology.cc", 'w') as file: + file.writelines(lines) + + with open("debug/"+varSpec+ "code" + ".txt", 'w') as file: + file.writelines(lines) + + os.system("make > /dev/null 2>&1") + time.sleep(0.3) #if executed too fast, this program will not work properly. Adding a delay will ensure the program will actually be made + os.system("./cacti -infile cache.cfg > output.txt") + os.system("./cacti -infile cache.cfg > debug/" + varSpec + ".txt") + time.sleep(0.3) + varSpec = removeTab(varSpec) + os.system("diff control.txt output.txt > " + directory + "/" + varSpec + ".txt") + time.sleep(0.3) + + diff = open(directory + "/" + varSpec + ".txt") + diff = diff.readlines() + + curResult = pd.DataFrame(index = [varSpec], columns=outputs) + + for word in outputs: + counter = 0; + value = None + value2 = None + + for line in diff: + if line.find(word) != -1 and counter == 1: + # print("found2") + if word == "IO Dynamic Power": + value2 = substring_before(line, "PHY") + value2 = substring_after(value2, " = ") + else: + value2 = substring_after(line, " = ") + + if value == value2: + curResult.at[varSpec, word] = "" + else: + curResult.at[varSpec, word] = value + ", " + value2 + break + elif line.find(word) != -1: + # print("found1") + counter = 1 + if word == "IO Dynamic Power": + value = substring_before(line, "PHY") + value = substring_after(value, " = ") + else: + value = substring_after(line, " = ") + else: + if pd.isnull(curResult.at[varSpec, word]): + curResult.at[varSpec, word] = " " + + if word == "IO Termination and Bias Power": + result = pd.concat([result, curResult]) + + + lines[x] = controlLine + print(result) + with open("extio_technology.cc", 'w') as file: + file.writelines(lines) +result.to_csv("check.csv", index=True, header=True) + + diff --git a/tech_param_parse.py b/tech_param_parse.py new file mode 100644 index 0000000..4ae6c8a --- /dev/null +++ b/tech_param_parse.py @@ -0,0 +1,227 @@ + +import pandas as pd +import os +import shutil +import subprocess + + +names = ["architecture", "current", "semiconductor", "SRAM_data", "CAM_data", "DRAM_data", "DRAM_cell", "chip_data_dict", "wire", "TSV_data"] + +def float_to_exponential(num): + return format(num, "e") + +def substring_after(s, delim): + return s.partition(delim)[2] + +# read the unit header but don't add the column label to it +def parse(file, first, last): + chunk = file.iloc[first:last] + chunk= chunk['parameters'].str.split(expand = True) + chunk = chunk.reset_index(drop=True) + chunk.loc[len(chunk)] = None + return chunk + +def partition(tech_param): + tech_param = pd.read_csv(tech_param, names = ['parameters']) + + architecture = parse(tech_param, 1, 13) + architecture.columns =['parameters', '(unit)', 'hp','lstp','lop','lp-dram','comm-dram'] + + current = parse(tech_param, 14, 36) + current.columns =['parameters', '(unit)', 'temp', 'hp','lstp','lop','lp-dram','comm-dram'] + + semiconductor = parse(tech_param, 37, 44) + semiconductor.columns =['parameters', '(unit)', 'hp', 'lstp', 'lop', 'lp-dram', 'comm-dram'] + + SRAM_data = parse(tech_param, 46, 51) + SRAM_data.columns =['parameters', '(unit)', 'cell_type', 'hp', 'lstp', 'lop','lp-dram','comm-dram'] + + CAM_data = parse(tech_param, 53, 58) + CAM_data.columns =['parameters', '(unit)', 'cell_type', 'hp', 'lstp', 'lop','lp-dram','comm-dram'] + + DRAM_data = parse(tech_param, 60, 66) + DRAM_data.columns =['parameters', '(unit)','cell_type', 'hp', 'lstp', 'lop','lp-dram','comm-dram'] + + DRAM_cell= parse(tech_param, 67, 71) + DRAM_cell.columns =['parameters', '(unit)', 'hp', 'lstp', 'lop', 'lp-dram', 'comm-dram' ] + + chip_data = parse(tech_param, 71, 78) + chip_data.columns =["parameters", "(unit)", "value"] + # chip_data_dict = {chip_data[0][0]: chip_data[1][0]} + # for x in range(8): + # chip_data_dict.update ({chip_data[0][x]: chip_data[1][x]}) + + wire = parse(tech_param, 79, 90) + wire.columns =['parameters','(units)', '0/0', '0/1', '0/2', '0/3', '1/0', '1/1', '1/2', '1/3' ] + + TSV_data = parse(tech_param, 91, None) + TSV_data.columns =['parameters','(units)', '0/0', '0/1', '0/2', '0/3', '1/0', '1/1', '1/2', '1/3'] + + return architecture, current, semiconductor, SRAM_data, CAM_data, DRAM_data, DRAM_cell, chip_data, wire, TSV_data + +def convert(dict, file): + for key in dict: + dict[key].to_csv(file, mode='a', index=False, header=True, sep=' ') + +def merge(file): + dict = {names[0]:data[0]} + initialize = {"none" : []} + initialize = pd.DataFrame(data=initialize) + initialize.to_csv(file, index=False, header=False, sep=' ') + for x in range(10): + dict.update({names[x]:data[x]}) + return dict + + +tech_size = "90nm" +data = partition("tech_params_control/"+ tech_size + ".dat") +tech_param_dict = merge('tech_params/' + tech_size + ".dat") +convert(tech_param_dict, 'tech_params/' + tech_size + ".dat") +os.system("./cacti -infile cache.cfg > control.txt") + + + +outputs = ["Access time", "Cycle time", "Total dynamic read energy per access", "Total dynamic write energy per access", + "Total leakage power of a bank", "Total gate leakage power of a bank", "Cache height x width", "IO Area", + "IO Dynamic Power", "IO Termination and Bias Power"] + +inputs = [] +for name in tech_param_dict: + temp = 0 + chunk = tech_param_dict[name] + for y in range(len(chunk)): + if not(pd.isnull(chunk.iloc[y,0])): + if chunk.iloc[y,0] == "-I_off_n" or chunk.iloc[y,0] == "-I_g_on_n": + for column in chunk.columns[3:]: + inputs.append(name + chunk.iloc[y,0] + "-" + column + "-" + chunk.iloc[y,2]) + else: + for column in chunk.columns[2:]: + inputs.append(name + chunk.iloc[y,0] + "-" + column.replace( '/', '')) +# print (inputs) + +table_outputs = pd.DataFrame(columns = outputs, index = inputs) +table_outputs.to_csv("final.csv", index=True, header=True) + +#parse through each chunk and do it bruh +for chunkName in tech_param_dict: + for y in range (len(tech_param_dict[chunkName])): + folder = chunkName + str(tech_param_dict[chunkName].iloc[y,0]) + directory = "results/" + folder + "/" + + if not os.path.isdir(directory): + os.makedirs(directory) + + if pd.isnull(input): + continue + + for x in range (len(tech_param_dict[chunkName].columns)): + + print (folder) + + + if folder == "current-I_off_n" or folder == "current-I_g_on_n": + input = folder + "-" + str(tech_param_dict[chunkName].columns[x]) + "-" + str(tech_param_dict[chunkName].iloc[y,2]) + else: + input = folder + "-" + str(tech_param_dict[chunkName].columns[x]).replace( '/', '') + + print (input) + + cell = tech_param_dict[chunkName].iloc[y,x] + if not(pd.isnull(cell)) and cell[0].isdigit() and input.find("-temp") == -1: + print(tech_param_dict[chunkName].iat[y,x]) + if tech_param_dict[chunkName].iat[y,x] == '0': + tech_param_dict[chunkName].iat[y,x] = '1' + else: + tech_param_dict[chunkName].iat[y,x] = float_to_exponential(float(tech_param_dict[chunkName].iat[y,x])*100) + print(tech_param_dict[chunkName].iat[y,x]) + + + # print (tech_param_dict[chunkName]) + convert(tech_param_dict, 'tech_params/' + tech_size + ".dat") #converts dictionary into .dat file + + print (subprocess.check_output("./cacti -infile cache.cfg > output.txt", shell=True, text=True)) + os.system("./cacti -infile cache.cfg > output.txt") + # if str(subprocess.check_output("./cacti -infile cache.cfg > output.txt", shell=True, text=True)).find("Assertion failed:") != -1: + # print("hello") + # data = partition("tech_params_control/90nm.dat") #resets data tuple + # tech_param_dict = merge('tech_params/90nm.dat') #puts each dataframe in the dictionary, labeled + # convert(tech_param_dict, 'tech_params/90nm.dat') #converts dictionary into .dat file + # continue + os.system("diff control.txt output.txt > " + directory + input + ".txt") + + diff = open(directory + input + ".txt") + lines = diff.readlines() + + for word in outputs: + counter = 0; + value = None + value2 = None + for line in lines: + if line.find(word) != -1 and counter == 1: + # print("found2") + value2 = substring_after(line, ":") + value2 = value2.replace('\n', '') + table_outputs.at[input,word] = value + ", " + value2 + "\n" + break + elif line.find(word) != -1: + # print("found1") + counter = 1 + value = substring_after(line, ":") + value = value.replace('\n', '') + elif line.find("ERROR: no valid tag organizations found") != -1: + # print("found1") + table_outputs.loc[input] = "ERROR: no valid tag organizations found" + break + else: + # print (table_outputs.at[input, word]) + if pd.isnull(table_outputs.at[input, word]): + table_outputs.at[input, word] = " " + # print (table_outputs.at[input, word]) + + data = partition('tech_params_control/' + tech_size + ".dat") #resets data tuple + tech_param_dict = merge('tech_params/' + tech_size + ".dat") #puts each dataframe in the dictionary, labeled + convert(tech_param_dict, 'tech_params/' + tech_size + ".dat") #converts dictionary into .dat file + +table_outputs.to_csv("cache.csv", index=True, header=True) + +''' +readL: outputs dataframesss + +process: change the values, write to data, call cacti +output to a different file and process that one instead + +write: input dataframes + +get the table going .csv + + +IO Area (sq.mm) = inf +IO Dynamic Power (mW) = 1506.36 PHY Power (mW) = 232.752 PHY Wakeup Time (us) = 27.503 +IO Termination and Bias Power (mW) = 2505.96 + + +''' + + +# process = subprocess.Popen(bash_command.split(), stdout=subprocess.PIPE, stderr=subprocess.PIPE) +# output, error = process.communicate() + +# # Decode output and error from bytes to string +# output_str = output.decode('utf-8') +# error_str = error.decode('utf-8') + +# # Print output and error +# print("Output:", output_str) + + +# for y in range (5): +# for x in range (7): +# if not(pd.isnull(data.iloc[y+1,x+2])) : +# data = partition("idk/cacti/tech_params/90nm.dat", tech_result) +# data.iloc[y+1,x+2] = float_to_exponential(float(data.iloc[y+1,x+2])*10) +# # print(data) + + + + +# print (partition("idk/cacti/tech_params/90nm.dat", tech_result)) diff --git a/tech_params_control/.DS_Store b/tech_params_control/.DS_Store new file mode 100644 index 0000000..4ae624d Binary files /dev/null and b/tech_params_control/.DS_Store differ diff --git a/tech_params_control/16nm.dat b/tech_params_control/16nm.dat new file mode 100644 index 0000000..2574ca7 --- /dev/null +++ b/tech_params_control/16nm.dat @@ -0,0 +1 @@ +Invalid technology nodes diff --git a/tech_params_control/180nm-old.dat b/tech_params_control/180nm-old.dat new file mode 100644 index 0000000..4028f3e --- /dev/null +++ b/tech_params_control/180nm-old.dat @@ -0,0 +1,294 @@ +#each column represents one technology flavors. +#options are itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram + +========================================================================== +parameters || hp | lstp | lop | lp-dram | comm-dram || + || | | | | || +========================================================================== + || | | | | || +-C_g_ideal || 13.28e-16 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_fringe || 0.16e-15 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_junc || 2e-15 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_junc_sw || 0.25e-15 | 0.25e-15 | 0.25e-15 | 0.25e-15 | 0.25e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-l_phy || 0.12 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-l_elec || 0.1 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________||__________________________ + || | | | | || +-nmos_effective_resistance_multiplier || 1.54 | 1.54 | 1.54 | 1.54 | 1.54 || +______________________________________||____________|___________|___________|___________|___________|| + || | | | | || +-Vdd || 1.5 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Vth || 0.4407 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Vdsat || 0.256 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-I_on_n || 750e-6 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-I_on_p || 350e-6 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || + I_off depends on Temperature [temp3-300]/10 is used as index || +_________________________________________________________________________|| + | || | | | | || +-I_off_n|0 || 7e-10 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|10 || 8.26e-10 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|20 || 9.74e-10 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|30 || 1.15e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|40 || 1.35e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|50 || 1.60e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|60 || 1.88e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|70 || 2.29e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|80 || 2.70e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|90 || 3.19e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|100 || 3.76e-9 | 0 | 0 | 0 | 0 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|0 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|10 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|20 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|30 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|40 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|50 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|60 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|70 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|80 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|90 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|100 || 1.65e-10 | 0 | 0 | 0 | 0 || +_________|___ ||__________|___________|___________|___________|___________|| + || | | | | || +-C_ox || 3.58e-14 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-t_ox || 2.4e-3 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-n2p_drv_rt || 2.45 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-lch_lk_rdc || 1 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Mobility_n || 302.16e8 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________||__________ + || | | | | || +-gmp_to_gmn_multiplier || 1.22 | 0 | 0 | 0 | 0 || +_______________________||___________|___________|___________|___________|___________|| + || | | | | || +-vpp || 0 | 0 | 0 | 0 | 0 || +____________||___________|___________|___________|___________|___________|| + + +SRAM +__________________________________________________________________________________ + | || | | | | || +-Wmemcella | 0 || 1.31 | 1.31 | 1.31 | 1.31 | 1.31 || +___________|________||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 0 || 1.23 | 1.23 | 1.23 | 1.23 | 1.23 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 0 || 2.08 | 2.08 | 2.08 | 2.08 | 2.08 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 0 || 146 | 146 | 146 | 146 | 146 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 0 || 1.46 | 1.46 | 1.46 | 1.46 | 1.46 || +________________|___||___________|___________|___________|___________|___________|| + +CAM +__________________________________________________________________________________ + | || | | | | || +-Wmemcella | 1 || 1.31 | 1.31 | 1.31 | 1.31 | 1.31 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 1 || 1.23 | 1.23 | 1.23 | 1.23 | 1.23 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 1 || 2.08 | 2.08 | 2.08 | 2.08 | 2.08 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 1 || 292 | 292 | 292 | 292 | 292 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 1 || 2.92 | 2.92 | 2.92 | 2.92 | 2.92 || +________________|___||___________|___________|___________|___________|___________|| + +DRAM +__________________________________________________________________________________ + | || | | | | || +-vdd_cell | 2 || 0 | | | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcella | 2 || 0 | | | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 2 || 0 | | | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 2 || 0 | | | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 2 || 0 | | | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 2 || 2 | | | 0 | 0 || +________________|___||___________|___________|___________|___________|___________|| + +______________________________________________________________________________ + || | | | | || +-dram_cell_I_on || 0 | | | 0 | 0 || +________________||___________|___________|___________|___________|___________|| + || | | | | || +-dram_cell_Vdd || 0 | | | 0 | 0 || +________________||___________|___________|___________|___________|___________|| + || | | | | || +-dram_cell_C || 0 | | | 0 | 0 || +________________||___________|___________|___________|___________|___________||____________________ + || | | | | || +-dram_cell_I_off_worst_case_len_temp || 0 | | | 0 | 0 || +_____________________________________||___________|___________|___________|___________|___________|| + + +__________________________________________________________________________ + || +-logic_scaling_co_eff 1.5 || +_________________________________________________________________________|| + || +-core_tx_density 0.245 || +_________________________________________________________________________|| + || +-sckt_co_eff 1.11 || +_________________________________________________________________________|| + || +-chip_layout_overhead 1.0 || +_________________________________________________________________________|| + || +-macro_layout_overhead 1.0 || +_________________________________________________________________________|| +__________________________________________________________________________ + || +-sense_delay .28e-9 || +_________________________________________________________________________|| + || +-sense_dy_power 14.7e-15 || +_________________________________________________________________________|| + + +_____________________________________________________________________________________________________________________________________________________ + || | | | | | | | | | || +-wire_pitch || 2.5 | 4 | 8 | 0 | 0 | 2.5 | 4 | 8 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-barrier_thickness || 0.017 | 0.017 | 0.017 | 0.017 | 0.017 | 0.017 | 0.017 | 0.017 | 0.017 | 0.017 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-dishing_thickness || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-alpha_scatter || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-aspect_ratio || 2.0 | 2.4 | 2.2 | 0 | 0 | 2.0 | 2.0 | 2.2 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-miller_value || 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-horiz_dielectric_constant || 2.709 | 2.709 | 2.709 | 2.709 | 2.709 | 2.709 | 2.709 | 2.709 | 2.709 | 2.709 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-vert_dielectric_constant || 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-ild_thickness || 0.75 | 0.75 | 1.5 | 0 | 0 | 0.75 | 0.75 | 1.5 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-fringe_cap || 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + +_____________________________________________________________________________________________________ + || | | | | | || +-tsv_pitch || 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_diameter || 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_length || 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_dielec_thickness || 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_contact_resistance || 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_depletion_width || 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_liner_dielectric_cons || 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + + + + + + + + diff --git a/tech_params_control/180nm.dat b/tech_params_control/180nm.dat new file mode 100644 index 0000000..5725ba3 --- /dev/null +++ b/tech_params_control/180nm.dat @@ -0,0 +1,113 @@ +parameters (unit) hp lstp lop lp-dram comm-dram +-C_g_ideal (F/um) 1.328e-15 0 0 0 0 +-C_fringe (F/um) 1.6e-16 0 0 0 0 +-C_junc (F/um^2) 2e-15 0 0 0 0 +-C_junc_sw (F/um^2) 2.5e-16 2.5e-16 2.5e-16 2.5e-16 2.5e-16 +-l_phy (um) 0.12 0 0 0 0 +-l_elec (um) 0.1 0 0 0 0 +-nmos_effective_resistance_multiplier (-) 1.54 0 0 0 0 +-Vdd (V) 1.5 0 0 0 0 +-Vth (V) 0.4407 0 0 0 0 +-Vdsat (V) 0.256 0 0 0 0 +-I_on_n (A/um) 0.00075 0 0 0 0 +-I_on_p (A/um) 0.00035 0 0 0 0 + + + +parameters (unit) temp hp lstp lop lp-dram comm-dram +-I_off_n (A/um) 0 7e-10 0 0 0 0 +-I_off_n (A/um) 10 8.26e-10 0 0 0 0 +-I_off_n (A/um) 20 9.74e-10 0 0 0 0 +-I_off_n (A/um) 30 1.15e-09 0 0 0 0 +-I_off_n (A/um) 40 1.35e-09 0 0 0 0 +-I_off_n (A/um) 50 1.6e-09 0 0 0 0 +-I_off_n (A/um) 60 1.88e-09 0 0 0 0 +-I_off_n (A/um) 70 2.29e-09 0 0 0 0 +-I_off_n (A/um) 80 2.7e-09 0 0 0 0 +-I_off_n (A/um) 90 3.19e-09 0 0 0 0 +-I_off_n (A/um) 100 3.76e-09 0 0 0 0 +-I_g_on_n (A/um) 0 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 10 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 20 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 30 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 40 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 50 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 60 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 70 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 80 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 90 1.65e-10 0 0 0 0 +-I_g_on_n (A/um) 100 1.65e-10 0 0 0 0 + + +parameters (unit) hp lstp lop lp-dram comm-dram +-C_ox (F/um^2) 3.58e-14 0 0 0 0 +-t_ox (um) 0.0024 0 0 0 0 +-n2p_drv_rt (-) 2.45 0 0 0 0 +-lch_lk_rdc (-) 1 0 0 0 0 +-Mobility_n (um^2/V.sec) 3.0216e+10 0 0 0 0 +-gmp_to_gmn_multiplier (-) 1.22 0 0 0 0 +-vpp (V) 0 0 0 0 0 + +SRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 0 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 0 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 0 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 0 146 146 146 146 146 +-asp_ratio_cell (-) 0 1.46 1.46 1.46 1.46 1.46 + +CAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 1 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 1 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 1 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 1 292 292 292 292 292 +-asp_ratio_cell (-) 1 2.92 2.92 2.92 2.92 2.92 + +DRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-vdd_cell (V) 2 0 0 0 0 0 +-Wmemcella (um) 2 0 0 0 0 0 +-Wmemcellpmos (um) 2 0 0 0 0 0 +-Wmemcellnmos (um) 2 0 0 0 0 0 +-area_cell (um^2) 2 0 0 0 0 0 +-asp_ratio_cell (-) 2 0 0 0 0 0 + +parameters hp lstp lop lp-dram comm-dram +-dram_cell_I_on (A/um) 0 0 0 0 0 +-dram_cell_Vdd (V) 0 0 0 0 0 +-dram_cell_C (F) 0 0 0 0 0 +-dram_cell_I_off_worst_case_len_temp (A/um) 0 0 0 0 0 + + +-logic_scaling_co_eff (-) 1.5 +-core_tx_density (1/um^2) 0.245 +-sckt_co_eff (-) 1.11 +-chip_layout_overhead (-) 1 +-macro_layout_overhead (-) 1 +-sense_delay (sec) 2.8e-10 +-sense_dy_power (J) 1.47e-14 + +parameters 0/0 0/1 0/2 0/3 1/0 1/1 1/2 1/3 +-wire_pitch (um) 2.5 4 8 0 2.5 4 8 2 +-barrier_thickness (um) 0.017 0.017 0.017 0 0.017 0.017 0.017 0 +-dishing_thickness (um) 0 0 0 0 0 0 0.1584 0 +-alpha_scatter (-) 1 1 1 0 1 1 1 0 +-aspect_ratio (-) 2 2.4 2.2 0 2 2 2.2 0 +-miller_value (-) 1.5 1.5 1.5 0 1.5 1.5 1.5 0 +-horiz_dielectric_constant (-) 2.709 2.709 2.709 0 3.038 3.038 3.038 0 +-vert_dielectric_constant (-) 3.9 3.9 3.9 0 3.9 3.9 3.9 0 +-ild_thickness (um) 0.75 0.75 1.5 0 0.75 0.75 1.98 0 +-fringe_cap (F/um) 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 +-resistivity (u-ohm.m) 0.022 0.022 0.022 0.022 0.022 0.022 0.022 0.022 + +parameters 0/0 0/1 0/2 1/0 1/1 1/2 +-wire_r_per_micron (ohm/um) 0 0 0 0 0 0 0 66.6667 +-wire_c_per_micron (F/um) 0 0 0 0 0 0 0 6.51042e-16 +-tsv_pitch (um) 0 0 0 0 0 0 +-tsv_diameter (um) 0 0 0 0 0 0 +-tsv_length (um) 0 0 0 0 0 0 +-tsv_dielec_thickness (um) 0 0 0 0 0 0 +-tsv_contact_resistance (ohm) 0 0 0 0 0 0 +-tsv_depletion_width (um) 0 0 0 0 0 0 +-tsv_liner_dielectric_cons (-) 0 0 0 0 0 0 diff --git a/tech_params_control/22nm.dat b/tech_params_control/22nm.dat new file mode 100644 index 0000000..8cabf32 --- /dev/null +++ b/tech_params_control/22nm.dat @@ -0,0 +1,113 @@ +parameters (unit) hp lstp lop lp-dram comm-dram +-C_g_ideal (F/um) 3.27e-16 3.22e-16 3.16e-16 0 1.99e-16 +-C_fringe (F/um) 6e-17 8e-17 8e-17 0 5.3e-17 +-C_junc (F/um^2) 0 0 0 0 1e-15 +-C_junc_sw (F/um^2) 2.5e-16 2.5e-16 2.5e-16 2.5e-16 2.5e-16 +-l_phy (um) 0.009 0.014 0.011 0 0.022 +-l_elec (um) 0.00468 0.008 0.00604 0 0.0181 +-nmos_effective_resistance_multiplier (-) 1.45 1.99 1.73 0 1.69 +-Vdd (V) 0.8 0.8 0.6 0 0.9 +-Vth (V) 0.1395 0.40126 0.2315 0 1 +-Vdsat (V) 0.0233 0.0664 0.0181 0 0.0972 +-I_on_n (A/um) 0.0026264 0.0007276 0.0009161 0 0.0009105 +-I_on_p (A/um) 0.0013132 0.0003638 0.00045805 0 0.00045525 + + + +parameters (unit) temp hp lstp lop lp-dram comm-dram +-I_off_n (A/um) 0 1.216e-07 2.43e-11 1.31e-08 0 1.1e-13 +-I_off_n (A/um) 10 1.24e-07 4.85e-11 2.6e-08 0 2.11e-13 +-I_off_n (A/um) 20 1.272e-07 9.68e-11 5.14e-08 0 3.88e-13 +-I_off_n (A/um) 30 1.344e-07 1.94e-10 1.02e-07 0 6.9e-13 +-I_off_n (A/um) 40 1.52e-07 3.87e-10 2.02e-07 0 1.19e-12 +-I_off_n (A/um) 50 2.152e-07 7.73e-10 3.99e-07 0 1.98e-12 +-I_off_n (A/um) 60 4.256e-07 3.55e-10 7.91e-07 0 3.22e-12 +-I_off_n (A/um) 70 8.16e-07 3.09e-09 1.09e-06 0 5.09e-12 +-I_off_n (A/um) 80 1.296e-06 6.19e-09 2.09e-06 0 7.85e-12 +-I_off_n (A/um) 90 2.184e-06 1.24e-08 4.04e-06 0 1.18e-11 +-I_off_n (A/um) 100 4.88e-06 2.48e-08 4.48e-06 0 1.72e-11 +-I_g_on_n (A/um) 0 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 10 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 20 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 30 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 40 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 50 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 60 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 70 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 80 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 90 1.81e-09 4.51e-10 2.74e-09 0 0 +-I_g_on_n (A/um) 100 1.81e-09 4.51e-10 2.74e-09 0 0 + + +parameters (unit) hp lstp lop lp-dram comm-dram +-C_ox (F/um^2) 3.63e-14 2.3e-14 2.87e-14 0 9.06e-15 +-t_ox (um) 0.00055 0.0011 0.0008 0 0.0035 +-n2p_drv_rt (-) 2 2 2 0 1.95 +-lch_lk_rdc (-) 0.305437 0.529101 0.420168 0 1 +-Mobility_n (um^2/V.sec) 4.2607e+10 7.3809e+10 6.9837e+10 0 3.6729e+10 +-gmp_to_gmn_multiplier (-) 1.38 0.99 1.11 0 0.9 +-vpp (V) 0 0 0 0 2.3 + +SRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 0 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 0 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 0 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 0 146 146 146 146 146 +-asp_ratio_cell (-) 0 1.46 1.46 1.46 1.46 1.46 + +CAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 1 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 1 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 1 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 1 292 292 292 292 292 +-asp_ratio_cell (-) 1 2.92 2.92 2.92 2.92 2.92 + +DRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-vdd_cell (V) 2 0 0 0 0 0 +-Wmemcella (um) 2 0 0 0 0 0.022 +-Wmemcellpmos (um) 2 0 0 0 0 0 +-Wmemcellnmos (um) 2 0 0 0 0 0 +-area_cell (um^2) 2 0 0 0 0 0.001936 +-asp_ratio_cell (-) 2 0 0 0 0 1 + +parameters hp lstp lop lp-dram comm-dram +-dram_cell_I_on (A/um) 0 0 0 0 2e-05 +-dram_cell_Vdd (V) 0 0 0 0 0.9 +-dram_cell_C (F) 0 0 0 0 3e-14 +-dram_cell_I_off_worst_case_len_temp (A/um) 0 0 0 0 1e-15 + + +-logic_scaling_co_eff (-) 0.2401 +-core_tx_density (1/um^2) 2.55102 +-sckt_co_eff (-) 1.1296 +-chip_layout_overhead (-) 1.2 +-macro_layout_overhead (-) 1.1 +-sense_delay (sec) 3e-11 +-sense_dy_power (J) 2.16e-15 + +parameters 0/0 0/1 0/2 0/3 1/0 1/1 1/2 1/3 +-wire_pitch (um) 2.5 4 8 0 2.5 4 8 2 +-barrier_thickness (um) 0 0 0 0 0.003 0.003 0.003 0 +-dishing_thickness (um) 0 0 0 0 0 0 0.01936 0 +-alpha_scatter (-) 1 1 1 0 1.05 1.05 1.05 0 +-aspect_ratio (-) 3 3 3 0 2 2 2.2 0 +-miller_value (-) 1.5 1.5 1.5 0 1.5 1.5 1.5 0 +-horiz_dielectric_constant (-) 1.414 1.414 1.414 0 2.104 2.104 2.104 0 +-vert_dielectric_constant (-) 3.9 3.9 3.9 0 3.9 3.9 3.9 0 +-ild_thickness (um) 0.15 0.15 0.3 0 0.15 0.15 0.275 0 +-fringe_cap (F/um) 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 +-resistivity (u-ohm.m) 0.018 0.018 0.018 0.018 0.022 0.022 0.022 0.022 + +parameters 0/0 0/1 0/2 1/0 1/1 1/2 +-wire_r_per_micron (ohm/um) 0 0 0 0 0 0 0 545.455 +-wire_c_per_micron (F/um) 0 0 0 0 0 0 0 2.75213e-15 +-tsv_pitch (um) 0.8 40 0 1.5 9 0 +-tsv_diameter (um) 0.4 7.5 0 0.8 4.5 0 +-tsv_length (um) 4 50 0 10 25 0 +-tsv_dielec_thickness (um) 0.1 0.2 0 0.1 0.1 0 +-tsv_contact_resistance (ohm) 0.1 0.2 0 0.1 0.1 0 +-tsv_depletion_width (um) 0.6 0.6 0 0.6 0.6 0 +-tsv_liner_dielectric_cons (-) 1.414 1.414 0 2.104 2.104 0 diff --git a/tech_params_control/32nm.dat b/tech_params_control/32nm.dat new file mode 100644 index 0000000..1e396d9 --- /dev/null +++ b/tech_params_control/32nm.dat @@ -0,0 +1,113 @@ +parameters (unit) hp lstp lop lp-dram comm-dram +-C_g_ideal (F/um) 5.34e-16 4.58e-16 4.54e-16 7.45e-16 2.56e-16 +-C_fringe (F/um) 4e-17 5.3e-17 5.7e-17 5.3e-17 5.3e-17 +-C_junc (F/um^2) 1e-15 1e-15 1e-15 1e-15 1e-15 +-C_junc_sw (F/um^2) 2.5e-16 2.5e-16 2.5e-16 2.5e-16 2.5e-16 +-l_phy (um) 0.013 0.02 0.016 0.056 0.032 +-l_elec (um) 0.01013 0.0173 0.01232 0.0419 0.0205 +-nmos_effective_resistance_multiplier (-) 1.49 1.99 1.73 1.65 1.69 +-Vdd (V) 0.9 1 0.6 1 1 +-Vth (V) 0.21835 0.513 0.24227 0.44467 1 +-Vdsat (V) 0.0509 0.0864 0.0464 0.174 0.129 +-I_on_n (A/um) 0.0022117 0.0006836 0.0008278 0.0010554 0.0010245 +-I_on_p (A/um) 0.00110585 0.0003418 0.0004139 0.0005277 0.00051225 + + + +parameters (unit) temp hp lstp lop lp-dram comm-dram +-I_off_n (A/um) 0 1.52e-07 2.06e-11 5.94e-08 3.57e-11 3.63e-14 +-I_off_n (A/um) 10 1.55e-07 3.3e-11 7.23e-08 5.51e-11 7.18e-14 +-I_off_n (A/um) 20 1.59e-07 5.15e-11 8.7e-08 8.27e-11 1.36e-13 +-I_off_n (A/um) 30 1.68e-07 7.83e-11 1.04e-07 1.21e-10 2.49e-13 +-I_off_n (A/um) 40 1.9e-07 1.16e-10 1.22e-07 1.74e-10 4.41e-13 +-I_off_n (A/um) 50 2.69e-07 1.69e-10 1.43e-07 2.45e-10 7.55e-13 +-I_off_n (A/um) 60 5.32e-07 2.4e-10 1.65e-07 3.38e-10 1.26e-12 +-I_off_n (A/um) 70 1.02e-06 3.34e-10 1.9e-07 4.53e-10 2.03e-12 +-I_off_n (A/um) 80 1.62e-06 4.54e-10 2.15e-07 5.87e-10 3.19e-12 +-I_off_n (A/um) 90 2.73e-06 5.96e-10 2.39e-07 7.29e-10 4.87e-12 +-I_off_n (A/um) 100 6.1e-06 7.44e-10 2.63e-07 8.87e-10 7.16e-12 +-I_g_on_n (A/um) 0 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 10 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 20 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 30 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 40 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 50 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 60 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 70 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 80 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 90 6.55e-08 3.73e-11 2.93e-09 0 0 +-I_g_on_n (A/um) 100 6.55e-08 3.73e-11 2.93e-09 0 0 + + +parameters (unit) hp lstp lop lp-dram comm-dram +-C_ox (F/um^2) 4.11e-14 2.29e-14 2.84e-14 1.48e-14 7.99e-15 +-t_ox (um) 0.0005 0.0012 0.0009 0.002 0.004 +-n2p_drv_rt (-) 2.41 2.23 2.28 2.05 1.95 +-lch_lk_rdc (-) 0.269833 0.518135 0.529101 1 1 +-Mobility_n (um^2/V.sec) 3.6184e+10 3.4746e+10 5.1352e+10 4.0812e+10 3.8076e+10 +-gmp_to_gmn_multiplier (-) 1.38 0.99 1.11 0.9 0.9 +-vpp (V) 0 0 0 1.5 2.6 + +SRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 0 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 0 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 0 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 0 146 146 146 146 146 +-asp_ratio_cell (-) 0 1.46 1.46 1.46 1.46 1.46 + +CAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 1 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 1 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 1 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 1 292 292 292 292 292 +-asp_ratio_cell (-) 1 2.92 2.92 2.92 2.92 2.92 + +DRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-vdd_cell (V) 2 0 0 0 1 1 +-Wmemcella (um) 2 0 0 0 0.056 0.032 +-Wmemcellpmos (um) 2 0 0 0 0 0 +-Wmemcellnmos (um) 2 0 0 0 0 0 +-area_cell (um^2) 2 0 0 0 0.03136 0.006144 +-asp_ratio_cell (-) 2 0 0 0 1.46 1.5 + +parameters hp lstp lop lp-dram comm-dram +-dram_cell_I_on (A/um) 0 0 0 3.6e-05 2e-05 +-dram_cell_Vdd (V) 0 0 0 1 1 +-dram_cell_C (F) 0 0 0 2e-14 3e-14 +-dram_cell_I_off_worst_case_len_temp (A/um) 0 0 0 1.89e-11 1e-15 + + +-logic_scaling_co_eff (-) 0.343 +-core_tx_density (1/um^2) 1.78571 +-sckt_co_eff (-) 1.1111 +-chip_layout_overhead (-) 1.2 +-macro_layout_overhead (-) 1.1 +-sense_delay (sec) 3e-11 +-sense_dy_power (J) 2.16e-15 + +parameters 0/0 0/1 0/2 0/3 1/0 1/1 1/2 1/3 +-wire_pitch (um) 2.5 4 8 0 2.5 4 8 2 +-barrier_thickness (um) 0 0 0 0 0.003 0.003 0.003 0 +-dishing_thickness (um) 0 0 0 0 0 0 0.02816 0 +-alpha_scatter (-) 1 1 1 0 1 1 1 0 +-aspect_ratio (-) 3 3 3 0 2 2 2.2 0 +-miller_value (-) 1.5 1.5 1.5 0 1.5 1.5 1.5 0 +-horiz_dielectric_constant (-) 1.664 1.664 1.664 0 2.214 2.214 2.214 0 +-vert_dielectric_constant (-) 3.9 3.9 3.9 0 3.9 3.9 3.9 0 +-ild_thickness (um) 0.21 0.21 0.42 0 0.21 0.21 0.385 0 +-fringe_cap (F/um) 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 +-resistivity (u-ohm.m) 0.018 0.018 0.018 0.018 0.022 0.022 0.022 0.022 + +parameters 0/0 0/1 0/2 1/0 1/1 1/2 +-wire_r_per_micron (ohm/um) 0 0 0 0 0 0 0 375 +-wire_c_per_micron (F/um) 0 0 0 0 0 0 0 1.89209e-15 +-tsv_pitch (um) 1.4 15 0 4 30 0 +-tsv_diameter (um) 0.7 2.3 0 2 3.8 0 +-tsv_length (um) 5 30 0 15 37.5 0 +-tsv_dielec_thickness (um) 0.1 0.2 0 0.1 0.5 0 +-tsv_contact_resistance (ohm) 0.1 0.2 0 0.1 0.2 0 +-tsv_depletion_width (um) 0.6 0.6 0 0.6 0.6 0 +-tsv_liner_dielectric_cons (-) 1.664 1.664 0 2.214 2.214 0 diff --git a/tech_params_control/45nm.dat b/tech_params_control/45nm.dat new file mode 100644 index 0000000..027bdfe --- /dev/null +++ b/tech_params_control/45nm.dat @@ -0,0 +1,113 @@ +parameters (unit) hp lstp lop lp-dram comm-dram +-C_g_ideal (F/um) 6.78e-16 5.18e-16 6.2e-16 1.1e-15 3.59e-16 +-C_fringe (F/um) 5e-17 8e-17 7.3e-17 8e-17 8e-17 +-C_junc (F/um^2) 1e-15 1e-15 1e-15 1e-15 1e-15 +-C_junc_sw (F/um^2) 2.5e-16 2.5e-16 2.5e-16 2.5e-16 2.5e-16 +-l_phy (um) 0.018 0.028 0.022 0.078 0.045 +-l_elec (um) 0.01345 0.0212 0.016 0.0504 0.0298 +-nmos_effective_resistance_multiplier (-) 1.51 1.99 1.76 1.65 1.69 +-Vdd (V) 1 1.1 0.7 1.1 1.1 +-Vth (V) 0.18035 0.50245 0.22599 0.44559 1 +-Vdsat (V) 0.0938 0.0912 0.0571 0.181 0.147 +-I_on_n (A/um) 0.0020466 0.0006662 0.0007489 0.000456 0.0009994 +-I_on_p (A/um) 0.0010233 0.0003331 0.00037445 0.000228 0.0004997 + + + +parameters (unit) temp hp lstp lop lp-dram comm-dram +-I_off_n (A/um) 0 2.8e-07 1.01e-11 4.03e-09 2.54e-11 1.31e-14 +-I_off_n (A/um) 10 3.28e-07 1.65e-11 5.02e-09 3.94e-11 2.68e-14 +-I_off_n (A/um) 20 3.81e-07 2.62e-11 6.18e-09 5.95e-11 5.25e-14 +-I_off_n (A/um) 30 4.39e-07 4.06e-11 7.51e-09 8.79e-11 9.88e-14 +-I_off_n (A/um) 40 5.02e-07 6.12e-11 9.04e-09 1.27e-10 1.79e-13 +-I_off_n (A/um) 50 5.69e-07 9.02e-11 1.08e-08 1.79e-10 3.15e-13 +-I_off_n (A/um) 60 6.42e-07 1.3e-10 1.27e-08 2.47e-10 5.36e-13 +-I_off_n (A/um) 70 7.2e-07 1.83e-10 1.47e-08 3.31e-10 8.86e-13 +-I_off_n (A/um) 80 8.03e-07 2.51e-10 1.66e-08 4.26e-10 1.42e-12 +-I_off_n (A/um) 90 8.91e-07 3.29e-10 1.84e-08 5.27e-10 2.2e-12 +-I_off_n (A/um) 100 9.84e-07 4.1e-10 2.03e-08 6.46e-10 3.29e-12 +-I_g_on_n (A/um) 0 3.59e-08 9.47e-12 3.24e-08 0 0 +-I_g_on_n (A/um) 10 3.59e-08 9.47e-12 4.01e-08 0 0 +-I_g_on_n (A/um) 20 3.59e-08 9.47e-12 4.9e-08 0 0 +-I_g_on_n (A/um) 30 3.59e-08 9.47e-12 5.92e-08 0 0 +-I_g_on_n (A/um) 40 3.59e-08 9.47e-12 7.08e-08 0 0 +-I_g_on_n (A/um) 50 3.59e-08 9.47e-12 8.38e-08 0 0 +-I_g_on_n (A/um) 60 3.59e-08 9.47e-12 9.82e-08 0 0 +-I_g_on_n (A/um) 70 3.59e-08 9.47e-12 1.14e-07 0 0 +-I_g_on_n (A/um) 80 3.59e-08 9.47e-12 1.29e-07 0 0 +-I_g_on_n (A/um) 90 3.59e-08 9.47e-12 1.43e-07 0 0 +-I_g_on_n (A/um) 100 3.59e-08 9.47e-12 1.54e-07 0 0 + + +parameters (unit) hp lstp lop lp-dram comm-dram +-C_ox (F/um^2) 3.77e-14 2.01e-14 2.82e-14 1.41e-14 7.98e-15 +-t_ox (um) 0.00065 0.0014 0.0009 0.0021 0.004 +-n2p_drv_rt (-) 2.41 2.23 2.28 2.05 1.95 +-lch_lk_rdc (-) 0.282008 0.480769 0.520833 1 1 +-Mobility_n (um^2/V.sec) 2.6668e+10 3.6396e+10 5.089e+10 4.263e+10 3.6858e+10 +-gmp_to_gmn_multiplier (-) 1.38 0.99 1.11 0.9 0.9 +-vpp (V) 0 0 0 1.5 2.7 + +SRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 0 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 0 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 0 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 0 146 146 146 146 146 +-asp_ratio_cell (-) 0 1.46 1.46 1.46 1.46 1.46 + +CAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 1 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 1 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 1 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 1 292 292 292 292 292 +-asp_ratio_cell (-) 1 2.92 2.92 2.92 2.92 2.92 + +DRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-vdd_cell (V) 2 0 0 0 1.1 1.1 +-Wmemcella (um) 2 0 0 0 0.079 0.045 +-Wmemcellpmos (um) 2 0 0 0 0 0 +-Wmemcellnmos (um) 2 0 0 0 0 0 +-area_cell (um^2) 2 0 0 0 0.06162 0.01215 +-asp_ratio_cell (-) 2 0 0 0 1.46 1.5 + +parameters hp lstp lop lp-dram comm-dram +-dram_cell_I_on (A/um) 0 0 0 3.6e-05 2e-05 +-dram_cell_Vdd (V) 0 0 0 1.1 1.1 +-dram_cell_C (F) 0 0 0 2e-14 3e-14 +-dram_cell_I_off_worst_case_len_temp (A/um) 0 0 0 1.95e-11 1e-15 + + +-logic_scaling_co_eff (-) 0.49 +-core_tx_density (1/um^2) 1.25 +-sckt_co_eff (-) 1.1387 +-chip_layout_overhead (-) 1.2 +-macro_layout_overhead (-) 1.1 +-sense_delay (sec) 4e-11 +-sense_dy_power (J) 2.7e-15 + +parameters 0/0 0/1 0/2 0/3 1/0 1/1 1/2 1/3 +-wire_pitch (um) 2.5 4 8 0 2.5 4 8 2 +-barrier_thickness (um) 0 0 0 0 0.004 0.004 0.004 0 +-dishing_thickness (um) 0 0 0 0 0 0 0.0396 0 +-alpha_scatter (-) 1 1 1 0 1 1 1 0 +-aspect_ratio (-) 3 3 3 0 2 2 2.2 0 +-miller_value (-) 1.5 1.5 1.5 0 1.5 1.5 1.5 0 +-horiz_dielectric_constant (-) 1.958 1.958 1.958 0 2.46 2.46 2.46 0 +-vert_dielectric_constant (-) 3.9 3.9 3.9 0 3.9 3.9 3.9 0 +-ild_thickness (um) 0.315 0.315 0.63 0 0.315 0.315 0.55 0 +-fringe_cap (F/um) 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 +-resistivity (u-ohm.m) 0.018 0.018 0.018 0.018 0.022 0.022 0.022 0.022 + +parameters 0/0 0/1 0/2 1/0 1/1 1/2 +-wire_r_per_micron (ohm/um) 0 0 0 0 0 0 0 266.667 +-wire_c_per_micron (F/um) 0 0 0 0 0 0 0 1.6276e-15 +-tsv_pitch (um) 2.2 20 0 3.4 40 0 +-tsv_diameter (um) 1.1 3.1 0 1.7 5 0 +-tsv_length (um) 6 40 0 20 50 0 +-tsv_dielec_thickness (um) 0.1 0.2 0 0.1 0.5 0 +-tsv_contact_resistance (ohm) 0.1 0.2 0 0.1 0.2 0 +-tsv_depletion_width (um) 0.6 0.6 0 0.6 0.6 0 +-tsv_liner_dielectric_cons (-) 1.958 1.958 0 2.46 2.46 0 diff --git a/tech_params_control/65nm-old.dat b/tech_params_control/65nm-old.dat new file mode 100644 index 0000000..90327a2 --- /dev/null +++ b/tech_params_control/65nm-old.dat @@ -0,0 +1,301 @@ +#each column represents one technology flavors. +#options are itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram + +========================================================================== +parameters || hp | lstp | lop | lp-dram | comm-dram || + || | | | | || +========================================================================== + || | | | | || +-C_g_ideal || 4.69e-16 | 6.14e-16 | 6e-16 | 1.46e-15 | 4e-16 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_fringe || 0.077e-15 | 0.08e-15 | 0.08e-15 | 0.08e-15 | 0.08e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_junc || 1e-15 | 1e-15 | 1e-15 | 1e-15 | 1e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_junc_sw || 0.25e-15 | 0.25e-15 | 0.25e-15 | 0.25e-15 | 0.25e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-l_phy || 0.025 | 0.045 | 0.032 | 0.12 | 0.065 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-l_elec || 0.019 | 0.0298 | 0.0216 | 0.0756 | 0.0426 || +____________||___________|___________|___________|___________|___________||__________________________ + || | | | | || +-nmos_effective_resistance_multiplier || 1.50 | 1.96 | 1.82 | 1.65 | 1.69 || +______________________________________||____________|___________|___________|___________|___________|| + || | | | | || +-Vdd || 1.1 | 1.2 | 0.8 | 1.2 | 1.6 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Vth || 0.19491 | 0.52354 | 0.28512 | 0.43806 | 1 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Vdsat || 7.71e-2 | 0.128 | 0.292 | 0.43806 | 0.385 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-I_on_n || 1197.2e-6 | 519.2e-6 | 573.1e-6 | 399.8e-6 | 1031e-6 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-I_on_p || 870.8e-6 | 266e-6 | 340.6e-6 | 399.8e-6 | 515.5e-6 || +____________||___________|___________|___________|___________|___________|| + || + I_off depends on Temperature [temp3-300]/10 is used as index || +_________________________________________________________________________|| + | || | | | | || +-I_off_n|0 || 1.96e-7 | 9.12e-12 | 4.9e-9 | 2.23e-11 | 1.80e-14 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|10 || 2.29e-7 | 1.49e-11 | 6.49e-9 | 3.46e-11 | 3.64e-14 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|20 || 2.66e-7 | 2.36e-11 | 8.45e-9 | 5.24e-11 | 7.03e-14 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|30 || 3.05e-7 | 3.64e-11 | 1.08e-8 | 7.75e-11 | 1.31e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|40 || 3.49e-7 | 5.48e-11 | 1.37e-8 | 1.12e-10 | 2.35e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|50 || 3.95e-7 | 8.05e-11 | 1.71e-8 | 1.58e-10 | 4.09e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|60 || 4.45e-7 | 1.15e-10 | 2.09e-8 | 2.18e-10 | 6.89e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|70 || 4.97e-7 | 1.59e-10 | 2.48e-8 | 2.88e-10 | 1.13e-12 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|80 || 5.48e-7 | 2.1e-10 | 2.84e-8 | 3.63e-10 | 1.78e-12 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|90 || 5.94e-7 | 2.62e-10 | 3.13e-8 | 4.41e-10 | 2.71e-12 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|100 || 6.3e-7 | 3.21e-10 | 3.42e-8 | 5.36e-10 | 3.99e-12 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|0 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|10 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|20 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|30 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|40 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|50 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|60 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|70 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|80 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|90 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|100 || 4.09e-8 | 1.09e-10 | 9.61e-9 | 0 | 0 || +_________|___ ||_________|___________|___________|___________|___________|| + || | | | | || +-C_ox || 1.88e-14 | 1.36e-14 | 1.87e-14 | 1.22e-14 | 6.16e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-t_ox || 1.1e-3 | 1.9e-3 | 1.2e-3 | 2.2e-3 | 5e-3 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-n2p_drv_rt || 2.41 | 2.23 | 2.28 | 2.05 | 2.39 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-lch_lk_rdc || 0.26738 | 0.35461 | 0.4878 | 1 | 1 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Mobility_n || 436.24e8 | 341.21e8 | 495.19e8 | 328.32e8 | 303.44e8 || +____________||___________|___________|___________|___________|___________||__________ + || | | | | || +-gmp_to_gmn_multiplier || 1.38 | 0.99 | 1.11 | 0.90 | 0.90 || +_______________________||___________|___________|___________|___________|___________|| + || | | | | || +-vpp || 0 | 0 | 0 | 1.6 | 3.3 || +____________||___________|___________|___________|___________|___________|| + +SRAM +__________________________________________________________________________________ + | || | | | | || +-Wmemcella | 0 || 1.31 | 1.31 | 1.31 | 1.31 | 1.31 || +___________|________||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 0 || 1.23 | 1.23 | 1.23 | 1.23 | 1.23 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 0 || 2.08 | 2.08 | 2.08 | 2.08 | 2.08 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 0 || 146 | 146 | 146 | 146 | 146 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 0 || 1.46 | 1.46 | 1.46 | 1.46 | 1.46 || +________________|___||___________|___________|___________|___________|___________|| + +CAM +__________________________________________________________________________________ + | || | | | | || +-Wmemcella | 1 || 1.31 | 1.31 | 1.31 | 1.31 | 1.31 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 1 || 1.23 | 1.23 | 1.23 | 1.23 | 1.23 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 1 || 2.08 | 2.08 | 2.08 | 2.08 | 2.08 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 1 || 292 | 292 | 292 | 292 | 292 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 1 || 2.92 | 2.92 | 2.92 | 2.92 | 2.92 || +________________|___||___________|___________|___________|___________|___________|| + +DRAM +__________________________________________________________________________________ + | || | | | | || +-vdd_cell | 2 || 0 | 0 | 0 | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcella | 2 || 0 | 0 | 0 | 0.09 | 0.065 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 2 || 0 | 0 | 0 | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 2 || 0 | 0 | 0 | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 2 || 0 | 0 | 0 | 0.11 | 0.02535 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 2 || 2 | 0 | 0 | 1.46 | 1.5 || +________________|___||___________|___________|___________|___________|___________|| + +______________________________________________________________________________ + || | | | | || +-dram_cell_I_on || 0 | 0 | 0 | 36e-6 | 20e-6 || +________________||___________|___________|___________|___________|___________|| + || | | | | || +-dram_cell_Vdd || 0 | 0 | 0 | 1.2 | 1.6 || +________________||___________|___________|___________|___________|___________|| + || | | | | || +-dram_cell_C || 0 | 0 | 0 | 20e-15 | 30e-15 || +________________||___________|___________|___________|___________|___________||____________________ + || | | | | || +-dram_cell_I_off_worst_case_len_temp || 0 | 0 | 0 | 19.6e-12 | 1e-15 || +_____________________________________||___________|___________|___________|___________|___________|| + + +__________________________________________________________________________ + || +-logic_scaling_co_eff 0.7 || +_________________________________________________________________________|| + || +-core_tx_density 0.875 || +_________________________________________________________________________|| + || +-sckt_co_eff 1.1359 || +_________________________________________________________________________|| + || +-chip_layout_overhead 1.2 || +_________________________________________________________________________|| + || +-macro_layout_overhead 1.1 || +_________________________________________________________________________|| +__________________________________________________________________________ + || +-sense_delay .2e-9 || +_________________________________________________________________________|| + || +-sense_dy_power 5.7e-15 || +_________________________________________________________________________|| + + + +_____________________________________________________________________________________________________________________________________________________ + || | | | | | | | | | || +-wire_pitch || 2.5 | 4 | 8 | 0 | 0 | 2.5 | 4 | 8 | 0.13 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-barrier_thickness || 0 | 0 | 0 | 0 | 0 | 0.006 | 0.006 | 0.006 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-dishing_thickness || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-alpha_scatter || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-aspect_ratio || 2.7 | 2.7 | 2.8 | 0 | 0 | 2.0 | 2.0 | 2.2 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-miller_value || 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-horiz_dielectric_constant || 2.303 | 2.303 | 2.303 | 0 | 0 | 2.734 | 2.734 | 2.734 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-vert_dielectric_constant || 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-ild_thickness || 0.405 | 0.405 | 0.81 | 0 | 0 | 0.405 | 0.405 | 1.1 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-fringe_cap || 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-wire_r_per_micron || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1.577e-15 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|__________ |___________|| + || | | | | | | | | | || +-wire_c_per_micron || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 184.6154 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + +_____________________________________________________________________________________________________ + || | | | | | || +-tsv_pitch || 3.2 | 30 | 0 | 5 | 60 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_diameter || 1.6 | 4.6 | 0 | 2.5 | 7.5 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_length || 7 | 50 | 0 | 25 | 62.5 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_dielec_thickness || 0.1 | 0.2 | 0 | 0.1 | 0.5 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_contact_resistance || 0.1 | 0.2 | 0 | 0.1 | 0.2 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_depletion_width || 0.6 | 0.6 | 0 | 0.6 | 0.6 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_liner_dielectric_cons || 2.303 | 2.303 | 0 | 2.734 | 2.734 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + + + + + + + + + diff --git a/tech_params_control/65nm.dat b/tech_params_control/65nm.dat new file mode 100644 index 0000000..06deb60 --- /dev/null +++ b/tech_params_control/65nm.dat @@ -0,0 +1,113 @@ +parameters (unit) hp lstp lop lp-dram comm-dram +-C_g_ideal (F/um) 4.69e-16 6.14e-16 6e-16 1.46e-15 4e-16 +-C_fringe (F/um) 7.7e-17 8e-17 8e-17 8e-17 8e-17 +-C_junc (F/um^2) 1e-15 1e-15 1e-15 1e-15 1e-15 +-C_junc_sw (F/um^2) 2.5e-16 2.5e-16 2.5e-16 2.5e-16 2.5e-16 +-l_phy (um) 0.025 0.045 0.032 0.12 0.065 +-l_elec (um) 0.019 0.0298 0.0216 0.0756 0.0426 +-nmos_effective_resistance_multiplier (-) 1.5 1.96 1.82 1.65 1.69 +-Vdd (V) 1.1 1.2 0.8 1.2 1.3 +-Vth (V) 0.19491 0.52354 0.28512 0.43806 1 +-Vdsat (V) 0.0771 0.128 0.292 0.43806 0.385 +-I_on_n (A/um) 0.0011972 0.0005192 0.0005731 0.0003998 0.001031 +-I_on_p (A/um) 0.0008708 0.000266 0.0003406 0.0002434 0.0005155 + + + +parameters (unit) temp hp lstp lop lp-dram comm-dram +-I_off_n (A/um) 0 1.96e-07 9.12e-12 4.9e-09 2.23e-11 1.8e-14 +-I_off_n (A/um) 10 2.29e-07 1.49e-11 6.49e-09 3.46e-11 3.64e-14 +-I_off_n (A/um) 20 2.66e-07 2.36e-11 8.45e-09 5.24e-11 7.03e-14 +-I_off_n (A/um) 30 3.05e-07 3.64e-11 1.08e-08 7.75e-11 1.31e-13 +-I_off_n (A/um) 40 3.49e-07 5.48e-11 1.37e-08 1.12e-10 2.35e-13 +-I_off_n (A/um) 50 3.95e-07 8.05e-11 1.71e-08 1.58e-10 4.09e-13 +-I_off_n (A/um) 60 4.45e-07 1.15e-10 2.09e-08 2.18e-10 6.89e-13 +-I_off_n (A/um) 70 4.97e-07 1.59e-10 2.48e-08 2.88e-10 1.13e-12 +-I_off_n (A/um) 80 5.48e-07 2.1e-10 2.84e-08 3.63e-10 1.78e-12 +-I_off_n (A/um) 90 5.94e-07 2.62e-10 3.13e-08 4.41e-10 2.71e-12 +-I_off_n (A/um) 100 6.3e-07 3.21e-10 3.42e-08 5.36e-10 3.99e-12 +-I_g_on_n (A/um) 0 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 10 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 20 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 30 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 40 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 50 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 60 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 70 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 80 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 90 4.09e-08 1.09e-10 9.61e-09 0 0 +-I_g_on_n (A/um) 100 4.09e-08 1.09e-10 9.61e-09 0 0 + + +parameters (unit) hp lstp lop lp-dram comm-dram +-C_ox (F/um^2) 1.88e-14 1.36e-14 1.87e-14 1.22e-14 6.16e-15 +-t_ox (um) 0.0011 0.0019 0.0012 0.0022 0.005 +-n2p_drv_rt (-) 2.41 2.23 2.28 2.05 2.39 +-lch_lk_rdc (-) 0.26738 0.35461 0.487805 1 1 +-Mobility_n (um^2/V.sec) 4.3624e+10 3.4121e+10 4.9519e+10 3.2832e+10 3.0344e+10 +-gmp_to_gmn_multiplier (-) 1.38 0.99 1.11 0.9 0.9 +-vpp (V) 0 0 0 1.6 3.3 + +SRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 0 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 0 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 0 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 0 146 146 146 146 146 +-asp_ratio_cell (-) 0 1.46 1.46 1.46 1.46 1.46 + +CAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 1 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 1 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 1 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 1 292 292 292 292 292 +-asp_ratio_cell (-) 1 2.92 2.92 2.92 2.92 2.92 + +DRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-vdd_cell (V) 2 0 0 0 0 1.2 +-Wmemcella (um) 2 0 0 0 0.09 0.065 +-Wmemcellpmos (um) 2 0 0 0 0 0 +-Wmemcellnmos (um) 2 0 0 0 0 0 +-area_cell (um^2) 2 0 0 0 0.11 0.02535 +-asp_ratio_cell (-) 2 0 0 0 1.46 1.5 + +parameters hp lstp lop lp-dram comm-dram +-dram_cell_I_on (A/um) 0 0 0 3.6e-05 2e-05 +-dram_cell_Vdd (V) 0 0 0 1.2 1.3 +-dram_cell_C (F) 0 0 0 2e-14 3e-14 +-dram_cell_I_off_worst_case_len_temp (A/um) 0 0 0 1.96e-11 1e-15 + + +-logic_scaling_co_eff (-) 0.7 +-core_tx_density (1/um^2) 0.875 +-sckt_co_eff (-) 1.1359 +-chip_layout_overhead (-) 1.2 +-macro_layout_overhead (-) 1.1 +-sense_delay (sec) 2e-10 +-sense_dy_power (J) 5.7e-15 + +parameters 0/0 0/1 0/2 0/3 1/0 1/1 1/2 1/3 +-wire_pitch (um) 2.5 4 8 0 2.5 4 8 2 +-barrier_thickness (um) 0 0 0 0 0.006 0.006 0.006 0 +-dishing_thickness (um) 0 0 0 0 0 0 0.0572 0 +-alpha_scatter (-) 1 1 1 0 1 1 1 0 +-aspect_ratio (-) 2.7 2.7 2.8 0 2 2 2.2 0 +-miller_value (-) 1.5 1.5 1.5 0 1.5 1.5 1.5 0 +-horiz_dielectric_constant (-) 2.303 2.303 2.303 0 2.734 2.734 2.734 0 +-vert_dielectric_constant (-) 3.9 3.9 3.9 0 3.9 3.9 3.9 0 +-ild_thickness (um) 0.405 0.405 0.81 0 0.405 0.405 0.77 0 +-fringe_cap (F/um) 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 +-resistivity (u-ohm.m) 0.018 0.018 0.018 0.018 0.022 0.022 0.022 0.022 + +parameters 0/0 0/1 0/2 1/0 1/1 1/2 +-wire_r_per_micron (ohm/um) 0 0 0 0 0 0 0 184.615 +-wire_c_per_micron (F/um) 0 0 0 0 0 0 0 1.57752e-15 +-tsv_pitch (um) 3.2 30 0 5 60 0 +-tsv_diameter (um) 1.6 4.6 0 2.5 7.5 0 +-tsv_length (um) 7 50 0 25 62.5 0 +-tsv_dielec_thickness (um) 0.1 0.2 0 0.1 0.5 0 +-tsv_contact_resistance (ohm) 0.1 0.2 0 0.1 0.2 0 +-tsv_depletion_width (um) 0.6 0.6 0 0.6 0.6 0 +-tsv_liner_dielectric_cons (-) 2.303 2.303 0 2.734 2.734 0 diff --git a/tech_params_control/90nm-old.dat b/tech_params_control/90nm-old.dat new file mode 100644 index 0000000..20aa001 --- /dev/null +++ b/tech_params_control/90nm-old.dat @@ -0,0 +1,301 @@ +#each column represents one technology flavors. +#options are itrs-hp, itrs-lstp, itrs-lop, lp-dram, comm-dram + +========================================================================== +parameters || hp | lstp | lop | lp-dram | comm-dram || + || | | | | || +========================================================================== + || | | | | || +-C_g_ideal || 6.64e-16 | 9.15e-16 | 8.45e-16 | 1.47e-15 | 5.08e-16 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_fringe || 0.08e-15 | 0.08e-15 | 0.08e-15 | 0.08e-15 | 0.08e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_junc || 1e-15 | 1e-15 | 1e-15 | 1e-15 | 1e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-C_junc_sw || 0.25e-15 | 0.25e-15 | 0.25e-15 | 0.25e-15 | 0.25e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-l_phy || 0.037 | 0.075 | 0.053 | 0.12 | 0.09 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-l_elec || 0.0266 | 0.0486 | 0.0354 | 0.0756 | 0.0576 || +____________||___________|___________|___________|___________|___________||__________________________ + || | | | | || +-nmos_effective_resistance_multiplier || 1.54 | 1.92 | 1.77 | 1.65 | 1.62 || +______________________________________||____________|___________|___________|___________|___________|| + || | | | | || +-Vdd || 1.2 | 1.3 | 0.9 | 1.2 | 1.6 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Vth || 0.23707 | 0.48203 | 0.30764 | 0.4545 | 1 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Vdsat || 0.128 | 0.373 | 0.113 | 0.3 | 0.32 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-I_on_n || 1076.9e-6 | 503.6e-6 | 386.6e-6 | 321.6e-6 | 1094.3e-6 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-I_on_p || 712.6e-6 | 235.1e-6 | 209.7e-6 | 203.3e-6 | 547.15e-6 || +____________||___________|___________|___________|___________|___________|| + || + I_off depends on Temperature [temp3-300]/10 is used as index || +_________________________________________________________________________|| + | || | | | | || +-I_off_n|0 || 3.24e-8 | 2.81e-12 | 2.14e-9 | 1.42e-11 | 5.80e-15 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|10 || 4.01e-8 | 4.76e-12 | 2.9e-9 | 2.25e-11 | 1.21e-14 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|20 || 4.90e-8 | 7.82e-12 | 3.87e-9 | 3.46e-11 | 2.42e-14 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|30 || 5.92e-8 | 1.25e-11 | 5.07e-9 | 5.18e-11 | 4.65e-14 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|40 || 7.08e-8 | 1.94e-11 | 6.54e-9 | 7.58e-11 | 8.60e-14 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|50 || 8.38e-8 | 2.94e-11 | 8.27e-8 | 1.08e-10 | 1.54e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|60 || 9.82e-8 | 4.36e-11 | 1.02e-7 | 1.51e-10 | 2.66e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|70 || 1.14e-7 | 6.32e-11 | 1.20e-7 | 2.02e-10 | 4.45e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|80 || 1.29e-7 | 8.95e-11 | 1.36e-8 | 2.57e-10 | 7.17e-13 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|90 || 1.43e-7 | 1.25e-10 | 1.52e-8 | 3.14e-10 | 1.11e-12 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_off_n|100 || 1.54e-7 | 1.7e-10 | 1.73e-8 | 3.85e-10 | 1.67e-12 || +________|___ ||___________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|0 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|10 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|20 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|30 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|40 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|50 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|60 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|70 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|80 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|90 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___||__________|___________|___________|___________|___________|| + | || | | | | || +-I_g_on_n|100 || 1.65e-8 | 3.87e-11 | 4.31e-8 | 0 | 0 || +_________|___ ||_________|___________|___________|___________|___________|| + || | | | | || +-C_ox || 1.79e-14 | 1.22e-14 | 1.59e-14 | 1.22e-14 | 5.65e-15 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-t_ox || 1.2e-3 | 2.2e-3 | 1.5e-3 | 2.2e-3 | 5.5e-3 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-n2p_drv_rt || 2.45 | 2.44 | 2.54 | 1.95 | 2.05 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-lch_lk_rdc || 1 | 1 | 1 | 1 | 1 || +____________||___________|___________|___________|___________|___________|| + || | | | | || +-Mobility_n || 342.16e8 | 356.76e8 | 460.39e8 | 323.95e8 | 302.2e8 || +____________||___________|___________|___________|___________|___________||__________ + || | | | | || +-gmp_to_gmn_multiplier || 1.22 | 0.88 | 0.98 | 0.90 | 0.90 || +_______________________||___________|___________|___________|___________|___________|| + || | | | | || +-vpp || 0 | 0 | 0 | 1.6 | 3.7 || +____________||___________|___________|___________|___________|___________|| + +SRAM +__________________________________________________________________________________ + | || | | | | || +-Wmemcella | 0 || 1.31 | 1.31 | 1.31 | 1.31 | 1.31 || +___________|________||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 0 || 1.23 | 1.23 | 1.23 | 1.23 | 1.23 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 0 || 2.08 | 2.08 | 2.08 | 2.08 | 2.08 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 0 || 146 | 146 | 146 | 146 | 146 || +______________|_____||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 0 || 1.46 | 1.46 | 1.46 | 1.46 | 1.46 || +________________|___||___________|___________|___________|___________|___________|| + +CAM +__________________________________________________________________________________ + | || | | | | || +-Wmemcella | 1 || 1.31 | 1.31 | 1.31 | 1.31 | 1.31 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 1 || 1.23 | 1.23 | 1.23 | 1.23 | 1.23 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 1 || 2.08 | 2.08 | 2.08 | 2.08 | 2.08 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 1 || 292 | 292 | 292 | 292 | 292 || +________________|___||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 1 || 2.92 | 2.92 | 2.92 | 2.92 | 2.92 || +________________|___||___________|___________|___________|___________|___________|| + +DRAM +__________________________________________________________________________________ + | || | | | | || +-vdd_cell | 2 || 0 | 0 | 0 | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcella | 2 || 0 | 0 | 0 | 0.14 | 0.09 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellpmos | 2 || 0 | 0 | 0 | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-Wmemcellnmos | 2 || 0 | 0 | 0 | 0 | 0 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-area_cell | 2 || 0 | 0 | 0 | 0.168 | 0.0486 || +_______________|____||___________|___________|___________|___________|___________|| + | || | | | | || +-asp_ratio_cell | 2 || 2 | 0 | 0 | 1.46 | 1.5 || +________________|___||___________|___________|___________|___________|___________|| + +______________________________________________________________________________ + || | | | | || +-dram_cell_I_on || 0 | 0 | 0 | 45e-6 | 20e-6 || +________________||___________|___________|___________|___________|___________|| + || | | | | || +-dram_cell_Vdd || 0 | 0 | 0 | 1.2 | 1.6 || +________________||___________|___________|___________|___________|___________|| + || | | | | || +-dram_cell_C || 0 | 0 | 0 | 20e-15 | 30e-15 || +________________||___________|___________|___________|___________|___________||____________________ + || | | | | || +-dram_cell_I_off_worst_case_len_temp || 0 | 0 | 0 | 21.1e-12 | 1e-15 || +_____________________________________||___________|___________|___________|___________|___________|| + + +__________________________________________________________________________ + || +-logic_scaling_co_eff 1 || +_________________________________________________________________________|| + || +-core_tx_density 0.6125 || +_________________________________________________________________________|| + || +-sckt_co_eff 1.1539 || +_________________________________________________________________________|| + || +-chip_layout_overhead 1.2 || +_________________________________________________________________________|| + || +-macro_layout_overhead 1.1 || +_________________________________________________________________________|| +__________________________________________________________________________ + || +-sense_delay .28e-9 || +_________________________________________________________________________|| + || +-sense_dy_power 14.7e-15 || +_________________________________________________________________________|| + + + +_____________________________________________________________________________________________________________________________________________________ + || | | | | | | | | | || +-wire_pitch || 2.5 | 4 | 8 | 0 | 0 | 2.5 | 4 | 8 | 0.18 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-barrier_thickness || 0.01 | 0.01 | 0.01 | 0.01 | 0.01 | 0.008 | 0.008 | 0.008 | 0.008 | 0.008 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-dishing_thickness || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-alpha_scatter || 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-aspect_ratio || 2.4 | 2.4 | 2.7 | 0 | 0 | 2.0 | 2.0 | 2.2 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-miller_value || 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 | 1.5 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-horiz_dielectric_constant || 2.709 | 2.709 | 2.709 | 2.709 | 2.709 | 3.038 | 3.038 | 3.038 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-vert_dielectric_constant || 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 | 3.9 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-ild_thickness || 0.48 | 0.48 | 0.96 | 0 | 0 | 0.48 | 0.48 | 1.1 | 0 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-fringe_cap || 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 | 0.115e-15 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-wire_r_per_micron || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 133.33 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + || | | | | | | | | | || +-wire_c_per_micron || 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1.302e-15 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|___________|___________|___________|___________|| + +_____________________________________________________________________________________________________ + || | | | | | || +-tsv_pitch || 4.0 | 45 | 0 | 6.9 | 90 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_diameter || 2.0 | 2.0 | 0 | 3.5 | 11.3 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_length || 8 | 60 | 0 | 30 | 75 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_dielec_thickness || 0.1 | 0.2 | 0 | 0.1 | 0.5 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_contact_resistance || 0.1 | 0.2 | 0 | 0.1 | 0.2 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_depletion_width || 0.6 | 0.6 | 0 | 0.6 | 0.6 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + || | | | | | || +-tsv_liner_dielectric_cons || 2.709 | 2.709 | 0 | 3.038 | 3.038 | 0 || +___________________________||___________|___________|___________|___________|___________|___________|| + + + + + + + + + diff --git a/tech_params_control/90nm.dat b/tech_params_control/90nm.dat new file mode 100644 index 0000000..f28033a --- /dev/null +++ b/tech_params_control/90nm.dat @@ -0,0 +1,110 @@ +parameters (unit) hp lstp lop lp-dram comm-dram +-C_g_ideal (F/um) 6.64e-16 9.15e-16 8.45e-16 1.47e-15 5.08e-16 +-C_fringe (F/um) 8e-17 8e-17 8e-17 8e-17 8e-17 +-C_junc (F/um^2) 1e-15 1e-15 1e-15 1e-15 1e-15 +-C_junc_sw (F/um^2) 2.5e-16 2.5e-16 2.5e-16 2.5e-16 2.5e-16 +-l_phy (um) 0.037 0.075 0.053 0.12 0.09 +-l_elec (um) 0.0266 0.0486 0.0354 0.0756 0.0576 +-nmos_effective_resistance_multiplier (-) 1.54 1.92 1.77 1.65 1.62 +-Vdd (V) 1.2 1.3 0.9 1.2 1.6 +-Vth (V) 0.23707 0.48203 0.30764 0.4545 1 +-Vdsat (V) 0.128 0.373 0.113 0.3 0.32 +-I_on_n (A/um) 0.0010769 0.0005036 0.0003866 0.0003216 0.0010943 +-I_on_p (A/um) 0.0007126 0.0002351 0.0002097 0.0002033 0.00054715 + +parameters (unit) temp hp lstp lop lp-dram comm-dram +-I_off_n (A/um) 0 3.24e-08 2.81e-12 2.14e-09 1.42e-11 5.8e-15 +-I_off_n (A/um) 10 4.01e-08 4.76e-12 2.9e-09 2.25e-11 1.21e-14 +-I_off_n (A/um) 20 4.9e-08 7.82e-12 3.87e-09 3.46e-11 2.42e-14 +-I_off_n (A/um) 30 5.92e-08 1.25e-11 5.07e-09 5.18e-11 4.65e-14 +-I_off_n (A/um) 40 7.08e-08 1.94e-11 6.54e-09 7.58e-11 8.6e-14 +-I_off_n (A/um) 50 8.38e-08 2.94e-11 8.27e-08 1.08e-10 1.54e-13 +-I_off_n (A/um) 60 9.82e-08 4.36e-11 1.02e-07 1.51e-10 2.66e-13 +-I_off_n (A/um) 70 1.14e-07 6.32e-11 1.2e-07 2.02e-10 4.45e-13 +-I_off_n (A/um) 80 1.29e-07 8.95e-11 1.36e-08 2.57e-10 7.17e-13 +-I_off_n (A/um) 90 1.43e-07 1.25e-10 1.52e-08 3.14e-10 1.11e-12 +-I_off_n (A/um) 100 1.54e-07 1.7e-10 1.73e-08 3.85e-10 1.67e-12 +-I_g_on_n (A/um) 0 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 10 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 20 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 30 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 40 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 50 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 60 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 70 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 80 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 90 1.65e-08 3.87e-11 4.31e-08 0 0 +-I_g_on_n (A/um) 100 1.65e-08 3.87e-11 4.31e-08 0 0 + +parameters (unit) hp lstp lop lp-dram comm-dram +-C_ox (F/um^2) 1.79e-14 1.22e-14 1.59e-14 1.22e-14 5.65e-15 +-t_ox (um) 0.0012 0.0022 0.0015 0.0022 0.0055 +-n2p_drv_rt (-) 2.45 2.44 2.54 1.95 2.05 +-lch_lk_rdc (-) 1 1 1 1 1 +-Mobility_n (um^2/V.sec) 3.4216e+10 3.5676e+10 4.6039e+10 3.2395e+10 3.022e+10 +-gmp_to_gmn_multiplier (-) 1.22 0.88 0.98 0.9 0.9 +-vpp (V) 0 0 0 1.6 3.7 + +SRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 0 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 0 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 0 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 0 146 146 146 146 146 +-asp_ratio_cell (-) 0 1.46 1.46 1.46 1.46 1.46 + +CAM +parameters cell_type hp lstp lop lp-dram comm-dram +-Wmemcella (um) 1 1.31 1.31 1.31 1.31 1.31 +-Wmemcellpmos (um) 1 1.23 1.23 1.23 1.23 1.23 +-Wmemcellnmos (um) 1 2.08 2.08 2.08 2.08 2.08 +-area_cell (um^2) 1 292 292 292 292 292 +-asp_ratio_cell (-) 1 2.92 2.92 2.92 2.92 2.92 + +DRAM +parameters cell_type hp lstp lop lp-dram comm-dram +-vdd_cell (V) 2 0 0 0 1.2 1.6 +-Wmemcella (um) 2 0 0 0 0.14 0.09 +-Wmemcellpmos (um) 2 0 0 0 0 0 +-Wmemcellnmos (um) 2 0 0 0 0 0 +-area_cell (um^2) 2 0 0 0 0.168 0.0486 +-asp_ratio_cell (-) 2 0 0 0 1.46 1.5 + +parameters hp lstp lop lp-dram comm-dram +-dram_cell_I_on (A/um) 0 0 0 4.5e-05 2e-05 +-dram_cell_Vdd (V) 0 0 0 1.2 1.6 +-dram_cell_C (F) 0 0 0 2e-14 3e-14 +-dram_cell_I_off_worst_case_len_temp (A/um) 0 0 0 2.11e-11 1e-15 + +-logic_scaling_co_eff (-) 1 +-core_tx_density (1/um^2) 0.6125 +-sckt_co_eff (-) 1.1539 +-chip_layout_overhead (-) 1.2 +-macro_layout_overhead (-) 1.1 +-sense_delay (sec) 2.8e-10 +-sense_dy_power (J) 1.47e-14 + +parameters 0/0 0/1 0/2 0/3 1/0 1/1 1/2 1/3 +-wire_pitch (um) 2.5 4 8 0 2.5 4 8 2 +-barrier_thickness (um) 0.01 0.01 0.01 0 0.008 0.008 0.008 0 +-dishing_thickness (um) 0 0 0 0 0 0 0.0792 0 +-alpha_scatter (-) 1 1 1 0 1 1 1 0 +-aspect_ratio (-) 2.4 2.4 2.7 0 2 2 2.2 0 +-miller_value (-) 1.5 1.5 1.5 0 1.5 1.5 1.5 0 +-horiz_dielectric_constant (-) 2.709 2.709 2.709 0 3.038 3.038 3.038 0 +-vert_dielectric_constant (-) 3.9 3.9 3.9 0 3.9 3.9 3.9 0 +-ild_thickness (um) 0.48 0.48 0.96 0 0.48 0.48 1.1 0 +-fringe_cap (F/um) 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 1.15e-16 +-resistivity (u-ohm.m) 0.022 0.022 0.022 0.022 0.022 0.022 0.022 0.022 + +parameters 0/0 0/1 0/2 1/0 1/1 1/2 +-wire_r_per_micron (ohm/um) 0 0 0 0 0 0 0 133.333 +-wire_c_per_micron (F/um) 0 0 0 0 0 0 0 1.30208e-15 +-tsv_pitch (um) 4 45 0 6.9 90 0 +-tsv_diameter (um) 2 6.9 0 3.5 11.3 0 +-tsv_length (um) 8 60 0 30 75 0 +-tsv_dielec_thickness (um) 0.1 0.2 0 0.1 0.5 0 +-tsv_contact_resistance (ohm) 0.1 0.2 0 0.1 0.2 0 +-tsv_depletion_width (um) 0.6 0.6 0 0.6 0.6 0 +-tsv_liner_dielectric_cons (-) 2.709 2.709 0 3.038 3.038 0 +