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Linking up to SPAD boundary --- .../assembler/instructions/cinst/bload.py | 4 + .../assembler/instructions/cinst/bones.py | 4 + .../assembler/instructions/cinst/cload.py | 4 + .../assembler/instructions/cinst/cstore.py | 4 + .../assembler/instructions/instruction.py | 4 + .../hec-assembler-tools/he_link.py | 35 +- .../hec-assembler-tools/linker/__init__.py | 7 +- .../linker/he_link_utils.py | 4 +- .../linker/instructions/cinst/bload.py | 36 +- .../linker/instructions/cinst/bones.py | 33 +- .../linker/instructions/cinst/cload.py | 44 +- .../linker/instructions/cinst/cstore.py | 35 +- .../linker/instructions/cinst/nload.py | 33 +- .../linker/instructions/instruction.py | 20 + .../linker/instructions/minst/mload.py | 58 +- .../linker/instructions/minst/mstore.py | 62 +- .../linker/kern_trace/__init__.py | 5 +- .../linker/kern_trace/kern_remap.py | 23 +- .../linker/kern_trace/kernel_info.py | 302 ++++++++++ .../linker/kern_trace/trace_info.py | 48 -- .../linker/linker_run_config.py | 3 + .../hec-assembler-tools/linker/loader.py | 2 +- .../linker/steps/program_linker.py | 539 ++++++++++++++---- .../linker/steps/program_linker_utils.py | 117 ++++ .../linker/steps/variable_discovery.py | 39 +- .../tests/unit_tests/test_he_link.py | 183 +++++- .../test_linker/test_he_link_utils.py | 33 +- .../test_kern_trace/test_kern_remap.py | 92 +-- .../test_kern_trace/test_kernel_info.py | 66 +++ .../test_kern_trace/test_trace_info.py | 61 +- .../test_steps/test_program_linker.py | 256 ++++++--- .../test_steps/test_variable_discovery.py | 194 ++++--- 32 files changed, 1821 insertions(+), 529 deletions(-) create mode 100644 assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py create mode 100644 assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py create mode 100644 assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py diff --git a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bload.py b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bload.py index 890da01b..fa25d16f 100644 --- a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bload.py +++ b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bload.py @@ -21,6 +21,10 @@ class Instruction(CInstruction): spad_src (int): SPAD address of the metadata word to load. """ + @classmethod + def get_latency(cls) -> int: + return cls._OP_DEFAULT_LATENCY + @classmethod def _get_op_name_asm(cls) -> str: """ diff --git a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bones.py b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bones.py index f40df3c4..c7d630bb 100644 --- a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bones.py +++ b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/bones.py @@ -19,6 +19,10 @@ class Instruction(CInstruction): spad_src (int): SPAD address of the metadata variable to load. """ + @classmethod + def get_latency(cls) -> int: + return cls._OP_DEFAULT_LATENCY + @classmethod def _get_op_name_asm(cls) -> str: """ diff --git a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cload.py b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cload.py index 233ce2fc..b0b129b6 100644 --- a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cload.py +++ b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cload.py @@ -19,6 +19,10 @@ class Instruction(CInstruction): https://github.com/IntelLabs/hec-assembler-tools/blob/master/docsrc/inst_spec/cinst/cinst_cload.md """ + @classmethod + def get_latency(cls) -> int: + return cls._OP_DEFAULT_LATENCY + @classmethod def _get_op_name_asm(cls) -> str: """ diff --git a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cstore.py b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cstore.py index b68950e6..801d39f2 100644 --- a/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cstore.py +++ b/assembler_tools/hec-assembler-tools/assembler/instructions/cinst/cstore.py @@ -22,6 +22,10 @@ class Instruction(CInstruction): https://github.com/IntelLabs/hec-assembler-tools/blob/master/docsrc/inst_spec/cinst/cinst_cstore.md """ + @classmethod + def get_latency(cls) -> int: + return cls._OP_DEFAULT_LATENCY + @classmethod def _get_op_name_asm(cls) -> str: """ diff --git a/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py b/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py index af1c51e4..e3916d95 100644 --- a/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py +++ b/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py @@ -303,6 +303,10 @@ def latency(self) -> int: Returns: int: The latency. + + Note: + Accessing `latency` as a property on the class (e.g., `MyInst.latency`) returns a property object, + not an integer. Use an instance (e.g., `my_inst.latency`) or the class variable `_OP_DEFAULT_LATENCY`. """ return self.__latency diff --git a/assembler_tools/hec-assembler-tools/he_link.py b/assembler_tools/hec-assembler-tools/he_link.py index 4adeb1a2..bff68aea 100644 --- a/assembler_tools/hec-assembler-tools/he_link.py +++ b/assembler_tools/hec-assembler-tools/he_link.py @@ -44,7 +44,7 @@ from linker.kern_trace.trace_info import TraceInfo from linker.linker_run_config import LinkerRunConfig from linker.loader import Loader -from linker.steps import program_linker +from linker.steps.program_linker import LinkedProgram from linker.steps.variable_discovery import check_unused_variables, scan_variables @@ -94,6 +94,8 @@ def main(run_config: LinkerRunConfig, verbose_stream=None): print("", file=verbose_stream) print("Interpreting variable meta information...", file=verbose_stream) + p_linker = LinkedProgram(keep_spad_boundary=True, keep_hbm_boundary=run_config.keep_hbm_boundary) + # Process kernel DInstructions when using trace file program_dinstrs = [] if run_config.using_trace_file: @@ -105,7 +107,7 @@ def main(run_config: LinkerRunConfig, verbose_stream=None): remap_vars(kernels_info, dinstrs_per_kernel, kernel_ops, verbose_stream) # Concatenate all mem info objects into one - program_dinstrs = program_linker.LinkedProgram.join_dinst_kernels(dinstrs_per_kernel) + program_dinstrs = p_linker.join_n_prune_dinst_kernels(dinstrs_per_kernel) # Write new program memory model to an output file if program_info.mem is None: @@ -119,7 +121,7 @@ def main(run_config: LinkerRunConfig, verbose_stream=None): print(" Finding all program variables...", file=verbose_stream) print(" Scanning", file=verbose_stream) - scan_variables(kernels_info=kernels_info, mem_model=mem_model, verbose_stream=verbose_stream) + scan_variables(p_linker, kernels_info, mem_model, verbose_stream) check_unused_variables(mem_model) @@ -127,7 +129,7 @@ def main(run_config: LinkerRunConfig, verbose_stream=None): print("Linking started", file=verbose_stream) # Link kernels and generate outputs - program_linker.LinkedProgram.link_kernels_to_files(kernels_info, program_info, mem_model, verbose_stream=verbose_stream) + p_linker.link_kernels_to_files(kernels_info, program_info, mem_model, verbose_stream=verbose_stream) # Flush cached kernels Loader.flush_cache() @@ -247,7 +249,25 @@ def parse_args(): "--no_hbm", dest="has_hbm", action="store_false", - help="If set, this flag tells he_prep there is no HBM in the target chip.", + help="If set, this flag tells he_link there is no HBM in the target chip.", + ) + parser.add_argument( + "--keep_spad_boundary", + action="store_true", + help=( + "If used along with '--use_trace_file', this flag tells he_link to keep a data boundary " + "among kernels in the final cinst output. This can be useful for debugging purposes. " + "This flag is ignored if '--keep_hbm_boundary' is set." + ), + ) + parser.add_argument( + "--keep_hbm_boundary", + action="store_true", + help=( + "If used along with '--use_trace_file', this flag tells he_link to keep a data boundary " + "among kernels in the final minst output. This can be useful for debugging purposes. " + "This flag will override the '--keep_spad_boundary' flag." + ), ) parser.add_argument( "--suppress_comments", @@ -276,6 +296,11 @@ def parse_args(): if p_args.input_dir == "" and p_args.trace_file: p_args.input_dir = os.path.dirname(p_args.trace_file) + # If no trace file is used boundaries should be kept + p_args.keep_hbm_boundary = True if not p_args.using_trace_file else p_args.keep_hbm_boundary + # If HBM boundary is kept, SPAD boundary is kept as a consequence + p_args.keep_spad_boundary = True if p_args.keep_hbm_boundary else p_args.keep_spad_boundary + # Enforce only if use_trace_file is not set if not p_args.using_trace_file: if p_args.input_mem_file == "": diff --git a/assembler_tools/hec-assembler-tools/linker/__init__.py b/assembler_tools/hec-assembler-tools/linker/__init__.py index c506d314..4da19aa1 100644 --- a/assembler_tools/hec-assembler-tools/linker/__init__.py +++ b/assembler_tools/hec-assembler-tools/linker/__init__.py @@ -214,8 +214,14 @@ def add_variable(self, var_name: str): # with predefined HBM address if var_name in self.__mem_info_fixed_addr_vars: var_info.uses = float("inf") + else: + var_info.uses = 0 self.hbm.force_allocate(var_info, self.__mem_info_vars[var_name].hbm_address) + else: + # Variables not explicitly marked in mem file are allocated on demand + var_info.hbm_address = -1 self.variables[var_name] = var_info + var_info.uses += 1 def use_variable(self, var_name: str, kernel: int) -> int: @@ -234,7 +240,6 @@ def use_variable(self, var_name: str, kernel: int) -> int: var_info.uses -= 1 # Mark the usage var_info.last_kernel_used = kernel - if var_info.hbm_address < 0: # Find HBM address for variable self.hbm.allocate(var_info) diff --git a/assembler_tools/hec-assembler-tools/linker/he_link_utils.py b/assembler_tools/hec-assembler-tools/linker/he_link_utils.py index cc364d78..1b31fd1a 100644 --- a/assembler_tools/hec-assembler-tools/linker/he_link_utils.py +++ b/assembler_tools/hec-assembler-tools/linker/he_link_utils.py @@ -111,7 +111,7 @@ def update_input_prefixes(kernel_ops, run_config): def remap_vars(kernels_info: list[KernelInfo], kernels_dinstrs, kernel_ops, verbose_stream): """ @brief Process kernel DInstructions to remap variables based on kernel operations - and update KernelInfo with remap_dict. + and update KernelInfo with hbm_remap_dict. @param kernels_info List of input KernelInfo. @param kernels_dinstrs List of kernel DInstructions. @@ -131,7 +131,7 @@ def remap_vars(kernels_info: list[KernelInfo], kernels_dinstrs, kernel_ops, verb # Remap dintrs' variables in kernel_dinstrs and return a mapping dict var_map = remap_dinstrs_vars(kernel_dinstrs, kernel_op) - kernel_info.remap_dict = var_map + kernel_info.hbm_remap_dict = var_map def initialize_memory_model(run_config, kernel_dinstrs=None, verbose_stream=None): diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py index ee7521f4..d81fc9b6 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py @@ -50,15 +50,39 @@ def __init__(self, tokens: list, comment: str = ""): @throws ValueError If the number of tokens is invalid or the instruction name is incorrect. """ super().__init__(tokens, comment=comment) + self._var_name = tokens[3] + # set spad_address to '0' if tokens[3] is a variable name + if not tokens[3].isdigit(): + self.tokens[3] = "0" # Should be set to SPAD address to write back. @property - def source(self) -> str: + def var_name(self) -> str: + """ + @brief Gets the name of the variable. + + This is a Variable name when loaded with no_hbm. + + @return The name of the variable. + """ + return self._var_name + + @var_name.setter + def var_name(self, value: str): + """ + @brief Sets the name of the variable. + + @param value The name of the variable to set. + """ + self._var_name = value + + @property + def spad_address(self) -> int: """ @brief Name of the source. - This is a Variable name when loaded. Should be set to HBM address to write back. + Spad address when there is HBM. """ - return self.tokens[3] + return int(self.tokens[3]) - @source.setter - def source(self, value: str): - self.tokens[3] = value + @spad_address.setter + def spad_address(self, value: int): + self.tokens[3] = str(value) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py index a0e34fa6..65fd0a5f 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py @@ -50,15 +50,36 @@ def __init__(self, tokens: list, comment: str = ""): @throws ValueError If the number of tokens is invalid or the instruction name is incorrect. """ super().__init__(tokens, comment=comment) + self._var_name = tokens[2] + if not tokens[2].isdigit(): + self.tokens[2] = "0" # Should be set to SPAD address to write back. @property - def source(self) -> str: + def var_name(self) -> str: + """ + @brief Gets the name of the variable. + + This is a Variable name when loaded and there is no HBM. + """ + return self._var_name + + @var_name.setter + def var_name(self, value: str): + """ + @brief Sets the name of the variable. + + @param value The name of the variable to set. + """ + self._var_name = value + + @property + def spad_address(self) -> int: """ @brief Name of the source. - This is a Variable name when loaded. Should be set to HBM address to write back. + Spad address when there is HBM. """ - return self.tokens[2] + return int(self.tokens[2]) - @source.setter - def source(self, value: str): - self.tokens[2] = value + @spad_address.setter + def spad_address(self, value: int): + self.tokens[2] = str(value) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py index f17f0909..74ccbb8f 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py @@ -50,15 +50,47 @@ def __init__(self, tokens: list, comment: str = ""): @throws ValueError If the number of tokens is invalid or the instruction name is incorrect. """ super().__init__(tokens, comment=comment) + self._var_name = tokens[3] + if not tokens[3].isdigit(): + self.tokens[3] = "-1" # Should be set to SPAD address to write back. @property - def source(self) -> str: + def var_name(self) -> str: + """ + @brief Gets the name of the original source variable. + + This is a Variable name when there is no HBM. + """ + return self._var_name + + @var_name.setter + def var_name(self, value: str): + self._var_name = value + + @property + def spad_address(self) -> int: """ @brief Name of the source. - This is a Variable name when loaded. Should be set to HBM address to write back. + SPAD address when loaded and there is HBM. + """ + return int(self.tokens[3]) + + @spad_address.setter + def spad_address(self, value: int): + self.tokens[3] = str(value) + + @property + def register(self) -> str: + """ + @brief Gets the name of the destination register. """ - return self.tokens[3] + return self.tokens[2] - @source.setter - def source(self, value: str): - self.tokens[3] = value + @register.setter + def register(self, value: str): + """ + @brief Sets the name of the destination register. + + @param value The name of the register to set. + """ + self.tokens[2] = value diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py index d8d34077..7be339f2 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py @@ -50,22 +50,43 @@ def __init__(self, tokens: list, comment: str = ""): @throws ValueError If the number of tokens is invalid or the instruction name is incorrect. """ super().__init__(tokens, comment=comment) + self._var_name = tokens[2] + if not tokens[2].isdigit(): + self.tokens[2] = "0" # Should be set to SPAD address to write back. @property - def dest(self) -> str: + def var_name(self) -> str: + """ + @brief Gets the name of the variable. + + @return The name of the variable. + """ + return self._var_name + + @var_name.setter + def var_name(self, value: str): + """ + @brief Sets the name of the variable. + + @param value The name of the variable to set. + """ + self._var_name = value + + @property + def spad_address(self) -> int: """ @brief Name of the destination. - This is a Variable name when loaded. Should be set to HBM address to write back. + Should be set to HBM address to write back. - @return The destination variable name or address. + @return The destination variable address. """ - return self.tokens[2] + return int(self.tokens[2]) - @dest.setter - def dest(self, value: str): + @spad_address.setter + def spad_address(self, value: int): """ @brief Sets the destination of the instruction. @param value The new destination value to set. """ - self.tokens[2] = value + self.tokens[2] = str(value) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py index d6e43f21..596100a4 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py @@ -51,15 +51,36 @@ def __init__(self, tokens: list, comment: str = ""): @throws ValueError If the number of tokens is invalid or the instruction name is incorrect. """ super().__init__(tokens, comment=comment) + self._var_name = tokens[3] + if not tokens[3].isdigit(): + self.tokens[3] = "0" # Should be set to SPAD address to write back. @property - def source(self) -> str: + def var_name(self) -> str: + """ + @brief Gets the name of the variable. + + This is a Variable name when there is no HBM. + """ + return self._var_name + + @var_name.setter + def var_name(self, value: str): + """ + @brief Sets the name of the variable. + + This is a Variable name. + """ + self._var_name = value + + @property + def spad_address(self) -> int: """ @brief Name of the source. - This is a Variable name when loaded. Should be set to HBM address to write back. + SPAD address when loaded and there is HBM. """ - return self.tokens[3] + return int(self.tokens[3]) - @source.setter - def source(self, value: str): - self.tokens[3] = value + @spad_address.setter + def spad_address(self, value: int): + self.tokens[3] = str(value) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/instruction.py b/assembler_tools/hec-assembler-tools/linker/instructions/instruction.py index 74ac6026..74c63572 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/instruction.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/instruction.py @@ -196,3 +196,23 @@ def to_line(self) -> str: tokens_str = ", ".join(self.tokens) return f"{tokens_str}{comment_str}" + + @property + def idx(self) -> int: + """ + @brief Gets the instruction index. + + This is the line number in the MInstruction file. + + @return The instruction index. + """ + return int(self.tokens[0]) + + @idx.setter + def idx(self, value: int): + """ + @brief Sets the instruction index. + + @param value The instruction index to set. + """ + self.tokens[0] = str(value) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py b/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py index 0900b94e..592b3bb3 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py @@ -49,23 +49,65 @@ def __init__(self, tokens: list, comment: str = ""): @throws ValueError If the number of tokens is invalid or the instruction name is incorrect. """ super().__init__(tokens, comment=comment) + self._var_name = tokens[3] + self.tokens[3] = "0" # Should be set to HBM address to write back. @property - def source(self) -> str: + def var_name(self) -> str: + """ + @brief Gets the name of the source variable. + + This is a Variable name. + + @return The name of the variable. + """ + return self._var_name + + @var_name.setter + def var_name(self, value: str): + """ + @brief Sets the name of the variable. + + @param value The name of the variable to set. + """ + self._var_name = value + + @property + def hbm_address(self) -> int: """ @brief Gets the name of the source. - This is a Variable name when loaded. Should be set to HBM address to write back. + Should be set to HBM address to write back. @return The name of the source. """ - return self.tokens[3] + return int(self.tokens[3]) + + @hbm_address.setter + def hbm_address(self, value: int): + """ + @brief Sets the address of the source. + + @param value The address of the source to set. + """ + self.tokens[3] = str(value) + + @property + def spad_address(self) -> int: + """ + @brief Gets the destination index. + + This is the index in the scratchpad where the data will be loaded. + + @return The destination index. + """ + return int(self.tokens[2]) - @source.setter - def source(self, value: str): + @spad_address.setter + def spad_address(self, value: int): """ - @brief Sets the name of the source. + @brief Sets the destination index. - @param value The name of the source to set. + @param value The destination index to set. """ - self.tokens[3] = value + self.tokens[2] = str(value) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/minst/mstore.py b/assembler_tools/hec-assembler-tools/linker/instructions/minst/mstore.py index 921dcff7..b9d2ab6c 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/minst/mstore.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/minst/mstore.py @@ -48,24 +48,66 @@ def __init__(self, tokens: list, comment: str = ""): @param comment An optional comment for the instruction. @throws ValueError If the number of tokens is invalid or the instruction name is incorrect. """ + self._var_name = tokens[2] super().__init__(tokens, comment=comment) + self.tokens[2] = "0" # Should be set to HBM address to write back. @property - def dest(self) -> str: + def var_name(self) -> str: """ - @brief Gets the name of the destination. + @brief Gets the name of the destination variable. - This is a Variable name when loaded. Should be set to HBM address to write back. + This is a Variable name when loaded. - @return The name of the destination. + @return The name of the variable. """ - return self.tokens[2] + return self._var_name - @dest.setter - def dest(self, value: str): + @var_name.setter + def var_name(self, value: str): """ - @brief Sets the name of the destination. + @brief Sets the name of the variable. - @param value The name of the destination to set. + @param value The name of the variable to set. """ - self.tokens[2] = value + self._var_name = value + + @property + def spad_address(self) -> int: + """ + @brief Gets the source index. + + This is the index in the scratchpad from which data will be stored. + + @return The source index. + """ + return int(self.tokens[3]) + + @spad_address.setter + def spad_address(self, value: int): + """ + @brief Sets the source index. + + @param value The source index to set. + """ + self.tokens[3] = str(value) + + @property + def hbm_address(self) -> int: + """ + @brief Gets the address of the destination. + + Should be set to HBM address to write back. + + @return The address of the destination. + """ + return int(self.tokens[2]) + + @hbm_address.setter + def hbm_address(self, value: int): + """ + @brief Sets the address of the destination. + + @param value The address of the destination to set. + """ + self.tokens[2] = str(value) diff --git a/assembler_tools/hec-assembler-tools/linker/kern_trace/__init__.py b/assembler_tools/hec-assembler-tools/linker/kern_trace/__init__.py index b57437b8..29375afd 100644 --- a/assembler_tools/hec-assembler-tools/linker/kern_trace/__init__.py +++ b/assembler_tools/hec-assembler-tools/linker/kern_trace/__init__.py @@ -10,8 +10,9 @@ from linker.kern_trace.context_config import ContextConfig from linker.kern_trace.kern_remap import remap_dinstrs_vars, remap_m_c_instrs_vars from linker.kern_trace.kern_var import KernVar +from linker.kern_trace.kernel_info import InstrAct, KernelInfo, MinstrMapEntry from linker.kern_trace.kernel_op import KernelOp -from linker.kern_trace.trace_info import KernelInfo, TraceInfo +from linker.kern_trace.trace_info import TraceInfo __all__ = [ "KernVar", @@ -21,4 +22,6 @@ "remap_dinstrs_vars", "remap_m_c_instrs_vars", "KernelInfo", + "InstrAct", + "MinstrMapEntry", ] diff --git a/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py b/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py index 1ea9bbd6..07fbeaba 100644 --- a/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py +++ b/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py @@ -75,26 +75,25 @@ def remap_dinstrs_vars(kernel_dinstrs: list[DInstruction], kernel_op: KernelOp) return var_mapping -def remap_m_c_instrs_vars(kernel_instrs: list, remap_dict: dict[str, str]) -> None: +def remap_m_c_instrs_vars(kernel_instrs: list, hbm_remap_dict: dict[str, str]) -> None: """ @brief Remaps variable names in M or C Instructions based on a provided remap dictionary. This function updates the variable names in each Instruction by replacing them with their corresponding values from the remap dictionary. - @param kernel_instrs: List of M or M Instruction objects to process - @param remap_dict: Dictionary mapping old variable names to new variable names + @param kernel_minstrs: List of M or C Instruction objects to process + @param hbm_remap_dict: Dictionary mapping old variable names to new variable names """ - if remap_dict: + if hbm_remap_dict: for instr in kernel_instrs: if not isinstance(instr, MInstruction | CInstruction): raise TypeError(f"Item {instr} is not a valid M or C Instruction.") - if isinstance(instr, minst.MLoad | cinst.BLoad | cinst.CLoad | cinst.BOnes | cinst.NLoad): - if instr.source in remap_dict: - instr.comment = instr.comment.replace(instr.source, remap_dict[instr.source]) - instr.source = remap_dict[instr.source] - elif isinstance(instr, minst.MStore | cinst.CStore): - if instr.dest in remap_dict: - instr.comment = instr.comment.replace(instr.dest, remap_dict[instr.dest]) - instr.dest = remap_dict[instr.dest] + if isinstance(instr, (minst.MLoad, minst.MStore, cinst.CLoad, cinst.CStore)): + if instr.var_name in hbm_remap_dict: + instr.comment = instr.comment.replace(instr.var_name, hbm_remap_dict[instr.var_name]) + instr.var_name = hbm_remap_dict[instr.var_name] + else: + for key, value in hbm_remap_dict.items(): + instr.comment = instr.comment.replace(key, value) diff --git a/assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py b/assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py new file mode 100644 index 00000000..f9b4df0d --- /dev/null +++ b/assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py @@ -0,0 +1,302 @@ +# Copyright (C) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +# These contents may have been developed with support from one or more Intel-operated +# generative artificial intelligence solutions + +"""@brief Module for handling kernel operation tracing and analysis.""" + +from enum import Enum + +from linker.instructions import cinst, minst +from linker.instructions.cinst.cinstruction import CInstruction +from linker.instructions.minst.minstruction import MInstruction +from linker.instructions.xinst.xinstruction import XInstruction + + +class InstrAct(Enum): + """@class InstrAct + @brief Enum for actions to be taken on instructions. + """ + + KEEP_HBM = 0 + KEEP_SPAD = 1 + SKIP = 2 + + +class MinstrMapEntry: + """@class MinstrMapEntry + @brief Structure for mapping MInstruction to its SPAD address and action. + """ + + def __init__(self, spad_addr: int, minstr: MInstruction, action: InstrAct): + self.spad_addr = spad_addr + self.minstr = minstr + self.action = action + + +class CinstrMapEntry: + """@class CinstrMapEntry + @brief Structure for mapping CInstruction to its register name and action. + """ + + def __init__(self, reg_name: str, cinstr: CInstruction, action: InstrAct): + self.reg_name = reg_name + self.cinstr = cinstr + self.action = action + + +class KernelInfo: + """ + @class KernelInfo + @brief Structure for kernel files. + + @details This class holds information about the kernel files used in the linker. + + @brief Dictionary for remapping variable names in DInstructions. + + """ + + # Dictionary with keys 'directory', 'prefix', 'minst', 'cinst', 'xinst', and optional 'mem' + _file_paths: dict[str, str] + + _minstrs: list[MInstruction] + _cinstrs: list[CInstruction] + _xinstrs: list[XInstruction] + + _hbm_remap_dict: dict[str, str] + _spad_size: int # Reflects the spad memory used by the kernel + + def __init__(self, config: dict): + """ + @brief Initializes KernelInfo with a configuration dictionary. + + @param config: Dictionary with keys 'directory', 'prefix', 'minst', 'cinst', 'xinst', and optional 'mem'. + """ + self.file_paths = config + + self._hbm_remap_dict = {} + self._spad_size = 0 # Reflects the spad memory used by the kernel + + self._minstrs = [] # Placeholder for kernel minst instructions + self._minstrs_map: list[MinstrMapEntry] = [] + self._cinstrs = [] # Placeholder for kernel cinst instructions + self._cinstrs_map: list[CinstrMapEntry] = [] + self._xinstrs = [] # Placeholder for kernel xinst instructions + + @property + def files(self) -> list[str]: + """ + @brief Returns a list of file names associated with the kernel. + """ + return [self.minst, self.cinst, self.xinst] + ([self.mem] if self.mem else []) + + @property + def hbm_remap_dict(self) -> dict[str, str]: + """ + @brief Returns the remap dictionary for variable names in DInstructions. + """ + return self._hbm_remap_dict + + @hbm_remap_dict.setter + def hbm_remap_dict(self, value: dict[str, str]): + """ + @brief Sets the remap dictionary for variable names in DInstructions. + + @param value: Dictionary mapping old variable names to new variable names. + """ + if not isinstance(value, dict): + raise TypeError("Remap dictionary must be of type dict.") + self._hbm_remap_dict = value + + @property + def spad_size(self) -> int: + """ + @brief Returns the scratchpad offset. + + This offset is used to adjust scratchpad addresses in instructions. + """ + return self._spad_size + + @spad_size.setter + def spad_size(self, value: int): + """ + @brief Sets the scratchpad offset. + + @param value: The new scratchpad offset to set. + """ + if not isinstance(value, int): + raise TypeError("Scratchpad offset must be an integer.") + self._spad_size = value + + @property + def directory(self) -> str: + """ + @brief Returns the directory where the kernel files are located. + """ + return self.file_paths["directory"] + + @property + def prefix(self) -> str: + """ + @brief Returns the prefix for the kernel files. + """ + return self.file_paths["prefix"] + + @property + def minst(self) -> str: + """ + @brief Returns the MInstruction file name. + """ + return self.file_paths["minst"] + + @property + def cinst(self) -> str: + """ + @brief Returns the CInstruction file name. + """ + return self.file_paths["cinst"] + + @property + def xinst(self) -> str: + """ + @brief Returns the XInstruction file name. + """ + return self.file_paths["xinst"] + + @property + def mem(self) -> str | None: + """ + @brief Returns the memory file name, if available. + + @return Optional[str]: The memory file name or None if not set. + """ + return self.file_paths.get("mem") + + @property + def minstrs(self) -> list[MInstruction]: + """ + @brief Returns the kernel minst instructions if loaded. + + @return Optional[dict]: The dict of kernel minst instructions or None if not loaded. + """ + return self._minstrs + + @minstrs.setter + def minstrs(self, value: list[MInstruction]): + """ + @brief Sets the kernel minst instructions. + + @param value: The dict of kernel minst instructions to set. + """ + self._minstrs = value + self._fill_minstrs_map() + + @property + def minstrs_map(self) -> list: + """ + @brief Returns the actions to be taken on minst instructions. + + @return list: The list of actions for minst instructions. + """ + return self._minstrs_map + + @minstrs_map.setter + def minstrs_map(self, value: list): + """ + @brief Sets the actions to be taken on minst instructions. + + @param value: The list of actions for minst instructions to set. + """ + if not isinstance(value, list): + raise TypeError("minstrs_map must be a list.") + self._minstrs_map = value + + @property + def cinstrs_map(self) -> list: + """ + @brief Returns the actions to be taken on cinst instructions. + + @return list: The list of actions for cinst instructions. + """ + return self._cinstrs_map + + @cinstrs_map.setter + def cinstrs_map(self, value: list): + """ + @brief Sets the actions to be taken on cinst instructions. + + @param value: The list of actions for cinst instructions to set. + """ + if not isinstance(value, list): + raise TypeError("cinstrs_map must be a list.") + self._cinstrs_map = value + + @property + def cinstrs(self) -> list[CInstruction]: + """ + @brief Returns the kernel cinst instructions if loaded. + + @return Optional[list]: The list of kernel cinst instructions or None if not loaded. + """ + return self._cinstrs + + @cinstrs.setter + def cinstrs(self, value: list[CInstruction]): + """ + @brief Sets the kernel cinst instructions. + + @param value: The list of kernel cinst instructions to set. + """ + if value is not None and not isinstance(value, list): + raise TypeError("cinstrs must be a list or None.") + self._cinstrs = value + self._fill_cinstrs_map() + + @property + def xinstrs(self) -> list[XInstruction]: + """ + @brief Returns the kernel xinst instructions if loaded. + + @return Optional[list]: The list of kernel xinst instructions or None if not loaded. + """ + return self._xinstrs + + @xinstrs.setter + def xinstrs(self, value: list[XInstruction]): + """ + @brief Sets the kernel xinst instructions. + + @param value: The list of kernel xinst instructions to set. + """ + if value is not None and not isinstance(value, list): + raise TypeError("xinstrs must be a list or None.") + self._xinstrs = value + + def _fill_minstrs_map(self): + """ + @brief Fills _minstrs_map with MinstrMapEntry for each instruction in _minstrs. + If instruction is MSyncc, spad_addr is set to -1. + """ + self._minstrs_map = [] + for minstr in self._minstrs: + if isinstance(minstr, minst.MSyncc): + spad_addr = -1 + else: + spad_addr = minstr.spad_address + entry = MinstrMapEntry(spad_addr, minstr, InstrAct.KEEP_HBM) + self._minstrs_map.append(entry) + + def _fill_cinstrs_map(self): + """ + @brief Fills _cinstrs_map with CinstrMapEntry for each instruction in _cinstrs. + If instruction is CSyncc, reg_name is set to ''. + """ + self._cinstrs_map = [] + for cinstr in self._cinstrs: + if isinstance(cinstr, (cinst.CLoad, cinst.BLoad, cinst.BOnes, cinst.NLoad)): + reg_name = cinstr.tokens[2] + else: + reg_name = "" + entry = CinstrMapEntry(reg_name, cinstr, InstrAct.KEEP_SPAD) + self._cinstrs_map.append(entry) diff --git a/assembler_tools/hec-assembler-tools/linker/kern_trace/trace_info.py b/assembler_tools/hec-assembler-tools/linker/kern_trace/trace_info.py index db150dbe..7c8298f4 100644 --- a/assembler_tools/hec-assembler-tools/linker/kern_trace/trace_info.py +++ b/assembler_tools/hec-assembler-tools/linker/kern_trace/trace_info.py @@ -14,54 +14,6 @@ from linker.kern_trace.kernel_op import KernelOp -class KernelInfo: - """ - @class KernelInfo - @brief Structure for kernel files. - - @details This class holds information about the kernel files used in the linker. - - @var directory - @var prefix - @var minst - @var cinst - @var xinst - @var mem - - @var remap_dict - @brief Dictionary for remapping variable names in DInstructions. - - """ - - directory: str - prefix: str - minst: str - cinst: str - xinst: str - mem: str | None = None - remap_dict: dict[str, str] = {} - - def __init__(self, config: dict): - """ - @brief Initializes KernelInfo with a configuration dictionary. - - @param config: Dictionary with keys 'directory', 'prefix', 'minst', 'cinst', 'xinst', and optional 'mem'. - """ - self.directory = config["directory"] - self.prefix = config["prefix"] - self.minst = config["minst"] - self.cinst = config["cinst"] - self.xinst = config["xinst"] - self.mem = config.get("mem") - - @property - def files(self) -> list[str]: - """ - @brief Returns a list of file names associated with the kernel. - """ - return [self.minst, self.cinst, self.xinst] + ([self.mem] if self.mem else []) - - class TraceInfo: """ @brief Class for handling trace files. diff --git a/assembler_tools/hec-assembler-tools/linker/linker_run_config.py b/assembler_tools/hec-assembler-tools/linker/linker_run_config.py index 6272fdb5..7e57ab56 100644 --- a/assembler_tools/hec-assembler-tools/linker/linker_run_config.py +++ b/assembler_tools/hec-assembler-tools/linker/linker_run_config.py @@ -82,6 +82,7 @@ def __init__(self, **kwargs): # class members based on configuration for config_name, default_value in self.__default_config.items(): value = kwargs.get(config_name, default_value) + print(f"Config: {config_name} = {value} default: {default_value}") if value is not None: setattr(self, config_name, value) else: @@ -114,6 +115,8 @@ def init_default_config(cls): cls.__default_config["output_dir"] = os.getcwd() cls.__default_config["input_dir"] = os.getcwd() cls.__default_config["output_prefix"] = None + cls.__default_config["keep_spad_boundary"] = False + cls.__default_config["keep_hbm_boundary"] = False cls.__initialized = True diff --git a/assembler_tools/hec-assembler-tools/linker/loader.py b/assembler_tools/hec-assembler-tools/linker/loader.py index 328c9999..51389ac6 100644 --- a/assembler_tools/hec-assembler-tools/linker/loader.py +++ b/assembler_tools/hec-assembler-tools/linker/loader.py @@ -40,7 +40,7 @@ def load_minst_kernel(cls, line_iter) -> list: @return A list of MInstruction objects. @throws RuntimeError If a line cannot be parsed into an MInstruction. """ - retval = [] + retval: list = [] for idx, s_line in enumerate(line_iter): minstr = instructions.create_from_str_line(s_line, minst.factory()) if not minstr: diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py index 29a0cf35..42cb3a31 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py @@ -11,11 +11,20 @@ from assembler.common.config import GlobalConfig from assembler.instructions import cinst as ISACInst +import linker.kern_trace.kern_remap as kern_mapper from linker import MemoryModel from linker.instructions import cinst, dinst, minst from linker.instructions.dinst.dinstruction import DInstruction -from linker.kern_trace.kern_remap import remap_m_c_instrs_vars +from linker.kern_trace import InstrAct, KernelInfo +from linker.kern_trace.kernel_info import CinstrMapEntry from linker.loader import Loader +from linker.steps.program_linker_utils import ( + calculate_instruction_latency_adjustment, + process_bload_instructions, + remove_csyncm, + search_minstrs_back, + search_minstrs_forward, +) class LinkedProgram: # pylint: disable=too-many-instance-attributes @@ -30,7 +39,30 @@ class LinkedProgram: # pylint: disable=too-many-instance-attributes The program itself is not contained in this object. """ - def __init__( + def __init__(self, keep_hbm_boundary: bool = False, keep_spad_boundary: bool = False): + """ + @brief Initializes a LinkedProgram object. + """ + # Variable trackers + self._minst_in_var_tracker: dict[str, int] = {} + self._cinst_in_var_tracker: dict[str, int] = {} + + self._intermediate_vars: list = [] + self._spad_offset = 0 + self._keep_hbm_boundary = keep_hbm_boundary + self._keep_spad_boundary = keep_spad_boundary + + self._minst_ostream = None + self._cinst_ostream = None + self._xinst_ostream = None + self.__mem_model: MemoryModel + self._bundle_offset = 0 + self._minst_line_offset = 0 + self._cinst_line_offset = 0 + self._kernel_count = 0 # Number of kernels linked into this program + self._is_open = False + + def initialize( self, program_minst_ostream, program_cinst_ostream, @@ -55,8 +87,28 @@ def __init__( self._bundle_offset = 0 self._minst_line_offset = 0 self._cinst_line_offset = 0 - self._kernel_count = 0 # Number of kernels linked into this program - self._is_open = True # Tracks whether this program is still accepting kernels to link + self._kernel_count = 0 + + # Tracks whether this program is still accepting kernels to link + self._is_open = True + + @property + def keep_hbm_boundary(self) -> bool: + """ + @brief Checks if the program is configured to keep HBM boundaries. + + @return bool True if HBM boundaries are kept, False otherwise. + """ + return self._keep_hbm_boundary + + @property + def keep_spad_boundary(self) -> bool: + """ + @brief Checks if the program is configured to keep SPAD boundaries. + + @return bool True if SPAD boundaries are kept, False otherwise. + """ + return self._keep_spad_boundary @property def is_open(self) -> bool: @@ -82,7 +134,7 @@ def close(self): tokens = [str(self._cinst_line_offset), cinst.CExit.name] cexit_cinstr = cinst.CExit(tokens) print( - f"{cexit_cinstr.tokens[0]}, {cexit_cinstr.to_line()}", + f"{cexit_cinstr.idx}, {cexit_cinstr.to_line()}", file=self._cinst_ostream, ) @@ -94,7 +146,7 @@ def close(self): ] cmsyncc_minstr = minst.MSyncc(tokens) print( - f"{cmsyncc_minstr.tokens[0]}, {cmsyncc_minstr.to_line()}", + f"{cmsyncc_minstr.idx}, {cmsyncc_minstr.to_line()}", end="", file=self._minst_ostream, ) @@ -114,6 +166,9 @@ def _validate_hbm_address(self, var_name: str, hbm_address: int): @exception RuntimeError If the HBM address is invalid or does not match the declared address. """ + if self.__mem_model is None: + raise RuntimeError("Memory model is not initialized.") + if hbm_address < 0: raise RuntimeError(f'Invalid negative HBM address for variable "{var_name}".') if var_name in self.__mem_model.mem_info_vars: @@ -136,6 +191,9 @@ def _validate_spad_address(self, var_name: str, spad_address: int): @exception RuntimeError If the SPAD address is invalid or does not match the declared address. """ + if self.__mem_model is None: + raise RuntimeError("Memory model is not initialized.") + # only available when no HBM assert not GlobalConfig.hasHBM @@ -154,7 +212,7 @@ def _validate_spad_address(self, var_name: str, spad_address: int): f" differs from allocated HBM address ({spad_address})." ) - def _update_minsts(self, kernel_minstrs: list): + def _update_minsts(self, kernel: KernelInfo): """ @brief Updates the MInsts in the kernel to offset to the current expected synchronization points, and convert variable placeholders/names into @@ -163,28 +221,52 @@ def _update_minsts(self, kernel_minstrs: list): All MInsts in the kernel are expected to synchronize with CInsts starting at line 0. Does not change the LinkedProgram object. - @param kernel_minstrs List of MInstructions to update. + @param kernel with minstrs Dict of MInstructions to update. """ - for minstr in kernel_minstrs: + if self.__mem_model is None: + raise RuntimeError("Memory model is not initialized.") + + idx: int = 0 + while idx < len(kernel.minstrs): + minstr = kernel.minstrs[idx] + + print(f"ROCHA ({idx}): processing minst {minstr.to_line()} token 0 {minstr.idx} id {minstr.id}") + # Update msyncc if isinstance(minstr, minst.MSyncc): - minstr.target = minstr.target + self._cinst_line_offset + if idx < len(kernel.minstrs) - 1: + # Update msyncc target to new cinst and global program offset + minstr.target = kernel.cinstrs_map[minstr.target].cinstr.idx + minstr.target = minstr.target + self._cinst_line_offset + # Change mload variable names into HBM addresses if isinstance(minstr, minst.MLoad): - var_name = minstr.source + var_name = minstr.var_name + + if kernel.minstrs_map[idx].action != InstrAct.SKIP: + minstr.spad_address += self._spad_offset + hbm_address = self.__mem_model.use_variable(var_name, self._kernel_count) self._validate_hbm_address(var_name, hbm_address) - minstr.source = str(hbm_address) + minstr.hbm_address = hbm_address minstr.comment = f" var: {var_name} - HBM({hbm_address})" + f";{minstr.comment}" if minstr.comment else "" + # Change mstore variable names into HBM addresses if isinstance(minstr, minst.MStore): - var_name = minstr.dest + var_name = minstr.var_name + + if kernel.minstrs_map[idx].action != InstrAct.SKIP: + minstr.spad_address += self._spad_offset + hbm_address = self.__mem_model.use_variable(var_name, self._kernel_count) self._validate_hbm_address(var_name, hbm_address) - minstr.dest = str(hbm_address) + minstr.hbm_address = hbm_address minstr.comment = f" var: {var_name} - HBM({hbm_address})" + f";{minstr.comment}" if minstr.comment else "" - def _remove_and_merge_csyncm_cnop(self, kernel_cinstrs: list): + print(f"ROCHA ({idx}) NEW minst {minstr.to_line()}") + idx += 1 # next instruction + + def _remove_and_merge_csyncm_cnop(self, kernel: KernelInfo): """ @brief Remove csyncm instructions and merge consecutive cnop instructions. @@ -193,9 +275,11 @@ def _remove_and_merge_csyncm_cnop(self, kernel_cinstrs: list): i = 0 current_bundle = 0 csyncm_count = 0 - while i < len(kernel_cinstrs): - cinstr = kernel_cinstrs[i] - cinstr.tokens[0] = str(i) # Update the line number + while i < len(kernel.cinstrs): + print(f"ROCHA ({i}): CINST -> {kernel.cinstrs[i].to_line()}") + + cinstr = kernel.cinstrs[i] + cinstr.idx = str(i) # Update the line number # ------------------------------ # This code block will remove csyncm instructions and keep track, @@ -219,21 +303,23 @@ def _remove_and_merge_csyncm_cnop(self, kernel_cinstrs: list): str(csyncm_count * ISACInst.CSyncm.get_throughput() - 1), ] ) - kernel_cinstrs.insert(i, cinstr_nop) + kernel.cinstrs.insert(i, cinstr_nop) + # Insert instruction also in cinstrs_map + kernel.cinstrs_map.insert(i, CinstrMapEntry("", cinstr_nop, InstrAct.KEEP_SPAD)) csyncm_count = 0 i += 1 if isinstance(cinstr, cinst.IFetch): current_bundle = cinstr.bundle + 1 # Update the line number - cinstr.tokens[0] = i + cinstr.idx = i if isinstance(cinstr, cinst.CSyncm): # Remove instruction - kernel_cinstrs.pop(i) + kernel.cinstrs_map[i].action = InstrAct.SKIP if current_bundle > 0: csyncm_count += 1 - else: - i += 1 + + i += 1 # ------------------------------ # This code block differs from previous in that csyncm instructions @@ -257,17 +343,17 @@ def _remove_and_merge_csyncm_cnop(self, kernel_cinstrs: list): # Merge continuous cnop i = 0 - while i < len(kernel_cinstrs): - cinstr = kernel_cinstrs[i] - cinstr.tokens[0] = str(i) + while i < len(kernel.cinstrs): + print(f"ROCHA ({i}): CINST -> {kernel.cinstrs[i].to_line()}") + cinstr = kernel.cinstrs[i] + cinstr.idx = str(i) if isinstance(cinstr, cinst.CNop): # Do look ahead - if i + 1 < len(kernel_cinstrs): - if isinstance(kernel_cinstrs[i + 1], cinst.CNop): + if i + 1 < len(kernel.cinstrs): + if isinstance(kernel.cinstrs[i + 1], cinst.CNop): # Add 1 because cnop n, waits for n+1 cycles - kernel_cinstrs[i + 1].cycles += cinstr.cycles + 1 - kernel_cinstrs.pop(i) - i -= 1 + kernel.cinstrs[i + 1].cycles += cinstr.cycles + 1 + kernel.cinstrs_map[i].action = InstrAct.SKIP i += 1 def _update_cinsts_addresses_and_offsets(self, kernel_cinstrs: list): @@ -280,6 +366,9 @@ def _update_cinsts_addresses_and_offsets(self, kernel_cinstrs: list): @param kernel_cinstrs List of CInstructions to update. """ + if self.__mem_model is None: + raise RuntimeError("Memory model is not initialized.") + for cinstr in kernel_cinstrs: # Update ifetch if isinstance(cinstr, cinst.IFetch): @@ -289,25 +378,82 @@ def _update_cinsts_addresses_and_offsets(self, kernel_cinstrs: list): raise NotImplementedError("`xinstfetch` not currently supported by linker.") # Update csyncm if isinstance(cinstr, cinst.CSyncm): - cinstr.target = cinstr.target + self._minst_line_offset + if cinstr.target > 4 or self._keep_hbm_boundary: + cinstr.target = cinstr.target + self._minst_line_offset if not GlobalConfig.hasHBM: - # update all SPAD instruction variable names to be SPAD addresses - # change xload variable names into SPAD addresses - if isinstance(cinstr, cinst.BLoad | cinst.BOnes | cinst.CLoad | cinst.NLoad): - var_name = cinstr.source - hbm_address = self.__mem_model.use_variable(var_name, self._kernel_count) - self._validate_spad_address(var_name, hbm_address) - cinstr.source = str(hbm_address) - cinstr.comment = f" var: {var_name} - HBM({hbm_address})" + f";{cinstr.comment}" if cinstr.comment else "" - if isinstance(cinstr, cinst.CStore): - var_name = cinstr.dest - hbm_address = self.__mem_model.use_variable(var_name, self._kernel_count) - self._validate_spad_address(var_name, hbm_address) - cinstr.dest = str(hbm_address) - cinstr.comment = f" var: {var_name} - HBM({hbm_address})" + f";{cinstr.comment}" if cinstr.comment else "" - - def _update_cinsts(self, kernel_cinstrs: list): + # Update all SPAD instruction variable names to be SPAD addresses + # Change xload variable names into SPAD addresses + if isinstance( + cinstr, + (cinst.BLoad, cinst.BOnes, cinst.CLoad, cinst.NLoad, cinst.CStore), + ): + hbm_address = self.__mem_model.use_variable(cinstr.var_name, self._kernel_count) + self._validate_spad_address(cinstr.var_name, hbm_address) + cinstr.spad_address = hbm_address + cinstr.comment = f" var: {cinstr.var_name} - HBM({hbm_address})" + f";{cinstr.comment}" if cinstr.comment else "" + + def _update_cinst_kernel_hbm(self, kernel: KernelInfo): + """ + @brief Updates CInsts for HBM mode, handling synchronization and address mapping. + + This method modifies the kernel's CInsts in place by updating synchronization points, + adjusting cycles, and remapping SPAD addresses. + + @param kernel (KernelInfo): The kernel to update. + """ + + idx: int = 0 + syncm_idx = 0 + while idx < len(kernel.cinstrs): + cinstr = kernel.cinstrs[idx] + print(f"ROCHA ({idx}): CINST -> {cinstr.to_line()} # {cinstr.comment}") + + if isinstance(cinstr, cinst.CSyncm): + syncm_idx = cinstr.target + # Update CSyncm target to the corresponding MInst + if kernel.cinstrs_map[idx].action != InstrAct.SKIP: + minstr = kernel.minstrs_map[syncm_idx].minstr + cinstr.target = minstr.idx + print(f"ROCHA ({idx}): CSyncm target {cinstr.target}") + + elif isinstance(cinstr, (cinst.CLoad, cinst.BLoad, cinst.BOnes)): + # Update CLoad/BLoad/BOnes SPAD addresses to new minst + if kernel.cinstrs_map[idx].action != InstrAct.SKIP: + print(f"ROCHA ({idx}): Updating CLoad/BLoad/BOnes syncm_idx {syncm_idx} source {cinstr.var_name}") + minstr_idx = search_minstrs_back(kernel.minstrs_map, syncm_idx, cinstr.spad_address) + minstr = kernel.minstrs_map[minstr_idx].minstr + cinstr.var_name = minstr.var_name + + if cinstr.var_name in self._cinst_in_var_tracker: + cinstr.spad_address = self._cinst_in_var_tracker[cinstr.var_name] + else: + cinstr.spad_address = minstr.spad_address + + elif isinstance(cinstr, cinst.NLoad): + # Update NLoad SPAD addresses to new minst + minstr_idx = search_minstrs_forward(kernel.minstrs_map, 0, cinstr.spad_address) + minstr = kernel.minstrs_map[minstr_idx].minstr + cinstr.var_name = minstr.var_name + + if cinstr.var_name in self._cinst_in_var_tracker: + cinstr.spad_address = self._cinst_in_var_tracker[cinstr.var_name] + else: + cinstr.spad_address = minstr.spad_address + + elif isinstance(cinstr, cinst.CStore): + # Update CStore SPAD addresses to new minst + if kernel.cinstrs_map[idx].action != InstrAct.SKIP: + minstr_idx = search_minstrs_forward(kernel.minstrs_map, syncm_idx, int(cinstr.spad_address)) + minstr = kernel.minstrs_map[minstr_idx].minstr + cinstr.var_name = minstr.var_name + cinstr.spad_address = minstr.spad_address + self._cinst_in_var_tracker[cinstr.var_name] = cinstr.spad_address + + print(f"ROCHA ({idx}): NEW CINST -> {cinstr.to_line()} # {cinstr.comment}") + idx += 1 # next instruction + + def _update_cinsts(self, kernel: KernelInfo): """ @brief Updates the CInsts in the kernel to offset to the current expected bundle and synchronization points. @@ -319,9 +465,11 @@ def _update_cinsts(self, kernel_cinstrs: list): @param kernel_cinstrs List of CInstructions to update. """ if not GlobalConfig.hasHBM: - self._remove_and_merge_csyncm_cnop(kernel_cinstrs) + self._remove_and_merge_csyncm_cnop(kernel) + else: + self._update_cinst_kernel_hbm(kernel) - self._update_cinsts_addresses_and_offsets(kernel_cinstrs) + self._update_cinsts_addresses_and_offsets(kernel.cinstrs) def _update_xinsts(self, kernel_xinstrs: list) -> int: """ @@ -342,7 +490,7 @@ def _update_xinsts(self, kernel_xinstrs: list) -> int: last_bundle = xinstr.bundle return last_bundle - def link_kernel(self, kernel_minstrs: list, kernel_cinstrs: list, kernel_xinstrs: list): + def link_kernel(self, kernel: KernelInfo): """ @brief Links a specified kernel (given by its three instruction queues) into this program. @@ -350,12 +498,7 @@ def link_kernel(self, kernel_minstrs: list, kernel_cinstrs: list, kernel_xinstrs The adjusted kernels will be appended into the output streams specified during construction of this object. - @param kernel_minstrs List of MInstructions for the MInst Queue corresponding to the kernel to link. - These instructions will be modified by this method. - @param kernel_cinstrs List of CInstructions for the CInst Queue corresponding to the kernel to link. - These instructions will be modified by this method. - @param kernel_xinstrs List of XInstructions for the XInst Queue corresponding to the kernel to link. - These instructions will be modified by this method. + @param kernel (KernelInfo): The kernel to link into this program. @exception RuntimeError If the program is closed and does not accept new kernels. """ @@ -364,53 +507,63 @@ def link_kernel(self, kernel_minstrs: list, kernel_cinstrs: list, kernel_xinstrs # No minsts without HBM if not GlobalConfig.hasHBM: - kernel_minstrs = [] + minstrs_list = [] + else: + # extract all instructions from minstrs marked as KEEP_HBM in minstrs_map + minstrs_list = [minstr_map.minstr for minstr_map in kernel.minstrs_map if minstr_map.action == InstrAct.KEEP_HBM] - self._update_minsts(kernel_minstrs) - self._update_cinsts(kernel_cinstrs) - self._bundle_offset = self._update_xinsts(kernel_xinstrs) + 1 + print(f"\nROCHA UPATADE MINST {kernel.minst} spad offset {self._spad_offset}\n") + self._update_minsts(kernel) + print(f"\nROCHA UPATADE CINST {kernel.cinst} spad offset {self._spad_offset}\n") + self._update_cinsts(kernel) + print(f"\nROCHA UPATADE xINST {kernel.xinst} spad offset {self._spad_offset}\n") + self._bundle_offset = self._update_xinsts(kernel.xinstrs) + 1 + self._spad_offset += (kernel.spad_size + 1) if not self._keep_hbm_boundary else 0 + + cinstrs_list = [cinstr_map.cinstr for cinstr_map in kernel.cinstrs_map if cinstr_map.action == InstrAct.KEEP_SPAD] # Append the kernel to the output - for xinstr in kernel_xinstrs: + for xinstr in kernel.xinstrs: print(xinstr.to_line(), end="", file=self._xinst_ostream) if not GlobalConfig.suppress_comments and xinstr.comment: print(f" #{xinstr.comment}", end="", file=self._xinst_ostream) print(file=self._xinst_ostream) - for idx, cinstr in enumerate(kernel_cinstrs[:-1]): # Skip the `cexit` + for idx, cinstr in enumerate(cinstrs_list[:-1]): # Skip the `cexit` line_no = idx + self._cinst_line_offset print(f"{line_no}, {cinstr.to_line()}", end="", file=self._cinst_ostream) if not GlobalConfig.suppress_comments and cinstr.comment: print(f" #{cinstr.comment}", end="", file=self._cinst_ostream) print(file=self._cinst_ostream) - for idx, minstr in enumerate(kernel_minstrs[:-1]): # Skip the exit `msyncc` + for idx, minstr in enumerate(minstrs_list[:-1]): # Skip the exit `msyncc` line_no = idx + self._minst_line_offset print(f"{line_no}, {minstr.to_line()}", end="", file=self._minst_ostream) if not GlobalConfig.suppress_comments and minstr.comment: print(f" #{minstr.comment}", end="", file=self._minst_ostream) print(file=self._minst_ostream) - self._minst_line_offset += len(kernel_minstrs) - 1 # Subtract last line that is getting removed - self._cinst_line_offset += len(kernel_cinstrs) - 1 # Subtract last line that is getting removed + self._minst_line_offset += len(minstrs_list) - 1 # Subtract last line that is getting removed + self._cinst_line_offset += len(cinstrs_list) - 1 # Subtract last line that is getting removed self._kernel_count += 1 # Count the appended kernel - @classmethod - def join_dinst_kernels(cls, kernels_instrs: list[list[DInstruction]]) -> list[DInstruction]: + def join_n_prune_dinst_kernels(self, kernels_dinstrs: list[list[DInstruction]]) -> list[DInstruction]: """ - @brief Joins a list of dinst kernels, consolidating variables that are outputs in one kernel - and inputs in the next. This ensures that variables carried across kernels are not duplicated, - and their Mem addresses are consistent. + @brief This method updates the class's intermediate (outputs of one kernel and inputs to the next) + variables and merges a list of dinst kernels. In addition, it identifies and removes instructions + that reference intermediate variables or perform redundant loads of the same variable. This ensures + that variables carried across kernels are not duplicated, memory addresses remain consistent, + and unnecessary operations are eliminated. - @param kernels_instrs List of Kernels' DInstructions lists. + @param kernels_dinstrs List of Kernels' DInstructions lists. @return list[DInstruction] A new instruction list representing the concatenated memory info. @exception ValueError If no DInstructions lists are provided for concatenation. """ - if not kernels_instrs: + if not kernels_dinstrs: raise ValueError("No DInstructions lists provided for concatenation.") # Use dictionaries to track unique variables by name @@ -418,9 +571,9 @@ def join_dinst_kernels(cls, kernels_instrs: list[list[DInstruction]]) -> list[DI carry_over_vars: dict[str, DInstruction] = {} mem_address: int = 0 - new_kernels_instrs: list[DInstruction] = [] - for kernel_instrs in kernels_instrs: - for cur_dinst in kernel_instrs: + new_kernels_dinstrs: list[DInstruction] = [] + for kernel_dinstrs in kernels_dinstrs: + for cur_dinst in kernel_dinstrs: # Save the current output instruction to add at the end if isinstance(cur_dinst, dinst.DStore): key = cur_dinst.var @@ -432,6 +585,7 @@ def join_dinst_kernels(cls, kernels_instrs: list[list[DInstruction]]) -> list[DI # Skip if the input is already in carry-over from previous outputs if key in carry_over_vars: carry_over_vars.pop(key) # Remove from (output) carry-overs since it's now an input + self._intermediate_vars.append(key) continue # If the input is not (a previous output) in carry-over, add if it's not already (loaded) in inputs @@ -440,23 +594,205 @@ def join_dinst_kernels(cls, kernels_instrs: list[list[DInstruction]]) -> list[DI cur_dinst.address = mem_address mem_address = mem_address + 1 - new_kernels_instrs.append(cur_dinst) + new_kernels_dinstrs.append(cur_dinst) continue # Add remaining carry-over variables to the new instructions for _, dintr in carry_over_vars.items(): dintr.address = mem_address - new_kernels_instrs.append(dintr) + new_kernels_dinstrs.append(dintr) mem_address = mem_address + 1 - return new_kernels_instrs + return new_kernels_dinstrs + + def prune_minst_kernel(self, kernel_info: KernelInfo): + """ + @brief Removes unnecessary MInsts from the kernel. + @param kernel_info KernelInfo object containing the kernel's MInsts. + This method modifies the kernel's MInsts in place by removing MLoad instructions that load + intermediate variables or already loaded variables, and MStore instructions that store + intermediate variables. It also tracks loaded variables in the `_minst_in_var_tracker` list. + """ + + if self._keep_hbm_boundary: + return + + # Initialize variables for tracking new indices and adjust_spad when instructions are removed + adjust_idx: int = 0 + adjust_spad: int = 0 + + spad_size: int = 0 + last_msyncc = None + + for idx, minstr in enumerate(kernel_info.minstrs): + if isinstance(minstr, minst.MSyncc): + last_msyncc = minstr + elif isinstance(minstr, minst.MStore): + # Remove mstore instructions that stores intermediate variables + if minstr.var_name in self._intermediate_vars: + # Remove the MSyncc if it is the immediately previous instruction + if last_msyncc and last_msyncc.idx == idx - 1: + kernel_info.minstrs_map[idx - 1].action = InstrAct.SKIP + adjust_idx -= 1 + + # Take variable into account for spad if we are keeping the spad boundary + if self._keep_spad_boundary: + kernel_info.minstrs_map[idx].action = InstrAct.KEEP_SPAD + minstr.spad_address += adjust_spad # Adjust source spad address + spad_size = minstr.spad_address + else: + kernel_info.minstrs_map[idx].action = InstrAct.SKIP + adjust_spad -= 1 + + adjust_idx -= 1 + # Keep instruction + else: + minstr.idx = minstr.idx + adjust_idx # Update line number + minstr.spad_address += adjust_spad # Adjust source spad address + spad_size = minstr.spad_address + elif isinstance(minstr, minst.MLoad): + # Remove mload instructions if variables already loaded + if minstr.var_name in self._minst_in_var_tracker: + kernel_info.minstrs_map[idx].action = InstrAct.SKIP + minstr.spad_address = self._minst_in_var_tracker[minstr.var_name] # Adjust dest spad address + adjust_spad -= 1 + adjust_idx -= 1 + continue + + # Remove mload instructions that load intermediate variables + if minstr.var_name in self._intermediate_vars: + kernel_info.minstrs_map[idx].action = InstrAct.KEEP_SPAD if self._keep_spad_boundary else InstrAct.SKIP + adjust_spad -= 1 + adjust_idx -= 1 + continue + + # Keep instruction + minstr.spad_address += adjust_spad # Adjust dest spad address + minstr.idx = minstr.idx + adjust_idx # Update line number + spad_size = minstr.spad_address + + # Track loaded variables + self._minst_in_var_tracker[minstr.var_name] = minstr.spad_address + + # Keep track of the spad size used by this kernel + kernel_info.spad_size = max(spad_size, kernel_info.spad_size) + + def prune_cinst_kernel_hbm(self, kernel: KernelInfo): + """ + @brief Prunes and updates CInsts for HBM mode, handling synchronization and address mapping. + """ + adjust_idx: int = 0 # Used to adjust the index when removing CInsts + adjust_cycles: int = 0 + + syncm_idx: int = 0 + idx: int = 0 + while idx < len(kernel.cinstrs): + cinstr = kernel.cinstrs[idx] + if isinstance(cinstr, cinst.IFetch): + adjust_cycles = 0 + elif isinstance(cinstr, cinst.CNop): + # Adjust CNop cycles based on removed instructions + cinstr.cycles += adjust_cycles + elif isinstance(cinstr, cinst.CSyncm): + # Keeping track of the minst + syncm_idx = cinstr.target + elif isinstance(cinstr, (cinst.CLoad, cinst.BLoad, cinst.BOnes)): + minstr_idx = search_minstrs_back(kernel.minstrs_map, syncm_idx, int(cinstr.spad_address)) + + cinstr.var_name = kernel.minstrs_map[minstr_idx].minstr.var_name + + # Remove CLoad/BLoad/BOnes instructions if minstr action is SKIP + if kernel.minstrs_map[minstr_idx].action == InstrAct.SKIP: + kernel.cinstrs_map[idx].action = InstrAct.SKIP + adjust_idx -= 1 + adjust_cycles += calculate_instruction_latency_adjustment(cinstr) + + # Remove any csyncm instructions before this load + _idx, _cycles = remove_csyncm(kernel.cinstrs, kernel.cinstrs_map, idx - 1) + adjust_idx += _idx + adjust_cycles += _cycles + + # Check if the variable is an intermediate variable + elif cinstr.var_name in self._intermediate_vars: + # Remove any csyncm instruction before this load + _idx, _cycles = remove_csyncm(kernel.cinstrs, kernel.cinstrs_map, idx - 1) + adjust_idx += _idx + adjust_cycles += _cycles + + elif isinstance(cinstr, cinst.CStore): + minstr_idx = search_minstrs_forward(kernel.minstrs_map, syncm_idx, int(cinstr.spad_address)) + + cinstr.var_name = kernel.minstrs_map[minstr_idx].minstr.var_name + + # Remove CStore instructions if minstr action is SKIP + if kernel.minstrs_map[minstr_idx].action == InstrAct.SKIP: + kernel.cinstrs_map[idx].action = InstrAct.SKIP + adjust_idx -= 1 + adjust_cycles += ISACInst.CStore.get_latency() + else: + cinstr.idx += adjust_idx # Update line number + + # Check if the variable is an intermediate variable + if cinstr.var_name in self._intermediate_vars: + # CSyncm no needed for intermediate variables + _idx, _cycles = remove_csyncm(kernel.cinstrs, kernel.cinstrs_map, idx + 1) + adjust_idx += _idx + adjust_cycles += _cycles + + idx += 1 # next instruction + + def prune_cinst_kernel_no_hbm(self, kernel: KernelInfo): + """ + @brief Prunes and updates CInsts for HBM mode, handling synchronization and address mapping. + """ + + if self._keep_hbm_boundary: + return + + adjust_cycles: int = 0 - @staticmethod - def link_kernels_to_files(input_files, output_files, mem_model, verbose_stream=None): + idx: int = 0 + while idx < len(kernel.cinstrs): + cinstr = kernel.cinstrs[idx] + # Update csyncm + if isinstance(cinstr, cinst.IFetch): + adjust_cycles = 0 + elif isinstance(cinstr, cinst.CNop): + cinstr.cycles += adjust_cycles + elif isinstance(cinstr, cinst.BLoad): + idx = process_bload_instructions(kernel.cinstrs, kernel.cinstrs_map, self._cinst_in_var_tracker, idx) + + if cinstr.var_name not in self._cinst_in_var_tracker: + self._cinst_in_var_tracker[cinstr.var_name] = 0 + + elif isinstance(cinstr, (cinst.CLoad, cinst.BOnes)): + # Remove CLoad/BLoad/BOnes instructions if variable already loaded + if cinstr.var_name in self._cinst_in_var_tracker: + kernel.cinstrs_map[idx].action = InstrAct.SKIP + adjust_cycles += calculate_instruction_latency_adjustment(cinstr) + # Check if the variable is an intermediate variable + elif cinstr.var_name in self._intermediate_vars and not self._keep_spad_boundary: + kernel.cinstrs_map[idx].action = InstrAct.SKIP + # Keep instruction + else: + self._cinst_in_var_tracker[cinstr.var_name] = cinstr.spad_address + + elif isinstance(cinstr, cinst.CStore) and cinstr.var_name in self._intermediate_vars and not self._keep_spad_boundary: + kernel.cinstrs_map[idx].action = InstrAct.SKIP + + idx += 1 # next instruction + + def link_kernels_to_files( + self, + kernels_info: list[KernelInfo], + output_files, + mem_model, + verbose_stream=None, + ): """ @brief Links input kernels and writes the output to the specified files. - @param input_files List of KernelInfo for input kernels. + @param kernels_info List of KernelInfo for input kernels. @param output_files KernelInfo for output. @param mem_model Memory model to use. @param verbose_stream Stream for verbose output. @@ -466,27 +802,36 @@ def link_kernels_to_files(input_files, output_files, mem_model, verbose_stream=N open(output_files.cinst, "w", encoding="utf-8") as fnum_output_cinst, open(output_files.xinst, "w", encoding="utf-8") as fnum_output_xinst, ): - result_program = LinkedProgram(fnum_output_minst, fnum_output_cinst, fnum_output_xinst, mem_model) + self.initialize(fnum_output_minst, fnum_output_cinst, fnum_output_xinst, mem_model) - for idx, kernel in enumerate(input_files): + for idx, kernel in enumerate(kernels_info): if verbose_stream: print( - f"[ {idx * 100 // len(input_files): >3}% ]", + f"[ {idx * 100 // len(kernels_info): >3}% ]", kernel.prefix, file=verbose_stream, ) - kernel_minstrs = Loader.load_minst_kernel_from_file(kernel.minst) - kernel_cinstrs = Loader.load_cinst_kernel_from_file(kernel.cinst) - kernel_xinstrs = Loader.load_xinst_kernel_from_file(kernel.xinst) - remap_m_c_instrs_vars(kernel_minstrs, kernel.remap_dict) - remap_m_c_instrs_vars(kernel_cinstrs, kernel.remap_dict) + if GlobalConfig.hasHBM: + kernel.cinstrs = Loader.load_cinst_kernel_from_file(kernel.cinst) + kern_mapper.remap_m_c_instrs_vars(kernel.cinstrs, kernel.hbm_remap_dict) + self.prune_cinst_kernel_hbm(kernel) + + kernel.xinstrs = Loader.load_xinst_kernel_from_file(kernel.xinst) + + self.link_kernel(kernel) - result_program.link_kernel(kernel_minstrs, kernel_cinstrs, kernel_xinstrs) if verbose_stream: - print( - "[ 100% ] Finalizing output", - output_files.prefix, - file=verbose_stream, - ) - result_program.close() + print("[ 100% ] Finalizing output", output_files.prefix, file=verbose_stream) + + self.close() + + def flush_buffers(self): + """ + @brief Flushes the CInst input variable tracker. + + This method clears the list of input variables used in CInsts. + """ + self._cinst_in_var_tracker.clear() + self._minst_in_var_tracker.clear() + self._spad_offset = 0 diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py new file mode 100644 index 00000000..cffd708b --- /dev/null +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py @@ -0,0 +1,117 @@ +# Copyright (C) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +# These contents may have been developed with support from one or more Intel-operated +# generative artificial intelligence solutions + +"""@brief This module provides functionality to link kernels into a program.""" + +from assembler.instructions import cinst as ISACInst + +from linker.instructions import cinst, minst +from linker.kern_trace.kernel_info import InstrAct + + +def calculate_instruction_latency_adjustment(cinstr) -> int: + """ + @brief Calculate the latency adjustment for different instruction types. + + @param cinstr The instruction to calculate latency for. + @return int The latency adjustment value. + """ + if isinstance(cinstr, cinst.CLoad): + return ISACInst.CLoad.get_latency() + if isinstance(cinstr, cinst.BLoad): + return ISACInst.BLoad.get_latency() + if isinstance(cinstr, cinst.BOnes): + return ISACInst.BOnes.get_latency() + return 0 + + +def process_bload_instructions(kernel_cinstrs, kernel_cinstrs_map, cinst_in_var_tracker, start_idx): + """ + @brief Process consecutive BLoad instructions and mark duplicates for skipping. + + @param kernel_cinstrs List of CInstructions. + @param kernel_cinstrs_map Map of CInstructions with actions. + @param cinst_in_var_tracker Dictionary tracking loaded variables. + @param start_idx Starting index for processing. + @return int The last processed index. + """ + idx = start_idx + + # Look ahead and process all consecutive BLoad instructions + while idx < len(kernel_cinstrs) and isinstance(kernel_cinstrs[idx], cinst.BLoad): + if kernel_cinstrs[idx].var_name in cinst_in_var_tracker: + kernel_cinstrs_map[idx].action = InstrAct.SKIP + idx += 1 + + # Adjust index since the calling loop will increment it again + return idx - 1 + + +def remove_csyncm(kernel_cinstrs, kernel_cinstrs_map, idx): + """ + @brief Remove CSyncm instruction for intermediate variables. + + @param kernel_cinstrs List of CInstructions. + @param kernel_cinstrs_map Map of CInstructions with actions. + @param direction Direction to look for CSyncm ("next" or "prev"). + @return tuple (adjust_idx, adjust_cycles) Adjustments for index and cycles. + """ + adjust_idx = 0 + adjust_cycles = 0 + + # Check if target instruction exists and is CSyncm + if 0 <= idx < len(kernel_cinstrs): + target_cinstr = kernel_cinstrs[idx] + if isinstance(target_cinstr, cinst.CSyncm): + kernel_cinstrs_map[idx].action = InstrAct.SKIP + adjust_cycles = ISACInst.CSyncm.get_throughput() + adjust_idx = -1 + + return adjust_idx, adjust_cycles + + +def search_minstrs_back(minstrs_map: list, idx: int, spad_address: int) -> int: + """ + @brief Searches for an MLoad based on its SPAD address. + + This method is used to find the instruction associated with a given SPAD address + in the MInsts of a kernel. + + @param minstrs_map Map with MInstructions to search. + @param idx Index to start searching from (inclusive, backwards). + @param spad_address The SPAD address to search for. + + @return int Index for the MLoad instruction associated with the SPAD address. + """ + # Traverse backwards from idx, including idx + for i in range(idx, -1, -1): + minstr = minstrs_map[i].minstr + if isinstance(minstr, minst.MLoad) and minstrs_map[i].spad_addr == spad_address: + return i + + raise RuntimeError(f"Could not find MLoad with SPAD address {spad_address} in kernel MInsts.") + + +def search_minstrs_forward(minstrs_map: list, idx: int, spad_address: int) -> int: + """ + @brief Searches for an MStore based on its SPAD address + + This method is used to find the instruction associated with a given SPAD address + in the MInsts of a kernel. + + @param minstrs_map Map with MInstructions to search. + @param idx Index to start searching from (inclusive, forwards). + @param spad_address The SPAD address to search for. + + @return int Index for the MInstruction associated with the SPAD address. + """ + # Traverse forwards from idx, including idx + for i in range(idx, len(minstrs_map)): + minstr = minstrs_map[i].minstr + if isinstance(minstr, (minst.MStore, minst.MLoad)) and minstrs_map[i].spad_addr == spad_address: + return i + + raise RuntimeError(f"Could not find MStore with SPAD address {spad_address} in kernel MInsts.") diff --git a/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py b/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py index 922846f7..ae4c4e0d 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py @@ -16,6 +16,7 @@ from linker.instructions.minst.minstruction import MInstruction from linker.kern_trace import KernelInfo, remap_m_c_instrs_vars from linker.loader import Loader +from linker.steps.program_linker import LinkedProgram def discover_variables_spad(cinstrs: list): @@ -35,10 +36,8 @@ def discover_variables_spad(cinstrs: list): # TODO: Implement variable counting for CInst ############### # Raise NotImplementedError("Implement variable counting for CInst") - if isinstance(cinstr, (cinst.BLoad, cinst.CLoad, cinst.BOnes, cinst.NLoad)): - retval = cinstr.source - elif isinstance(cinstr, cinst.CStore): - retval = cinstr.dest + if isinstance(cinstr, (cinst.BLoad, cinst.CLoad, cinst.BOnes, cinst.NLoad, cinst.CStore)): + retval = cinstr.var_name if retval is not None: if not Variable.validateName(retval): @@ -60,10 +59,8 @@ def discover_variables(minstrs: list): if not isinstance(minstr, MInstruction): raise TypeError(f"Item {idx} in list of MInstructions is not a valid MInstruction.") retval = None - if isinstance(minstr, minst.MLoad): - retval = minstr.source - elif isinstance(minstr, minst.MStore): - retval = minstr.dest + if isinstance(minstr, (minst.MLoad, minst.MStore)): + retval = minstr.var_name if retval is not None: if not Variable.validateName(retval): @@ -72,6 +69,7 @@ def discover_variables(minstrs: list): def scan_variables( + p_linker: LinkedProgram, kernels_info: list[KernelInfo], mem_model: MemoryModel, verbose_stream: TextIO | None = None, @@ -83,6 +81,7 @@ def scan_variables( @param mem_model Memory model to update. @param verbose_stream Stream for verbose output. """ + for idx, kernel_info in enumerate(kernels_info): if not GlobalConfig.hasHBM: if verbose_stream: @@ -91,10 +90,15 @@ def scan_variables( kernel_info.cinst, file=verbose_stream, ) - kernel_cinstrs = Loader.load_cinst_kernel_from_file(kernel_info.cinst) - remap_m_c_instrs_vars(kernel_cinstrs, kernel_info.remap_dict) - for var_name in discover_variables_spad(kernel_cinstrs): + + kernel_info.cinstrs = Loader.load_cinst_kernel_from_file(kernel_info.cinst) + remap_m_c_instrs_vars(kernel_info.cinstrs, kernel_info.hbm_remap_dict) + print(f"\nROCHA Pruning Cinst {kernel_info.cinst}\n") + p_linker.prune_cinst_kernel_no_hbm(kernel_info) + + for var_name in discover_variables_spad(kernel_info.cinstrs): mem_model.add_variable(var_name) + else: if verbose_stream: print( @@ -102,11 +106,18 @@ def scan_variables( kernel_info.minst, file=verbose_stream, ) - kernel_minstrs = Loader.load_minst_kernel_from_file(kernel_info.minst) - remap_m_c_instrs_vars(kernel_minstrs, kernel_info.remap_dict) - for var_name in discover_variables(kernel_minstrs): + kernel_info.minstrs = Loader.load_minst_kernel_from_file(kernel_info.minst) + remap_m_c_instrs_vars(kernel_info.minstrs, kernel_info.hbm_remap_dict) + + print(f"\nROCHA Pruning Minst {kernel_info.minst}\n") + p_linker.prune_minst_kernel(kernel_info) + + for var_name in discover_variables(kernel_info.minstrs): mem_model.add_variable(var_name) + # Clean p_linker var trackers + p_linker.flush_buffers() + def check_unused_variables(mem_model): """ diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py index 169480d1..6d7528a7 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py @@ -36,6 +36,8 @@ def test_main(self, using_trace_file): mock_config.hbm_size = 1024 mock_config.suppress_comments = False mock_config.use_xinstfetch = False + mock_config.keep_spad_boundary = not using_trace_file + mock_config.keep_hbm_boundary = not using_trace_file # The expected kernel name pattern from parse_kernel_ops expected_kernel_name = "kernel1_pisa.tw" @@ -54,6 +56,13 @@ def test_main(self, using_trace_file): ), ] + # Setup output files with proper file paths + mock_output_files = MagicMock() + mock_output_files.minst = "/tmp/output.minst" + mock_output_files.cinst = "/tmp/output.cinst" + mock_output_files.xinst = "/tmp/output.xinst" + mock_output_files.mem = "/tmp/output.mem" if using_trace_file else None + # Create mock DInstructions with proper .var attributes mock_dinstr1 = MagicMock() mock_dinstr1.var = "ct0_data" @@ -62,7 +71,7 @@ def test_main(self, using_trace_file): # Create a dictionary of mocks to reduce the number of local variables mocks = { - "prepare_output": MagicMock(), + "prepare_output": MagicMock(return_value=mock_output_files), "prepare_input": MagicMock(return_value=input_files), "scan_variables": MagicMock(), "check_unused_variables": MagicMock(), @@ -88,6 +97,8 @@ def test_main(self, using_trace_file): ) ] ), + "linked_program": MagicMock(), + "mock_open": mock_open(), # Add a mock_open to handle file operations } # Add trace_file property to mock_config @@ -104,10 +115,8 @@ def test_main(self, using_trace_file): "linker.instructions.BaseInstruction.dump_instructions_to_file", mocks["dump_instructions"], ), - patch( - "linker.steps.program_linker.LinkedProgram.join_dinst_kernels", - mocks["join_dinst"], - ), + patch("he_link.LinkedProgram", return_value=mocks["linked_program"]), + patch.object(mocks["linked_program"], "join_n_prune_dinst_kernels", mocks["join_dinst"]), patch( "assembler.memory_model.mem_info.MemInfo.from_dinstrs", mocks["from_dinstrs"], @@ -119,20 +128,28 @@ def test_main(self, using_trace_file): patch("linker.MemoryModel"), patch("he_link.scan_variables", mocks["scan_variables"]), patch("he_link.check_unused_variables", mocks["check_unused_variables"]), - patch("linker.kern_trace.TraceInfo.parse_kernel_ops", mocks["parse_kernel_ops"]), patch( - "os.path.isfile", - return_value=True, # Make all file existence checks return True + "linker.kern_trace.TraceInfo.parse_kernel_ops_from_file", + mocks["parse_kernel_ops"], ), patch( - "linker.steps.program_linker.LinkedProgram.link_kernels_to_files", - mocks["link_kernels"], + "os.path.isfile", + return_value=True, # Make all file existence checks return True ), patch("linker.kern_trace.remap_dinstrs_vars", mocks["remap_dinstrs_vars"]), patch("he_link.update_input_prefixes", mocks["update_input_prefixes"]), patch("he_link.remap_vars", mocks["remap_vars"]), patch("he_link.initialize_memory_model", mocks["initialize_memory_model"]), + patch("he_link.Loader.flush_cache"), + patch( + "builtins.open", + mocks["mock_open"], # Mock all file opens to prevent actual file operations + ), ): + # Mock link_kernels_to_files directly instead of patching the method + # This avoids the internal file operations while still tracking the call + mocks["linked_program"].link_kernels_to_files = mocks["link_kernels"] + # Run the main function with all patches in place he_link.main(mock_config, MagicMock()) @@ -145,12 +162,14 @@ def test_main(self, using_trace_file): if using_trace_file: # Assert that the trace processing flow was used + mocks["parse_kernel_ops"].assert_called_once_with(mock_config.trace_file) mocks["update_input_prefixes"].assert_called_once() mocks["remap_vars"].assert_called_once() mocks["initialize_memory_model"].assert_called_once() assert not mocks["from_file_iter"].called else: # Assert that the normal flow was used + assert not mocks["parse_kernel_ops"].called assert not mocks["update_input_prefixes"].called assert not mocks["remap_vars"].called mocks["initialize_memory_model"].assert_called_once() @@ -167,21 +186,44 @@ def test_warning_on_use_xinstfetch(self): mock_config.suppress_comments = False mock_config.use_xinstfetch = True # Should trigger warning mock_config.input_mem_file = "input.mem" + mock_config.keep_spad_boundary = True + mock_config.keep_hbm_boundary = True + + # Create mock objects for file paths + mock_output_files = MagicMock() + mock_output_files.minst = "/tmp/output.minst" + mock_output_files.cinst = "/tmp/output.cinst" + mock_output_files.xinst = "/tmp/output.xinst" + + # Create a LinkedProgram mock + mock_linked_program = MagicMock() + mock_link_kernels = MagicMock() + + # Create file operation mock + mock_file_open = mock_open() # Act & Assert with ( patch("warnings.warn") as mock_warn, patch("assembler.common.constants.convertBytes2Words", return_value=1024), - patch("linker.he_link_utils.prepare_output_files"), - patch("linker.he_link_utils.prepare_input_files"), + patch("he_link.prepare_output_files", return_value=mock_output_files), + patch("he_link.prepare_input_files", return_value=[]), patch("assembler.common.counter.Counter.reset"), - patch("builtins.open", mock_open()), + patch( + "linker.steps.program_linker.LinkedProgram", + return_value=mock_linked_program, + ), patch("assembler.memory_model.mem_info.MemInfo.from_file_iter"), patch("linker.MemoryModel"), - patch("linker.steps.variable_discovery.scan_variables"), - patch("linker.steps.variable_discovery.check_unused_variables"), - patch("linker.steps.program_linker.LinkedProgram.link_kernels_to_files"), + patch("he_link.scan_variables"), + patch("he_link.check_unused_variables"), + patch("he_link.initialize_memory_model"), + patch("he_link.Loader.flush_cache"), + patch("builtins.open", mock_file_open), # Mock all file operations ): + # Set link_kernels_to_files method directly to avoid internal file operations + mock_linked_program.link_kernels_to_files = mock_link_kernels + he_link.main(mock_config, None) mock_warn.assert_called_once() @@ -213,6 +255,8 @@ def test_parse_args_minimal(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -222,6 +266,7 @@ def test_parse_args_minimal(self): assert args.output_prefix == "output_prefix" assert args.input_mem_file == "input.mem" assert args.using_trace_file is False + assert args.keep_spad_boundary is True def test_parse_args_using_trace_file(self): """ @@ -244,6 +289,8 @@ def test_parse_args_using_trace_file(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -252,6 +299,7 @@ def test_parse_args_using_trace_file(self): assert args.output_prefix == "output_prefix" assert args.trace_file == "trace_file_path" assert args.using_trace_file is True # Should be computed from trace_file + assert args.keep_spad_boundary is False # Should be False when using trace file def test_trace_file_with_missing_output_prefix(self): """ @@ -299,6 +347,8 @@ def test_required_args_when_trace_file_not_set(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ), patch("argparse.ArgumentParser.error") as mock_error, @@ -327,6 +377,8 @@ def test_required_args_when_trace_file_not_set(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ), patch("argparse.ArgumentParser.error") as mock_error, @@ -359,6 +411,8 @@ def test_ignored_args_when_trace_file_set(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ), patch("warnings.warn") as mock_warn, @@ -396,6 +450,8 @@ def test_hbm_flags_parsing(self): hbm_size=2048, # Valid hbm_size suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -419,6 +475,8 @@ def test_hbm_flags_parsing(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -441,6 +499,8 @@ def test_hbm_flags_parsing(self): hbm_size=0, # Edge case: zero suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -467,6 +527,8 @@ def test_verbose_flag_parsing(self): hbm_size=None, suppress_comments=False, verbose=0, # Default level + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -489,6 +551,8 @@ def test_verbose_flag_parsing(self): hbm_size=None, suppress_comments=False, verbose=1, # Single -v + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -511,6 +575,8 @@ def test_verbose_flag_parsing(self): hbm_size=None, suppress_comments=False, verbose=2, # Double -vv + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -533,6 +599,8 @@ def test_verbose_flag_parsing(self): hbm_size=None, suppress_comments=False, verbose=5, # High verbosity + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ): args = he_link.parse_args() @@ -560,6 +628,8 @@ def test_input_dir_defaults_to_trace_file_directory(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ), patch("os.path.dirname", return_value="/path/to") as mock_dirname, @@ -588,6 +658,8 @@ def test_input_dir_defaults_to_trace_file_directory(self): hbm_size=None, suppress_comments=False, verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=False, ), ), patch("os.path.dirname") as mock_dirname, @@ -598,3 +670,82 @@ def test_input_dir_defaults_to_trace_file_directory(self): mock_dirname.assert_not_called() # Input_dir should remain as specified assert args.input_dir == "/custom/path" + + def test_boundary_flags_parsing(self): + """ + @brief Test the parsing of --keep_spad_boundary and --keep_hbm_boundary flags + """ + # Test with keep_spad_boundary flag set (trace file mode) + with patch( + "argparse.ArgumentParser.parse_args", + return_value=argparse.Namespace( + input_prefixes=None, + output_prefix="output_prefix", + input_mem_file="", + trace_file="trace_file_path", + input_dir="", + output_dir="", + using_trace_file=None, + mem_spec_file="", + isa_spec_file="", + has_hbm=True, + hbm_size=None, + suppress_comments=False, + verbose=0, + keep_spad_boundary=True, + keep_hbm_boundary=False, + ), + ): + args = he_link.parse_args() + assert args.keep_spad_boundary is True + assert args.keep_hbm_boundary is False + + # Test with keep_hbm_boundary flag set (should override keep_spad_boundary) + with patch( + "argparse.ArgumentParser.parse_args", + return_value=argparse.Namespace( + input_prefixes=None, + output_prefix="output_prefix", + input_mem_file="", + trace_file="trace_file_path", + input_dir="", + output_dir="", + using_trace_file=None, + mem_spec_file="", + isa_spec_file="", + has_hbm=True, + hbm_size=None, + suppress_comments=False, + verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=True, + ), + ): + args = he_link.parse_args() + assert args.keep_spad_boundary is True # Should be set to True due to HBM boundary override + assert args.keep_hbm_boundary is True + + # Test default behavior when not using trace file (both should be True) + with patch( + "argparse.ArgumentParser.parse_args", + return_value=argparse.Namespace( + input_prefixes=["input_prefix"], + output_prefix="output_prefix", + input_mem_file="input.mem", + trace_file="", + input_dir="", + output_dir="", + using_trace_file=False, + mem_spec_file="", + isa_spec_file="", + has_hbm=True, + hbm_size=None, + suppress_comments=False, + verbose=0, + keep_spad_boundary=False, + keep_hbm_boundary=True, + ), + ): + args = he_link.parse_args() + assert args.keep_spad_boundary is True # Should be forced to True when not using trace file + assert args.keep_hbm_boundary is True # Should be forced to True when not using trace file diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_he_link_utils.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_he_link_utils.py index 4d0c5b45..e6ff3d54 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_he_link_utils.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_he_link_utils.py @@ -20,7 +20,7 @@ remap_vars, update_input_prefixes, ) -from linker.kern_trace.trace_info import KernelInfo +from linker.kern_trace.kernel_info import KernelInfo class TestHelperFunctions: @@ -102,7 +102,10 @@ def test_prepare_input_files(self): ) # Act - with patch("os.path.isfile", return_value=True), patch("assembler.common.makeUniquePath", side_effect=lambda x: x): + with ( + patch("os.path.isfile", return_value=True), + patch("assembler.common.makeUniquePath", side_effect=lambda x: x), + ): result = prepare_input_files(mock_config, mock_output_files) # Assert @@ -137,7 +140,10 @@ def test_prepare_input_files_file_not_found(self): ) # Act & Assert - with patch("os.path.isfile", return_value=False), patch("assembler.common.makeUniquePath", side_effect=lambda x: x): + with ( + patch("os.path.isfile", return_value=False), + patch("assembler.common.makeUniquePath", side_effect=lambda x: x), + ): with pytest.raises(FileNotFoundError): prepare_input_files(mock_config, mock_output_files) @@ -164,7 +170,10 @@ def test_prepare_input_files_output_conflict(self): ) # Act & Assert - with patch("os.path.isfile", return_value=True), patch("assembler.common.makeUniquePath", side_effect=lambda x: x): + with ( + patch("os.path.isfile", return_value=True), + patch("assembler.common.makeUniquePath", side_effect=lambda x: x), + ): with pytest.raises(RuntimeError): prepare_input_files(mock_config, output_files) @@ -300,9 +309,9 @@ def test_remap_vars_with_multiple_kernels(self): # Second call mock_remap_vars.assert_any_call(test_data["kernel_dinstrs"][1], test_data["kernel_ops"][1]) - # Verify the remap_dict was set on each kernel file - assert test_data["files"][0].remap_dict == test_data["expected_dicts"] - assert test_data["files"][1].remap_dict == test_data["expected_dicts"] + # Verify the hbm_remap_dict was set on each kernel file + assert test_data["files"][0].hbm_remap_dict == test_data["expected_dicts"] + assert test_data["files"][1].hbm_remap_dict == test_data["expected_dicts"] def test_remap_vars_with_mismatched_prefixes(self): """ @@ -379,7 +388,10 @@ def test_initialize_memory_model_with_kernel_dinstrs(self): # Act with ( - patch("assembler.common.constants.convertBytes2Words", return_value=1024 * 1024) as mock_convert, + patch( + "assembler.common.constants.convertBytes2Words", + return_value=1024 * 1024, + ) as mock_convert, patch( "assembler.memory_model.mem_info.MemInfo.from_dinstrs", return_value=mock_mem_info, @@ -424,7 +436,10 @@ def test_initialize_memory_model_with_input_mem_file(self): # Act with ( - patch("assembler.common.constants.convertBytes2Words", return_value=2048 * 1024) as mock_convert, + patch( + "assembler.common.constants.convertBytes2Words", + return_value=2048 * 1024, + ) as mock_convert, patch("builtins.open", mock_open()) as mock_open_file, patch( "assembler.memory_model.mem_info.MemInfo.from_file_iter", diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kern_remap.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kern_remap.py index 8f93fce9..43978938 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kern_remap.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kern_remap.py @@ -12,7 +12,7 @@ from unittest.mock import MagicMock import pytest -from linker.instructions.cinst import BLoad, BOnes, CLoad, CStore, NLoad +from linker.instructions.cinst import CLoad, CStore from linker.instructions.minst import MLoad, MStore from linker.kern_trace.kern_remap import remap_dinstrs_vars, remap_m_c_instrs_vars from linker.kern_trace.kern_var import KernVar @@ -213,17 +213,17 @@ def test_remap_m_load_instructions(self): """ # Arrange mock_instr = MagicMock(spec=MLoad) - mock_instr.source = "old_source" + mock_instr.var_name = "old_source" mock_instr.comment = "" kernel_instrs = [mock_instr] - remap_dict = self._create_remap_dict() + hbm_remap_dict = self._create_remap_dict() # Act - remap_m_c_instrs_vars(kernel_instrs, remap_dict) + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) # Assert - assert mock_instr.source == "new_source" + assert mock_instr.var_name == "new_source" def test_remap_m_store_instructions(self): """ @@ -231,40 +231,37 @@ def test_remap_m_store_instructions(self): """ # Arrange mock_instr = MagicMock(spec=MStore) - mock_instr.dest = "old_dest" + mock_instr.var_name = "old_dest" mock_instr.comment = "Store old_dest" kernel_instrs = [mock_instr] - remap_dict = self._create_remap_dict() + hbm_remap_dict = self._create_remap_dict() # Act - remap_m_c_instrs_vars(kernel_instrs, remap_dict) + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) # Assert - assert mock_instr.dest == "new_dest" + assert mock_instr.var_name == "new_dest" + assert mock_instr.comment == "Store new_dest" def test_remap_c_load_instructions(self): """ @brief Test remapping variables in CLoad, BLoad, BOnes, and NLoad instructions """ # Arrange - c_instrs = [] + mock_instr = MagicMock(spec=CLoad) + mock_instr.var_name = "old_source" + mock_instr.comment = "old_source" - # Create mock instructions of each type - for instr_class in [CLoad, BLoad, BOnes, NLoad]: - mock_instr = MagicMock(spec=instr_class) - mock_instr.source = "old_source" - mock_instr.comment = "" - c_instrs.append(mock_instr) - - remap_dict = self._create_remap_dict() + kernel_instrs = [mock_instr] + hbm_remap_dict = self._create_remap_dict() # Act - remap_m_c_instrs_vars(c_instrs, remap_dict) + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) # Assert - for instr in c_instrs: - assert instr.source == "new_source" + assert mock_instr.var_name == "new_source" + assert mock_instr.comment == "new_source" def test_remap_c_store_instructions(self): """ @@ -272,17 +269,17 @@ def test_remap_c_store_instructions(self): """ # Arrange mock_instr = MagicMock(spec=CStore) - mock_instr.dest = "old_dest" + mock_instr.var_name = "old_dest" mock_instr.comment = "Store old_dest" kernel_instrs = [mock_instr] - remap_dict = self._create_remap_dict() + hbm_remap_dict = self._create_remap_dict() # Act - remap_m_c_instrs_vars(kernel_instrs, remap_dict) + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) # Assert - assert mock_instr.dest == "new_dest" + assert mock_instr.var_name == "new_dest" def test_skip_unmapped_variables(self): """ @@ -290,20 +287,22 @@ def test_skip_unmapped_variables(self): """ # Arrange mock_load = MagicMock(spec=MLoad) - mock_load.source = "unmapped_source" + mock_load.var_name = "unmapped_source" + mock_load.comment = "Load unmapped_source" mock_store = MagicMock(spec=MStore) - mock_store.dest = "unmapped_dest" + mock_store.var_name = "unmapped_dest" + mock_store.comment = "" kernel_instrs = [mock_load, mock_store] - remap_dict = self._create_remap_dict() + hbm_remap_dict = self._create_remap_dict() # Act - remap_m_c_instrs_vars(kernel_instrs, remap_dict) + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) # Assert - assert mock_load.source == "unmapped_source" # Unchanged - assert mock_store.dest == "unmapped_dest" # Unchanged + assert mock_load.var_name == "unmapped_source" # Unchanged + assert mock_store.var_name == "unmapped_dest" # Unchanged def test_empty_remap_dict(self): """ @@ -311,16 +310,16 @@ def test_empty_remap_dict(self): """ # Arrange mock_instr = MagicMock(spec=MLoad) - mock_instr.source = "source" + mock_instr.var_name = "source" kernel_instrs = [mock_instr] - remap_dict = {} # Empty dict + hbm_remap_dict = {} # Empty dict # Act - remap_m_c_instrs_vars(kernel_instrs, remap_dict) + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) # Assert - assert mock_instr.source == "source" # Unchanged + assert mock_instr.var_name == "source" # Unchanged def test_invalid_instruction_type(self): """ @@ -330,8 +329,27 @@ def test_invalid_instruction_type(self): mock_instr = MagicMock() # Not a proper instruction type kernel_instrs = [mock_instr] - remap_dict = self._create_remap_dict() + hbm_remap_dict = self._create_remap_dict() # Act & Assert with pytest.raises(TypeError, match="not a valid M or C Instruction"): - remap_m_c_instrs_vars(kernel_instrs, remap_dict) + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) + + def test_invalid_var_name(self): + """ + @brief Test comment gets updated even if var_name is not a valid M or C instruction + """ + # Arrange + mock_instr = MagicMock(spec=CLoad) + mock_instr.var_name = "0" # Not a var_name + mock_instr.comment = "Store old_dest" + + kernel_instrs = [mock_instr] + hbm_remap_dict = self._create_remap_dict() + + # Act + remap_m_c_instrs_vars(kernel_instrs, hbm_remap_dict) + + # Assert + assert mock_instr.var_name == "0" # Unchanged + assert mock_instr.comment == "Store new_dest" diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py new file mode 100644 index 00000000..2a237d33 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py @@ -0,0 +1,66 @@ +# Copyright (C) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +# These contents may have been developed with support from one +# or more Intel-operated generative artificial intelligence solutions + +""" +@file test_kernel_info.py +@brief Unit tests for the KernelInfo class +""" + +from linker.kern_trace.kernel_info import KernelInfo + + +class TestKernelInfo: + """ + @class TestKernelInfo + @brief Test cases for the KernelInfo class + """ + + def test_kernel_files_creation(self): + """ + @brief Test KernelInfo creation and attribute access + """ + # Act + kernel_files = KernelInfo( + { + "directory": "/tmp/dir", + "prefix": "prefix", + "minst": "prefix.minst", + "cinst": "prefix.cinst", + "xinst": "prefix.xinst", + "mem": "prefix.mem", + } + ) + + # Assert + assert kernel_files.directory == "/tmp/dir" + assert kernel_files.prefix == "prefix" + assert kernel_files.minst == "prefix.minst" + assert kernel_files.cinst == "prefix.cinst" + assert kernel_files.xinst == "prefix.xinst" + assert kernel_files.mem == "prefix.mem" + + def test_kernel_files_without_mem(self): + """ + @brief Test KernelInfo creation without mem file + """ + # Act + kernel_files = KernelInfo( + { + "directory": "/tmp/dir", + "prefix": "prefix", + "minst": "prefix.minst", + "cinst": "prefix.cinst", + "xinst": "prefix.xinst", + } + ) + + # Assert + assert kernel_files.directory == "/tmp/dir" + assert kernel_files.prefix == "prefix" + assert kernel_files.minst == "prefix.minst" + assert kernel_files.cinst == "prefix.cinst" + assert kernel_files.xinst == "prefix.xinst" + assert kernel_files.mem is None diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_trace_info.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_trace_info.py index 5eddc45a..a867ea3e 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_trace_info.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_trace_info.py @@ -14,61 +14,7 @@ import pytest from linker.kern_trace.context_config import ContextConfig from linker.kern_trace.kernel_op import KernelOp -from linker.kern_trace.trace_info import KernelInfo, TraceInfo - - -class TestKernelInfo: - """ - @class TestKernelInfo - @brief Test cases for the KernelInfo class - """ - - def test_kernel_files_creation(self): - """ - @brief Test KernelInfo creation and attribute access - """ - # Act - kernel_files = KernelInfo( - { - "directory": "/tmp/dir", - "prefix": "prefix", - "minst": "prefix.minst", - "cinst": "prefix.cinst", - "xinst": "prefix.xinst", - "mem": "prefix.mem", - } - ) - - # Assert - assert kernel_files.directory == "/tmp/dir" - assert kernel_files.prefix == "prefix" - assert kernel_files.minst == "prefix.minst" - assert kernel_files.cinst == "prefix.cinst" - assert kernel_files.xinst == "prefix.xinst" - assert kernel_files.mem == "prefix.mem" - - def test_kernel_files_without_mem(self): - """ - @brief Test KernelInfo creation without mem file - """ - # Act - kernel_files = KernelInfo( - { - "directory": "/tmp/dir", - "prefix": "prefix", - "minst": "prefix.minst", - "cinst": "prefix.cinst", - "xinst": "prefix.xinst", - } - ) - - # Assert - assert kernel_files.directory == "/tmp/dir" - assert kernel_files.prefix == "prefix" - assert kernel_files.minst == "prefix.minst" - assert kernel_files.cinst == "prefix.cinst" - assert kernel_files.xinst == "prefix.xinst" - assert kernel_files.mem is None +from linker.kern_trace.trace_info import TraceInfo class TestTraceInfo: @@ -257,7 +203,10 @@ def test_parse_kernel_ops_with_empty_trace(self): trace_file = "/path/to/empty_trace.txt" # Act - with patch("os.path.isfile", return_value=True), patch("builtins.open", mock_open(read_data="")): + with ( + patch("os.path.isfile", return_value=True), + patch("builtins.open", mock_open(read_data="")), + ): trace_info = TraceInfo(trace_file) result = trace_info.parse_kernel_ops() diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py index c73cd794..fe57391e 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py @@ -10,12 +10,12 @@ import io import unittest -from collections import namedtuple from unittest.mock import MagicMock, call, mock_open, patch from assembler.common.config import GlobalConfig from linker import MemoryModel from linker.instructions import cinst, dinst, minst +from linker.kern_trace import InstrAct from linker.steps.program_linker import LinkedProgram @@ -41,7 +41,9 @@ def setUp(self): self.suppress_comments_patcher = patch.object(GlobalConfig, "suppress_comments", False) self.mock_suppress_comments = self.suppress_comments_patcher.start() - self.program = LinkedProgram( + self.program = LinkedProgram() + + self.program.initialize( self.streams["minst"], self.streams["cinst"], self.streams["xinst"], @@ -103,7 +105,8 @@ def test_close(self): # Test closing the program with comments suppressed. with patch.object(GlobalConfig, "suppress_comments", True): - program = LinkedProgram( + program = LinkedProgram() + program.initialize( self.streams["minst"], self.streams["cinst"], self.streams["xinst"], @@ -124,12 +127,14 @@ def test_update_minsts(self): mock_msyncc.target = 5 mock_mload = MagicMock(spec=minst.MLoad) - mock_mload.source = "input_var" + mock_mload.var_name = "input_var" + mock_mload.hbm_address = 0 mock_mload.comment = "original comment" mock_mstore = MagicMock(spec=minst.MStore) - mock_mstore.dest = "output_var" - mock_mstore.comment = None + mock_mstore.var_name = "output_var" + mock_mstore.hbm_address = 0 + mock_mstore.comment = "" # Set up memory model mock self.mem_model.use_variable.side_effect = [ @@ -137,19 +142,36 @@ def test_update_minsts(self): 20, ] # Return different addresses for different vars + # Create mock CInstr for cinstrs_map + mock_cinstr = MagicMock() + mock_cinstr.idx = 5 # Same as msyncc.target + + # Create mock CinstrMapEntry + mock_cinstr_map_entry = MagicMock() + mock_cinstr_map_entry.cinstr = mock_cinstr + + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.minstrs = [mock_msyncc, mock_mload, mock_mstore] + mock_kernel_info.cinstrs_map = {5: mock_cinstr_map_entry} # Map target 5 to mock entry + mock_kernel_info.minstrs_map = [MagicMock(), MagicMock(), MagicMock()] + + # Configure minstrs_map actions + for minstr_map in mock_kernel_info: + minstr_map.action = MagicMock() # Mock the action attribute + # Execute the update - kernel_minstrs = [mock_msyncc, mock_mload, mock_mstore] self.program._cinst_line_offset = 10 # Set initial offset self.program._kernel_count = 1 # Set kernel count - self.program._update_minsts(kernel_minstrs) + self.program._update_minsts(mock_kernel_info) # Verify results self.assertEqual(mock_msyncc.target, 15) # 5 + 10 - self.assertEqual(mock_mload.source, "10") # Replaced with HBM address + self.assertEqual(mock_mload.hbm_address, 10) # Replaced with HBM address self.assertIn("input_var", mock_mload.comment) # Comment updated self.assertIn("original comment", mock_mload.comment) # Original comment preserved - self.assertEqual(mock_mstore.dest, "20") # Replaced with HBM address + self.assertEqual(mock_mstore.hbm_address, 20) # Replaced with HBM address # Verify the memory model was used correctly self.mem_model.use_variable.assert_has_calls([call("input_var", 1), call("output_var", 1)]) @@ -178,29 +200,41 @@ def test_remove_and_merge_csyncm_cnop(self): mock_cnop2.cycles = 3 mock_cnop2.tokens = [0] + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.cinstrs = [ + mock_ifetch, + mock_csyncm1, + mock_cnop1, + mock_csyncm2, + mock_cnop2, + ] + + # Create mock cinstrs_map entries + mock_kernel_info.cinstrs_map = [] + for cinstr in mock_kernel_info.cinstrs: + mock_entry = MagicMock() + mock_entry.action = MagicMock() # Mock the action attribute + mock_entry.cinstr = cinstr + mock_kernel_info.cinstrs_map.append(mock_entry) + # Set up ISACInst.CSyncm.get_throughput with patch("assembler.instructions.cinst.CSyncm.get_throughput", return_value=2): # Execute the method - kernel_cinstrs = [ - mock_ifetch, - mock_csyncm1, - mock_cnop1, - mock_csyncm2, - mock_cnop2, - ] - self.program._remove_and_merge_csyncm_cnop(kernel_cinstrs) - - # Verify CSyncm instructions were removed - self.assertNotIn(mock_csyncm1, kernel_cinstrs) - self.assertNotIn(mock_csyncm2, kernel_cinstrs) + self.program._remove_and_merge_csyncm_cnop(mock_kernel_info) + + # Verify CSyncm instructions' actions were marked as SKIP + # CSyncm1 is at index 1, CSyncm2 is at index 3 + self.assertEqual(mock_kernel_info.cinstrs_map[1].action, InstrAct.SKIP) + self.assertEqual(mock_kernel_info.cinstrs_map[3].action, InstrAct.SKIP) # Verify CNop cycles were updated (should have added 2 for each CSyncm) # First CNop gets 2 cycles added from first CSyncm self.assertEqual(mock_cnop1.cycles, 4) # 2 + 2 # Verify the line numbers were updated - for i, instr in enumerate(kernel_cinstrs): - self.assertEqual(instr.tokens[0], str(i)) + for i, instr in enumerate(mock_kernel_info.cinstrs): + self.assertEqual(instr.idx, str(i)) def test_update_cinsts_addresses_and_offsets(self): """@brief Test updating CInst addresses and offsets. @@ -218,11 +252,13 @@ def test_update_cinsts_addresses_and_offsets(self): # Create SPAD instructions for no-HBM case mock_bload = MagicMock(spec=cinst.BLoad) - mock_bload.source = "var1" + mock_bload.var_name = "var1" + mock_bload.spad_address = 0 mock_bload.comment = "original comment" mock_cstore = MagicMock(spec=cinst.CStore) - mock_cstore.dest = "var2" + mock_cstore.var_name = "var2" + mock_cstore.spad_address = 0 mock_cstore.comment = None # Execute the method with HBM enabled @@ -248,11 +284,11 @@ def test_update_cinsts_addresses_and_offsets(self): self.program._update_cinsts_addresses_and_offsets(kernel_cinstrs) # Verify SPAD instructions were updated - self.assertEqual(mock_bload.source, "30") + self.assertEqual(mock_bload.spad_address, 30) self.assertIn("var1", mock_bload.comment) self.assertIn("original comment", mock_bload.comment) - self.assertEqual(mock_cstore.dest, "40") + self.assertEqual(mock_cstore.spad_address, 40) # Verify the memory model was used correctly self.mem_model.use_variable.assert_has_calls([call("var1", 2), call("var2", 2)]) @@ -271,13 +307,18 @@ def test_update_cinsts(self): patch.object(LinkedProgram, "_remove_and_merge_csyncm_cnop") as mock_remove, patch.object(LinkedProgram, "_update_cinsts_addresses_and_offsets") as mock_update, ): - # Execute the method with HBM enabled - kernel_cinstrs = ["cinst1", "cinst2"] - self.program._update_cinsts(kernel_cinstrs) + mock_cinst1 = MagicMock() + mock_cinst2 = MagicMock() + + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.cinstrs = [mock_cinst1, mock_cinst2] + + self.program._update_cinsts(mock_kernel_info) # Verify that only _update_cinsts_addresses_and_offsets was called mock_remove.assert_not_called() - mock_update.assert_called_once_with(kernel_cinstrs) + mock_update.assert_called_once_with(mock_kernel_info.cinstrs) # Reset mocks mock_remove.reset_mock() @@ -285,11 +326,11 @@ def test_update_cinsts(self): # Execute the method with HBM disabled with patch.object(GlobalConfig, "hasHBM", False): - self.program._update_cinsts(kernel_cinstrs) + self.program._update_cinsts(mock_kernel_info) # Verify that both methods were called - mock_remove.assert_called_once_with(kernel_cinstrs) - mock_update.assert_called_once_with(kernel_cinstrs) + mock_remove.assert_called_once_with(mock_kernel_info) + mock_update.assert_called_once_with(mock_kernel_info.cinstrs) def test_update_xinsts(self): """@brief Test updating XInsts. @@ -338,31 +379,45 @@ def test_link_kernel(self): # Setup mock_update_xinsts to return a bundle offset mock_update_xinsts.return_value = 5 - # Create mock instruction lists - kernel_minstrs = [MagicMock(), MagicMock()] - kernel_cinstrs = [MagicMock(), MagicMock()] - kernel_xinstrs = [MagicMock(), MagicMock()] + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.minstrs = [MagicMock(), MagicMock()] + mock_kernel_info.cinstrs = [MagicMock(), MagicMock()] + mock_kernel_info.xinstrs = [MagicMock(), MagicMock()] + mock_kernel_info.spad_size = 0 # Configure the mocks for to_line method - for i, xinstr in enumerate(kernel_xinstrs): + for i, xinstr in enumerate(mock_kernel_info.xinstrs): xinstr.to_line.return_value = f"xinst{i}" - xinstr.comment = f"xinst_comment{i}" if i % 2 == 0 else None - - for i, cinstr in enumerate(kernel_cinstrs[:-1]): # Skip the last one (cexit) - cinstr.to_line.return_value = f"cinst{i}" - cinstr.comment = f"cinst_comment{i}" if i % 2 == 0 else None + xinstr.comment = f"xinst_comment{i}" - for i, minstr in enumerate(kernel_minstrs[:-1]): # Skip the last one (msyncc) + # Create proper minstrs_map entries with references to mocked instructions + mock_kernel_info.minstrs_map = [] + for i, minstr in enumerate(mock_kernel_info.minstrs): minstr.to_line.return_value = f"minst{i}" - minstr.comment = f"minst_comment{i}" if i % 2 == 0 else None + minstr.comment = f"minst_comment{i}" + minstr_map_entry = MagicMock() + minstr_map_entry.minstr = minstr + minstr_map_entry.action = InstrAct.KEEP_HBM + mock_kernel_info.minstrs_map.append(minstr_map_entry) + + # Create proper cinstrs_map entries with references to mocked instructions + mock_kernel_info.cinstrs_map = [] + for i, cinstr in enumerate(mock_kernel_info.cinstrs): + cinstr.to_line.return_value = f"cinst{i}" + cinstr.comment = f"cinst_comment{i}" + cinstr_map_entry = MagicMock() + cinstr_map_entry.cinstr = cinstr + cinstr_map_entry.action = InstrAct.KEEP_SPAD + mock_kernel_info.cinstrs_map.append(cinstr_map_entry) # Execute the method - self.program.link_kernel(kernel_minstrs, kernel_cinstrs, kernel_xinstrs) + self.program.link_kernel(mock_kernel_info) # Verify update methods were called - mock_update_minsts.assert_called_once_with(kernel_minstrs) - mock_update_cinsts.assert_called_once_with(kernel_cinstrs) - mock_update_xinsts.assert_called_once_with(kernel_xinstrs) + mock_update_minsts.assert_called_once_with(mock_kernel_info) + mock_update_cinsts.assert_called_once_with(mock_kernel_info) + mock_update_xinsts.assert_called_once_with(mock_kernel_info.xinstrs) # Verify bundle offset was updated self.assertEqual(self.program._bundle_offset, 6) # 5 + 1 @@ -413,16 +468,25 @@ def test_link_kernel_with_no_hbm(self): xinstr.to_line.return_value = "xinst" xinstr.comment = None - for cinstr in kernel_cinstrs[:-1]: # Skip the last one (cexit) + for cinstr in kernel_cinstrs: cinstr.to_line.return_value = "cinst" cinstr.comment = None + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.minstrs = kernel_minstrs + mock_kernel_info.cinstrs = kernel_cinstrs + mock_kernel_info.xinstrs = kernel_xinstrs + mock_kernel_info.minstrs_map = [MagicMock(), MagicMock()] + mock_kernel_info.cinstrs_map = [MagicMock(), MagicMock()] + mock_kernel_info.spad_size = 0 + # Execute the method - self.program.link_kernel(kernel_minstrs, kernel_cinstrs, kernel_xinstrs) + self.program.link_kernel(mock_kernel_info) # Verify update methods were called # No minsts should be processed when HBM is disabled - mock_update_cinsts.assert_called_once_with(kernel_cinstrs) + mock_update_cinsts.assert_called_once_with(mock_kernel_info) mock_update_xinsts.assert_called_once_with(kernel_xinstrs) # Verify bundle offset was updated @@ -442,7 +506,7 @@ def test_link_kernel_with_closed_program(self): # Try to link a kernel with self.assertRaises(RuntimeError): - self.program.link_kernel([], [], []) + self.program.link_kernel([]) def test_link_kernel_with_suppress_comments(self): """@brief Test linking a kernel with comments suppressed. @@ -471,8 +535,17 @@ def test_link_kernel_with_suppress_comments(self): kernel_minstrs[0].to_line.return_value = "minst" kernel_minstrs[0].comment = "minst_comment" + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.minstrs = kernel_minstrs + mock_kernel_info.cinstrs = kernel_cinstrs + mock_kernel_info.xinstrs = kernel_xinstrs + mock_kernel_info.minstrs_map = [MagicMock(), MagicMock()] + mock_kernel_info.cinstrs_map = [MagicMock(), MagicMock()] + mock_kernel_info.spad_size = 0 + # Execute the method - self.program.link_kernel(kernel_minstrs, kernel_cinstrs, kernel_xinstrs) + self.program.link_kernel(mock_kernel_info) # Verify comments were suppressed xinst_output = self.streams["xinst"].getvalue() @@ -489,29 +562,27 @@ def test_link_kernels_to_files(self): @test Verifies that kernels are correctly linked and written to output files """ - # Create a namedtuple similar to KernelInfo for testing - KernelInfo = namedtuple("KernelInfo", ["prefix", "minst", "cinst", "xinst", "mem", "remap_dict"]) - - # Arrange - input_files = [ - KernelInfo( - prefix="/tmp/input1", - minst="/tmp/input1.minst", - cinst="/tmp/input1.cinst", - xinst="/tmp/input1.xinst", - mem=None, - remap_dict={}, - ) - ] - - output_files = KernelInfo( - prefix="/tmp/output", - minst="/tmp/output.minst", - cinst="/tmp/output.cinst", - xinst="/tmp/output.xinst", - mem=None, - remap_dict=None, - ) + program = LinkedProgram() + + # Create mock KernelInfo objects + mock_input_kernel = MagicMock() + mock_input_kernel.prefix = "/tmp/input1" + mock_input_kernel.minst = "/tmp/input1.minst" + mock_input_kernel.cinst = "/tmp/input1.cinst" + mock_input_kernel.xinst = "/tmp/input1.xinst" + mock_input_kernel.mem = None + mock_input_kernel.hbm_remap_dict = {} + + mock_output_kernel = MagicMock() + mock_output_kernel.prefix = "/tmp/output" + mock_output_kernel.minst = "/tmp/output.minst" + mock_output_kernel.cinst = "/tmp/output.cinst" + mock_output_kernel.xinst = "/tmp/output.xinst" + mock_output_kernel.mem = None + mock_output_kernel.hbm_remap_dict = None + + kernels_info = [mock_input_kernel] + program_info = mock_output_kernel mock_mem_model = MagicMock() mock_verbose = MagicMock() @@ -531,15 +602,15 @@ def test_link_kernels_to_files(self): "linker.steps.program_linker.Loader.load_xinst_kernel_from_file", return_value=[], ), - patch.object(LinkedProgram, "__init__", return_value=None) as mock_init, + patch.object(LinkedProgram, "initialize", return_value=None) as mock_init, patch.object(LinkedProgram, "link_kernel") as mock_link_kernel, patch.object(LinkedProgram, "close") as mock_close, ): - LinkedProgram.link_kernels_to_files(input_files, output_files, mock_mem_model, mock_verbose) + program.link_kernels_to_files(kernels_info, program_info, mock_mem_model, mock_verbose) # Assert mock_init.assert_called_once() - mock_link_kernel.assert_called_once_with([], [], []) + mock_link_kernel.assert_called_once_with(mock_input_kernel) mock_close.assert_called_once() @@ -564,7 +635,8 @@ def setUp(self): self.suppress_comments_patcher = patch.object(GlobalConfig, "suppress_comments", False) self.mock_suppress_comments = self.suppress_comments_patcher.start() - self.program = LinkedProgram( + self.program = LinkedProgram() + self.program.initialize( self.streams["minst"], self.streams["cinst"], self.streams["xinst"], @@ -645,21 +717,24 @@ def test_validate_spad_address_mismatch(self): class TestJoinDinstKernels(unittest.TestCase): - """@brief Tests for the join_dinst_kernels static method.""" + """@brief Tests for the join_n_prune_dinst_kernels static method.""" def test_join_dinst_kernels_empty(self): """@brief Test joining empty list of DInst kernels. @test Verifies that a ValueError is raised for an empty list """ + program = LinkedProgram() with self.assertRaises(ValueError): - LinkedProgram.join_dinst_kernels([]) + program.join_n_prune_dinst_kernels([]) def test_join_dinst_kernels_single_kernel(self): """@brief Test joining a single DInst kernel. @test Verifies that instructions from a single kernel are correctly processed """ + program = LinkedProgram() + # Create mock DInstructions mock_dload = MagicMock(spec=dinst.DLoad) mock_dload.var = "var1" @@ -668,7 +743,7 @@ def test_join_dinst_kernels_single_kernel(self): mock_dstore.var = "var2" # Execute the method - result = LinkedProgram.join_dinst_kernels([[mock_dload, mock_dstore]]) + result = program.join_n_prune_dinst_kernels([[mock_dload, mock_dstore]]) # Verify result self.assertEqual(len(result), 2) @@ -684,6 +759,8 @@ def test_join_dinst_kernels_multiple_kernels(self): @test Verifies that instructions from multiple kernels are correctly merged """ + program = LinkedProgram() + # Create mock DInstructions for first kernel mock_dload1 = MagicMock(spec=dinst.DLoad) mock_dload1.var = "var1" @@ -702,7 +779,7 @@ def test_join_dinst_kernels_multiple_kernels(self): mock_dstore2.var = "var4" # Execute the method - result = LinkedProgram.join_dinst_kernels([[mock_dload1, mock_dstore1], [mock_dload2, mock_dkeygen, mock_dstore2]]) + result = program.join_n_prune_dinst_kernels([[mock_dload1, mock_dstore1], [mock_dload2, mock_dkeygen, mock_dstore2]]) # Verify result - should contain load1, store1 (output), keygen, store2 (output) # dload2 should be skipped since it loads var2 which is already an output from kernel1 @@ -722,6 +799,9 @@ def test_join_dinst_kernels_with_carry_over_vars(self): @test Verifies that variables used across kernels are properly consolidated """ + + program = LinkedProgram() + # Create mock DInstructions for first kernel mock_dload1 = MagicMock(spec=dinst.DLoad) mock_dload1.var = "var1" @@ -737,7 +817,7 @@ def test_join_dinst_kernels_with_carry_over_vars(self): mock_dstore2.var = "var2" # Same variable is also an output # Execute the method - result = LinkedProgram.join_dinst_kernels([[mock_dload1, mock_dstore1], [mock_dload2, mock_dstore2]]) + result = program.join_n_prune_dinst_kernels([[mock_dload1, mock_dstore1], [mock_dload2, mock_dstore2]]) # Verify result - should contain load1, store2 # Both dload2 and dstore1 should be skipped since var2 is carried over diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_variable_discovery.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_variable_discovery.py index 7e3e121c..d5f3581a 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_variable_discovery.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_variable_discovery.py @@ -9,7 +9,6 @@ """ import unittest -from collections import namedtuple from unittest.mock import MagicMock, patch import pytest @@ -29,21 +28,81 @@ def setUp(self): """@brief Set up test fixtures.""" # Group MInstructions in a dictionary self.m_instrs = { - "load": MagicMock(source="var1"), - "store": MagicMock(dest="var2"), + "load": MagicMock(var_name="var1"), + "store": MagicMock(var_name="var2"), "other": MagicMock(), # MInstruction that's neither MLoad nor MStore } # Group CInstructions in a dictionary self.c_instrs = { - "bload": MagicMock(source="var3"), - "cload": MagicMock(source="var4"), - "bones": MagicMock(source="var5"), - "nload": MagicMock(source="var6"), - "cstore": MagicMock(dest="var7"), + "bload": MagicMock(var_name="var3"), + "cload": MagicMock(var_name="var4"), + "bones": MagicMock(var_name="var5"), + "nload": MagicMock(var_name="var6"), + "cstore": MagicMock(var_name="var7"), "other": MagicMock(), # CInstruction that's none of the above } + def _create_is_instance_mock( + self, + mock_minst_class=None, + mock_cinst_class=None, + mock_minst=None, + mock_cinst=None, + ): + """@brief Create a mock for isinstance that handles tuples of classes.""" + cinstrs = [ + self.c_instrs["bload"], + self.c_instrs["cload"], + self.c_instrs["bones"], + self.c_instrs["nload"], + self.c_instrs["cstore"], + self.c_instrs["other"], + ] + + minstrs = [ + self.m_instrs["load"], + self.m_instrs["store"], + self.m_instrs["other"], + ] + + # Improved mock for isinstance that handles tuples of classes + def mock_isinstance(obj, cls): + # Handle tuple case first + if isinstance(cls, tuple): + return any(mock_isinstance(obj, c) for c in cls) + + # Use a dictionary to map class types to their respective checks + class_checks = {} + + # Only add cinst-related checks if mock_cinst is not None + if mock_cinst is not None and mock_cinst_class is not None: + class_checks.update( + { + mock_cinst_class: lambda: obj in cinstrs, + mock_cinst.BLoad: lambda: obj is self.c_instrs["bload"], + mock_cinst.CLoad: lambda: obj is self.c_instrs["cload"], + mock_cinst.BOnes: lambda: obj is self.c_instrs["bones"], + mock_cinst.NLoad: lambda: obj is self.c_instrs["nload"], + mock_cinst.CStore: lambda: obj is self.c_instrs["cstore"], + } + ) + + # Only add minst-related checks if mock_minst is not None + if mock_minst is not None and mock_minst_class is not None: + class_checks.update( + { + mock_minst_class: lambda: obj in minstrs, + mock_minst.MLoad: lambda: obj is self.m_instrs["load"], + mock_minst.MStore: lambda: obj is self.m_instrs["store"], + } + ) + + # Check if cls is in our mapping and return the result of its check function + return class_checks.get(cls, lambda: False)() + + return mock_isinstance + @patch("linker.steps.variable_discovery.minst") @patch("linker.steps.variable_discovery.MInstruction") @patch("assembler.memory_model.variable.Variable.validateName") @@ -56,39 +115,21 @@ def test_discover_variables_valid(self, mock_validate, mock_minst_class, mock_mi mock_minst.MLoad = MagicMock() mock_minst.MStore = MagicMock() - # Configure type checking at the module level, avoiding patching isinstance - def is_minst_side_effect(obj): - return obj in [ - self.m_instrs["load"], - self.m_instrs["store"], - self.m_instrs["other"], - ] - - def is_mload_side_effect(obj): - return obj is self.m_instrs["load"] - - def is_mstore_side_effect(obj): - return obj is self.m_instrs["store"] - - # Replace the actual isinstance calls in the module with our mock functions - with patch( - "linker.steps.variable_discovery.isinstance", - side_effect=lambda obj, cls: { - mock_minst_class: is_minst_side_effect(obj), - mock_minst.MLoad: is_mload_side_effect(obj), - mock_minst.MStore: is_mstore_side_effect(obj), - }.get(cls, False), - ): + # Test with a list containing both MLoad and MStore + minstrs = [ + self.m_instrs["load"], + self.m_instrs["store"], + self.m_instrs["other"], + ] + + # Get the mock_isinstance function + mock_isinstance = self._create_is_instance_mock(mock_minst_class=mock_minst_class, mock_minst=mock_minst) + + # Patch the isinstance calls at the module level + with patch("linker.steps.variable_discovery.isinstance", side_effect=mock_isinstance): # Configure validateName to return True mock_validate.return_value = True - # Test with a list containing both MLoad and MStore - minstrs = [ - self.m_instrs["load"], - self.m_instrs["store"], - self.m_instrs["other"], - ] - # Call the function result = list(discover_variables(minstrs)) @@ -125,8 +166,9 @@ def test_discover_variables_invalid_type(self): self.assertIn("not a valid MInstruction", str(context.exception)) @patch("linker.steps.variable_discovery.minst") + @patch("linker.steps.variable_discovery.MInstruction") @patch("assembler.memory_model.variable.Variable.validateName") - def test_discover_variables_invalid_variable_name(self, mock_validate, mock_minst): + def test_discover_variables_hbm_invalid(self, mock_validate, mock_minst_class, mock_minst): """@brief Test discovering variables with an invalid variable name. @test Verifies that a RuntimeError is raised when a variable name is invalid @@ -134,13 +176,14 @@ def test_discover_variables_invalid_variable_name(self, mock_validate, mock_mins # Setup mocks mock_minst.MLoad = MagicMock() - # Configure validateName to return False + # Configure validateName to return True mock_validate.return_value = False - with patch( - "linker.steps.variable_discovery.isinstance", - side_effect=lambda obj, cls: True, - ): + # Get the mock_isinstance function + mock_isinstance = self._create_is_instance_mock(mock_minst_class=mock_minst_class, mock_minst=mock_minst) + + # Patch the isinstance calls at the module level + with patch("linker.steps.variable_discovery.isinstance", side_effect=mock_isinstance): # Call the function with self.assertRaises(RuntimeError) as context: list(discover_variables([self.m_instrs["load"]])) @@ -176,24 +219,8 @@ def test_discover_variables_spad_valid(self, mock_validate, mock_cinst_class, mo self.c_instrs["other"], ] - # Improved mock for isinstance that handles tuples of classes - def mock_isinstance(obj, cls): - # Handle tuple case first - if isinstance(cls, tuple): - return any(mock_isinstance(obj, c) for c in cls) - - # Use a dictionary to map class types to their respective checks - class_checks = { - mock_cinst_class: lambda: obj in cinstrs, - mock_cinst.BLoad: lambda: obj is self.c_instrs["bload"], - mock_cinst.CLoad: lambda: obj is self.c_instrs["cload"], - mock_cinst.BOnes: lambda: obj is self.c_instrs["bones"], - mock_cinst.NLoad: lambda: obj is self.c_instrs["nload"], - mock_cinst.CStore: lambda: obj is self.c_instrs["cstore"], - } - - # Check if cls is in our mapping and return the result of its check function - return class_checks.get(cls, lambda: False)() + # Get the mock_isinstance function + mock_isinstance = self._create_is_instance_mock(mock_cinst_class=mock_cinst_class, mock_cinst=mock_cinst) # Patch the isinstance calls at the module level with patch("linker.steps.variable_discovery.isinstance", side_effect=mock_isinstance): @@ -246,22 +273,14 @@ def test_discover_variables_spad_invalid_variable_name(self, mock_validate, mock # Setup mocks mock_cinst.BLoad = MagicMock() - # Configure validateName to return False + # Configure validateName to return True mock_validate.return_value = False - # Mock isinstance to make our mock object appear as CInstruction and BLoad - with patch( - "linker.steps.variable_discovery.isinstance", - side_effect=lambda obj, cls: { - mock_cinst_class: True, - ( - mock_cinst.BLoad, - mock_cinst.CLoad, - mock_cinst.BOnes, - mock_cinst.NLoad, - ): True, - }.get(cls, False), - ): + # Get the mock_isinstance function + mock_isinstance = self._create_is_instance_mock(mock_cinst_class=mock_cinst_class, mock_cinst=mock_cinst) + + # Patch the isinstance calls at the module level + with patch("linker.steps.variable_discovery.isinstance", side_effect=mock_isinstance): # Call the function with self.assertRaises(RuntimeError) as context: list(discover_variables_spad([self.c_instrs["bload"]])) @@ -276,22 +295,9 @@ def test_scan_variables(self): @test Verifies that scan_variables correctly processes input files and updates the memory model in both HBM and non-HBM modes """ - # Create a namedtuple similar to KernelInfo for testing - KernelInfo = namedtuple( - "KernelInfo", - ["directory", "prefix", "minst", "cinst", "xinst", "mem", "remap_dict"], - ) - input_files = [ - KernelInfo( - directory="/tmp", - prefix="input1", - minst="/tmp/input1.minst", - cinst="/tmp/input1.cinst", - xinst="/tmp/input1.xinst", - mem=None, - remap_dict=None, - ) - ] + # Create proper mock KernelInfo objects instead of namedtuples + mock_kernel_info = MagicMock() + input_files = [mock_kernel_info] # Test with both True and False for hasHBM for has_hbm in [True, False]: @@ -300,6 +306,7 @@ def test_scan_variables(self): GlobalConfig.hasHBM = has_hbm mock_mem_model = MagicMock() mock_verbose = MagicMock() + mock_linker = MagicMock() # Act with ( @@ -319,8 +326,9 @@ def test_scan_variables(self): "linker.steps.variable_discovery.discover_variables_spad", return_value=["var1", "var2"], ), + patch("linker.steps.variable_discovery.remap_m_c_instrs_vars"), ): - scan_variables(input_files, mock_mem_model, mock_verbose) + scan_variables(mock_linker, input_files, mock_mem_model, mock_verbose) # Assert self.assertEqual(mock_mem_model.add_variable.call_count, 2) From 2a6766a88386e30deb6c1cdd217e74662a029b18 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Wed, 13 Aug 2025 01:03:30 +0000 Subject: [PATCH 04/12] Adding unit tests --- .../linker/kern_trace/kernel_info.py | 16 +- .../linker/steps/program_linker_utils.py | 3 + .../test_kern_trace/test_kernel_info.py | 230 +++- .../test_steps/test_program_linker.py | 1040 ++++++++++++++++- .../test_steps/test_program_linker_utils.py | 396 +++++++ 5 files changed, 1641 insertions(+), 44 deletions(-) create mode 100644 assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker_utils.py diff --git a/assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py b/assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py index f9b4df0d..3888d13f 100644 --- a/assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py +++ b/assembler_tools/hec-assembler-tools/linker/kern_trace/kernel_info.py @@ -178,7 +178,7 @@ def minstrs(self) -> list[MInstruction]: """ @brief Returns the kernel minst instructions if loaded. - @return Optional[dict]: The dict of kernel minst instructions or None if not loaded. + @return Optional[dict]: The dict of kernel minst instructions. """ return self._minstrs @@ -189,6 +189,8 @@ def minstrs(self, value: list[MInstruction]): @param value: The dict of kernel minst instructions to set. """ + if not isinstance(value, list): + raise TypeError("minstrs must be a list.") self._minstrs = value self._fill_minstrs_map() @@ -237,7 +239,7 @@ def cinstrs(self) -> list[CInstruction]: """ @brief Returns the kernel cinst instructions if loaded. - @return Optional[list]: The list of kernel cinst instructions or None if not loaded. + @return Optional[list]: The list of kernel cinst instructions. """ return self._cinstrs @@ -248,8 +250,8 @@ def cinstrs(self, value: list[CInstruction]): @param value: The list of kernel cinst instructions to set. """ - if value is not None and not isinstance(value, list): - raise TypeError("cinstrs must be a list or None.") + if not isinstance(value, list): + raise TypeError("cinstrs must be a list.") self._cinstrs = value self._fill_cinstrs_map() @@ -258,7 +260,7 @@ def xinstrs(self) -> list[XInstruction]: """ @brief Returns the kernel xinst instructions if loaded. - @return Optional[list]: The list of kernel xinst instructions or None if not loaded. + @return Optional[list]: The list of kernel xinst instructions. """ return self._xinstrs @@ -269,8 +271,8 @@ def xinstrs(self, value: list[XInstruction]): @param value: The list of kernel xinst instructions to set. """ - if value is not None and not isinstance(value, list): - raise TypeError("xinstrs must be a list or None.") + if not isinstance(value, list): + raise TypeError("xinstrs must be a list.") self._xinstrs = value def _fill_minstrs_map(self): diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py index cffd708b..0a80b428 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py @@ -87,6 +87,9 @@ def search_minstrs_back(minstrs_map: list, idx: int, spad_address: int) -> int: @return int Index for the MLoad instruction associated with the SPAD address. """ # Traverse backwards from idx, including idx + if idx < 0 or idx >= len(minstrs_map): + raise IndexError(f"Index {idx} is out of bounds for minstrs_map of length {len(minstrs_map)}.") + for i in range(idx, -1, -1): minstr = minstrs_map[i].minstr if isinstance(minstr, minst.MLoad) and minstrs_map[i].spad_addr == spad_address: diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py index 2a237d33..15a3af61 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_kern_trace/test_kernel_info.py @@ -9,7 +9,11 @@ @brief Unit tests for the KernelInfo class """ -from linker.kern_trace.kernel_info import KernelInfo +from unittest.mock import MagicMock + +import pytest +from linker.instructions import cinst, minst +from linker.kern_trace.kernel_info import InstrAct, KernelInfo class TestKernelInfo: @@ -64,3 +68,227 @@ def test_kernel_files_without_mem(self): assert kernel_files.cinst == "prefix.cinst" assert kernel_files.xinst == "prefix.xinst" assert kernel_files.mem is None + + def test_files_property(self): + """ + @brief Test files property returns correct list of files + """ + # With mem file + kernel_files = KernelInfo( + { + "directory": "/tmp/dir", + "prefix": "prefix", + "minst": "prefix.minst", + "cinst": "prefix.cinst", + "xinst": "prefix.xinst", + "mem": "prefix.mem", + } + ) + + expected_files = ["prefix.minst", "prefix.cinst", "prefix.xinst", "prefix.mem"] + assert kernel_files.files == expected_files + + # Without mem file + kernel_files_no_mem = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + expected_files_no_mem = ["prefix.minst", "prefix.cinst", "prefix.xinst"] + assert kernel_files_no_mem.files == expected_files_no_mem + + def test_hbm_remap_dict_property(self): + """ + @brief Test hbm_remap_dict getter and setter + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Test initial empty dict + assert kernel_files.hbm_remap_dict == {} + + # Test setter with valid dict + remap_dict = {"old_var": "new_var", "var1": "var2"} + kernel_files.hbm_remap_dict = remap_dict + assert kernel_files.hbm_remap_dict == remap_dict + + # Test setter with invalid type + with pytest.raises(TypeError, match="Remap dictionary must be of type dict"): + kernel_files.hbm_remap_dict = ["not", "a", "dict"] + + def test_spad_size_property(self): + """ + @brief Test spad_size getter and setter + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Test initial value + assert kernel_files.spad_size == 0 + + # Test setter with valid int + kernel_files.spad_size = 42 + assert kernel_files.spad_size == 42 + + # Test setter with invalid type + with pytest.raises(TypeError, match="Scratchpad offset must be an integer"): + kernel_files.spad_size = "not an int" + + def test_minstrs_property_and_map_filling(self): + """ + @brief Test minstrs property and automatic map filling + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Create mock instructions + mock_mload = MagicMock() + mock_mload.spad_address = 10 + + mock_msyncc = MagicMock(spec=minst.MSyncc) + + mock_mstore = MagicMock() + mock_mstore.spad_address = 20 + + minstrs = [mock_mload, mock_msyncc, mock_mstore] + + # Test setter + kernel_files.minstrs = minstrs + assert kernel_files.minstrs == minstrs + + # Test that minstrs_map was automatically filled + assert len(kernel_files.minstrs_map) == 3 + + # Check first entry (mload) + assert kernel_files.minstrs_map[0].spad_addr == 10 + assert kernel_files.minstrs_map[0].minstr == mock_mload + assert kernel_files.minstrs_map[0].action == InstrAct.KEEP_HBM + + # Check second entry (msyncc - should have spad_addr -1) + assert kernel_files.minstrs_map[1].spad_addr == -1 + assert kernel_files.minstrs_map[1].minstr == mock_msyncc + assert kernel_files.minstrs_map[1].action == InstrAct.KEEP_HBM + + # Check third entry (mstore) + assert kernel_files.minstrs_map[2].spad_addr == 20 + assert kernel_files.minstrs_map[2].minstr == mock_mstore + assert kernel_files.minstrs_map[2].action == InstrAct.KEEP_HBM + + def test_minstrs_map_property(self): + """ + @brief Test minstrs_map getter and setter + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Test initial empty list + assert kernel_files.minstrs_map == [] + + # Test setter with valid list + mock_entry = MagicMock() + new_map = [mock_entry] + kernel_files.minstrs_map = new_map + assert kernel_files.minstrs_map == new_map + + # Test setter with invalid type + with pytest.raises(TypeError, match="minstrs_map must be a list"): + kernel_files.minstrs_map = "not a list" + + def test_cinstrs_property_and_map_filling(self): + """ + @brief Test cinstrs property and automatic map filling + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Create mock instructions + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.tokens = ["0", "cload", "reg1", "var1"] + + mock_csyncm = MagicMock() + mock_csyncm.tokens = ["1", "csyncm", "5"] + + mock_bload = MagicMock(spec=cinst.BLoad) + mock_bload.tokens = ["2", "bload", "reg2", "var2"] + + cinstrs = [mock_cload, mock_csyncm, mock_bload] + + # Test setter + kernel_files.cinstrs = cinstrs + assert kernel_files.cinstrs == cinstrs + + # Test that cinstrs_map was automatically filled + assert len(kernel_files.cinstrs_map) == 3 + + # Check first entry (cload - should have reg_name from tokens[2]) + assert kernel_files.cinstrs_map[0].reg_name == "reg1" + assert kernel_files.cinstrs_map[0].cinstr == mock_cload + assert kernel_files.cinstrs_map[0].action == InstrAct.KEEP_SPAD + + # Check second entry (csyncm - should have empty reg_name) + assert kernel_files.cinstrs_map[1].reg_name == "" + assert kernel_files.cinstrs_map[1].cinstr == mock_csyncm + assert kernel_files.cinstrs_map[1].action == InstrAct.KEEP_SPAD + + # Check third entry (bload - should have reg_name from tokens[2]) + assert kernel_files.cinstrs_map[2].reg_name == "reg2" + assert kernel_files.cinstrs_map[2].cinstr == mock_bload + assert kernel_files.cinstrs_map[2].action == InstrAct.KEEP_SPAD + + def test_cinstrs_map_property(self): + """ + @brief Test cinstrs_map getter and setter + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Test initial empty list + assert kernel_files.cinstrs_map == [] + + # Test setter with valid list + mock_entry = MagicMock() + new_map = [mock_entry] + kernel_files.cinstrs_map = new_map + assert kernel_files.cinstrs_map == new_map + + # Test setter with invalid type + with pytest.raises(TypeError, match="cinstrs_map must be a list"): + kernel_files.cinstrs_map = "not a list" + + def test_xinstrs_property(self): + """ + @brief Test xinstrs property getter and setter + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Test initial empty list + assert kernel_files.xinstrs == [] + + # Test setter with valid list + mock_xinstr = MagicMock() + xinstrs = [mock_xinstr] + kernel_files.xinstrs = xinstrs + assert kernel_files.xinstrs == xinstrs + + # Test setter with invalid type + with pytest.raises(TypeError, match="xinstrs must be a list"): + kernel_files.xinstrs = None + + def test_cinstrs_setter_with_none(self): + """ + @brief Test cinstrs setter with None value + """ + kernel_files = KernelInfo( + {"directory": "/tmp/dir", "prefix": "prefix", "minst": "prefix.minst", "cinst": "prefix.cinst", "xinst": "prefix.xinst"} + ) + + # Test setter with invalid type + with pytest.raises(TypeError, match="cinstrs must be a list"): + kernel_files.cinstrs = None diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py index fe57391e..2212dc24 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py @@ -12,6 +12,7 @@ import unittest from unittest.mock import MagicMock, call, mock_open, patch +import pytest from assembler.common.config import GlobalConfig from linker import MemoryModel from linker.instructions import cinst, dinst, minst @@ -117,64 +118,118 @@ def test_close(self): # Should not contain "terminating MInstQ" comment self.assertNotIn("terminating MInstQ", self.streams["minst"].getvalue()) - def test_update_minsts(self): - """@brief Test updating MInsts. + def test_update_minsts_no_mem_model(self): + """@brief Test updating MInsts when no memory model is available. - @test Verifies that MInsts are correctly updated with offsets and variable addresses + @test Verifies that RuntimeError is raised when memory model is None """ # Create mock MInstructions - mock_msyncc = MagicMock(spec=minst.MSyncc) - mock_msyncc.target = 5 - mock_mload = MagicMock(spec=minst.MLoad) mock_mload.var_name = "input_var" mock_mload.hbm_address = 0 mock_mload.comment = "original comment" - mock_mstore = MagicMock(spec=minst.MStore) - mock_mstore.var_name = "output_var" - mock_mstore.hbm_address = 0 - mock_mstore.comment = "" + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.minstrs = [mock_mload] + mock_kernel_info.minstrs_map = [MagicMock()] + + # Set memory model to None + self.program._LinkedProgram__mem_model = None - # Set up memory model mock + # Execute the update and verify RuntimeError is raised + with pytest.raises(RuntimeError, match="Memory model is not initialized"): + self.program._update_minsts(mock_kernel_info) + + def test_update_minsts(self): + """@brief Test updating MInsts with SPAD addresses when HBM is enabled. + + @test Verifies that SPAD addresses are correctly updated with _spad_offset when linking multiple kernels + """ + self.program._kernel_count = 1 # Set kernel count + self.program._cinst_line_offset = 10 # Set initial offset + + # Create mock MInstructions with initial SPAD addresses + mock_msyncc = MagicMock(spec=minst.MSyncc) + mock_msyncc.target = 1 + + mock_mload1 = MagicMock(spec=minst.MLoad) + mock_mload1.var_name = "input_var1" + mock_mload1.hbm_address = 0 + mock_mload1.spad_address = 5 + mock_mload1.comment = "original comment" + + mock_mstore1 = MagicMock(spec=minst.MStore) + mock_mstore1.var_name = "output_var1" + mock_mstore1.hbm_address = 0 + mock_mstore1.spad_address = 10 + mock_mstore1.comment = "Storing output_var1" + + mock_mload2 = MagicMock(spec=minst.MLoad) + mock_mload2.var_name = "input_var2" + mock_mload2.hbm_address = 0 + mock_mload2.spad_address = 15 + mock_mload2.comment = "another comment" + + # Set up memory model mock to return HBM addresses self.mem_model.use_variable.side_effect = [ - 10, - 20, - ] # Return different addresses for different vars + 100, # HBM address for input_var1 + 200, # HBM address for output_var1 + 300, # HBM address for input_var2 + ] + + # Create mock KernelInfo + mock_kernel_info = MagicMock() + mock_kernel_info.minstrs = [mock_mload1, mock_msyncc, mock_mstore1, mock_mload2] + mock_kernel_info.minstrs_map = [MagicMock(), MagicMock(), MagicMock(), MagicMock()] + + # Configure minstrs_map actions to KEEP_HBM for HBM mode + for minstr_map in mock_kernel_info.minstrs_map: + minstr_map.action = InstrAct.KEEP_HBM # Create mock CInstr for cinstrs_map mock_cinstr = MagicMock() - mock_cinstr.idx = 5 # Same as msyncc.target + mock_cinstr.idx = 6 # Same as msyncc.target # Create mock CinstrMapEntry mock_cinstr_map_entry = MagicMock() mock_cinstr_map_entry.cinstr = mock_cinstr + mock_kernel_info.cinstrs_map = [MagicMock(), mock_cinstr_map_entry] - # Create mock KernelInfo - mock_kernel_info = MagicMock() - mock_kernel_info.minstrs = [mock_msyncc, mock_mload, mock_mstore] - mock_kernel_info.cinstrs_map = {5: mock_cinstr_map_entry} # Map target 5 to mock entry - mock_kernel_info.minstrs_map = [MagicMock(), MagicMock(), MagicMock()] - - # Configure minstrs_map actions - for minstr_map in mock_kernel_info: - minstr_map.action = MagicMock() # Mock the action attribute + # Set SPAD offset to test address adjustment + self.program._spad_offset = 50 + self.program._kernel_count = 1 # Execute the update - self.program._cinst_line_offset = 10 # Set initial offset - self.program._kernel_count = 1 # Set kernel count self.program._update_minsts(mock_kernel_info) - # Verify results - self.assertEqual(mock_msyncc.target, 15) # 5 + 10 - self.assertEqual(mock_mload.hbm_address, 10) # Replaced with HBM address - self.assertIn("input_var", mock_mload.comment) # Comment updated - self.assertIn("original comment", mock_mload.comment) # Original comment preserved - - self.assertEqual(mock_mstore.hbm_address, 20) # Replaced with HBM address - - # Verify the memory model was used correctly - self.mem_model.use_variable.assert_has_calls([call("input_var", 1), call("output_var", 1)]) + # Verify MSyncc target was updated with _cinst_line_offset + self.assertEqual(mock_msyncc.target, 16) # 5 + 10 + + # Verify SPAD addresses were updated with _spad_offset + self.assertEqual(mock_mload1.spad_address, 55) # 5 + 50 + self.assertEqual(mock_mstore1.spad_address, 60) # 10 + 50 + self.assertEqual(mock_mload2.spad_address, 65) # 15 + 50 + + # Verify HBM addresses were updated with memory model addresses + self.assertEqual(mock_mload1.hbm_address, 100) + self.assertEqual(mock_mstore1.hbm_address, 200) + self.assertEqual(mock_mload2.hbm_address, 300) + + # Verify comments were updated with variable names + self.assertIn("input_var1", mock_mload1.comment) + self.assertIn("original comment", mock_mload1.comment) + self.assertIn("output_var1", mock_mstore1.comment) + self.assertIn("input_var2", mock_mload2.comment) + self.assertIn("another comment", mock_mload2.comment) + + # Verify the memory model was called with correct parameters + expected_calls = [ + call("input_var1", 1), # kernel_count = 1 + call("output_var1", 1), + call("input_var2", 1), + ] + self.mem_model.use_variable.assert_has_calls(expected_calls) def test_remove_and_merge_csyncm_cnop(self): """@brief Test removing CSyncm instructions and merging CNop instructions. @@ -332,6 +387,107 @@ def test_update_cinsts(self): mock_remove.assert_called_once_with(mock_kernel_info) mock_update.assert_called_once_with(mock_kernel_info.cinstrs) + def test_update_cinst_kernel_hbm(self): + """@brief Test updating CInsts in HBM mode. + + @test Verifies that CInst instructions are correctly updated with synchronization points + and SPAD address mappings in HBM mode + """ + # Create mock CInstructions + mock_csyncm = MagicMock(spec=cinst.CSyncm) + mock_csyncm.target = 2 + mock_csyncm.comment = "sync comment" + + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.var_name = "input_var" + mock_cload.spad_address = 10 + mock_cload.comment = "load input variable" + + mock_cstore = MagicMock(spec=cinst.CStore) + mock_cstore.var_name = "output_var" + mock_cstore.spad_address = 20 + mock_cstore.comment = "" + + mock_nload = MagicMock(spec=cinst.NLoad) + mock_nload.var_name = "nload_var" + mock_nload.comment = "" + mock_nload.spad_address = 15 + + # Create mock MInstructions + mock_mload = MagicMock(spec=minst.MLoad) + mock_mload.var_name = "input_var" + mock_mload.spad_address = 100 + mock_mload.comment = "load input variable" + mock_mload.idx = 0 + + mock_mstore = MagicMock(spec=minst.MStore) + mock_mstore.var_name = "output_var" + mock_mstore.spad_address = 200 + mock_mstore.comment = "" + mock_mstore.idx = 1 + + mock_nload_minstr = MagicMock(spec=minst.MLoad) + mock_nload_minstr.var_name = "nload_var" + mock_nload_minstr.spad_address = 150 + mock_nload_minstr.comment = "nload comment" + mock_nload_minstr.idx = 2 + + # Create mock KernelInfo + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_csyncm, mock_cload, mock_cstore, mock_nload] + mock_kernel.minstrs = [mock_mload, mock_nload_minstr, mock_mstore] + + # Create mock cinstrs_map + mock_kernel.cinstrs_map = [MagicMock(), MagicMock(), MagicMock(), MagicMock()] + for entry in mock_kernel.cinstrs_map: + entry.action = InstrAct.KEEP_SPAD + + # Create mock minstrs_map + mock_mload_entry = MagicMock() + mock_mload_entry.minstr = mock_mload + mock_mload_entry.spad_addr = 10 + + mock_mstore_entry = MagicMock() + mock_mstore_entry.minstr = mock_mstore + mock_mstore_entry.spad_addr = 20 + + mock_nload_entry = MagicMock() + mock_nload_entry.minstr = mock_nload_minstr + mock_nload_entry.spad_addr = 15 + + mock_kernel.minstrs_map = [mock_mload_entry, mock_nload_entry, mock_mstore_entry] + + # Mock the search functions + with patch("linker.steps.program_linker.search_minstrs_back", return_value=0) as mock_search_back: + with patch("linker.steps.program_linker.search_minstrs_forward") as mock_search_forward: + mock_search_forward.side_effect = [2, 1] # First call returns 2, second call returns 1 + + # Execute the method + self.program._update_cinst_kernel_hbm(mock_kernel) + + # Verify CSyncm target was updated to MInst idx + self.assertEqual(mock_csyncm.target, 1) # Should be set to mstore.idx + + # Verify CLoad was updated with correct variable name and SPAD address + self.assertEqual(mock_cload.var_name, "input_var") + self.assertEqual(mock_cload.spad_address, 100) + + # Verify CStore was updated with correct variable name and SPAD address + self.assertEqual(mock_cstore.var_name, "output_var") + self.assertEqual(mock_cstore.spad_address, 200) + + # Verify variable was added to tracker + self.assertEqual(self.program._cinst_in_var_tracker["output_var"], 200) + + # Verify NLoad was updated with correct variable name and SPAD address + self.assertEqual(mock_nload.var_name, "nload_var") + self.assertEqual(mock_nload.spad_address, 150) + + # Verify search functions were called correctly + mock_search_back.assert_called_with(mock_kernel.minstrs_map, 2, 10) + mock_search_forward.assert_any_call(mock_kernel.minstrs_map, 2, 20) + mock_search_forward.assert_any_call(mock_kernel.minstrs_map, 0, 15) + def test_update_xinsts(self): """@brief Test updating XInsts. @@ -613,6 +769,26 @@ def test_link_kernels_to_files(self): mock_link_kernel.assert_called_once_with(mock_input_kernel) mock_close.assert_called_once() + def test_flush_buffers(self): + """@brief Test flushing the CInst and MInst input variable trackers. + + @test Verifies that buffers are correctly cleared and SPAD offset is reset + """ + # Set up some data in the trackers and SPAD offset + self.program._cinst_in_var_tracker = {"var1": 10, "var2": 20, "var3": 30} + self.program._minst_in_var_tracker = {"var4": 40, "var5": 50} + self.program._spad_offset = 100 + + # Execute the method + self.program.flush_buffers() + + # Verify that all trackers are cleared + self.assertEqual(self.program._cinst_in_var_tracker, {}) + self.assertEqual(self.program._minst_in_var_tracker, {}) + + # Verify that SPAD offset is reset to 0 + self.assertEqual(self.program._spad_offset, 0) + class TestLinkedProgramValidation(unittest.TestCase): """@brief Tests for the validation methods of the LinkedProgram class.""" @@ -828,5 +1004,797 @@ def test_join_dinst_kernels_with_carry_over_vars(self): self.assertIn(mock_dstore2, result) # Final output for var2 +class TestPruneCinstKernel(unittest.TestCase): + """@brief Tests for the prune_cinst_kernel methods.""" + + def setUp(self): + """@brief Set up test fixtures.""" + self.streams = { + "minst": io.StringIO(), + "cinst": io.StringIO(), + "xinst": io.StringIO(), + } + self.mem_model = MagicMock(spec=MemoryModel) + + # Mock the hasHBM property to return True by default + self.has_hbm_patcher = patch.object(GlobalConfig, "hasHBM", True) + self.mock_has_hbm = self.has_hbm_patcher.start() + + self.program = LinkedProgram() + self.program.initialize( + self.streams["minst"], + self.streams["cinst"], + self.streams["xinst"], + self.mem_model, + ) + + def tearDown(self): + """@brief Tear down test fixtures.""" + self.has_hbm_patcher.stop() + + def test_prune_cinst_kernel_hbm_ifetch_resets_cycles(self): + """@brief Test that IFetch resets adjust_cycles in HBM mode.""" + # Create mock instructions + mock_ifetch = MagicMock(spec=cinst.IFetch) + mock_cnop = MagicMock(spec=cinst.CNop) + mock_cnop.cycles = 5 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_ifetch, mock_cnop] + mock_kernel.cinstrs_map = [MagicMock(), MagicMock()] + + self.program.prune_cinst_kernel_hbm(mock_kernel) + + # CNop cycles should remain unchanged since adjust_cycles is reset by IFetch + self.assertEqual(mock_cnop.cycles, 5) + + def test_prune_cinst_kernel_hbm_cnop_adds_cycles(self): + """@brief Test that CNop adds adjust_cycles in HBM mode.""" + # Create mock instructions + mock_cnop = MagicMock(spec=cinst.CNop) + mock_cnop.cycles = 3 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cnop] + mock_kernel.cinstrs_map = [MagicMock()] + mock_kernel.minstrs_map = [] + + # Set up program to have some adjust_cycles + with patch.object(self.program, "_intermediate_vars", ["var1"]): + # Mock a CLoad that would be skipped to create adjust_cycles + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.spad_address = 10 + mock_cload.var_name = "test_var" + + mock_kernel.cinstrs = [mock_cload, mock_cnop] + mock_kernel.cinstrs_map = [MagicMock(), MagicMock()] + + # Mock minstr that would be found and skipped + mock_minstr = MagicMock() + mock_minstr.var_name = "test_var" + mock_minstr_entry = MagicMock() + mock_minstr_entry.minstr = mock_minstr + mock_minstr_entry.action = InstrAct.SKIP + mock_kernel.minstrs_map = [mock_minstr_entry] + + with patch("linker.steps.program_linker.search_minstrs_back", return_value=0): + with patch("linker.steps.program_linker.calculate_instruction_latency_adjustment", return_value=2): + self.program.prune_cinst_kernel_hbm(mock_kernel) + + # CNop should have added the adjustment cycles + self.assertEqual(mock_cnop.cycles, 5) # 3 + 2 + + def test_prune_cinst_kernel_hbm_csyncm_tracks_index(self): + """@brief Test that CSyncm tracks minst index in HBM mode.""" + # Create mock instructions + mock_csyncm = MagicMock(spec=cinst.CSyncm) + mock_csyncm.target = 1 + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.spad_address = 10 + mock_cload.var_name = "test_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_csyncm, mock_cload] + mock_kernel.cinstrs_map = [MagicMock(), MagicMock()] + mock_kernel.cinstrs_map[1].action = InstrAct.KEEP_SPAD + + # Mock minstr + mock_minstr = MagicMock() + mock_minstr.var_name = "test_var" + mock_minstr_entry = MagicMock() + mock_minstr_entry.minstr = mock_minstr + mock_minstr_entry.action = InstrAct.KEEP_HBM + mock_kernel.minstrs_map = [mock_minstr_entry, mock_minstr_entry] + + # Verify search was called with correct syncm_idx + with patch("linker.steps.program_linker.search_minstrs_back") as mock_search: + mock_search.return_value = 0 + self.program.prune_cinst_kernel_hbm(mock_kernel) + mock_search.assert_called_with(mock_kernel.minstrs_map, 1, 10) + + def test_prune_cinst_kernel_hbm_cload_with_skipped_minstr(self): + """@brief Test CLoad handling when corresponding minstr is skipped in HBM mode.""" + # Create mock CLoad + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.spad_address = 10 + mock_cload.var_name = "test_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cload] + mock_kernel.cinstrs_map = [MagicMock()] + + # Mock minstr that is skipped + mock_minstr = MagicMock() + mock_minstr.var_name = "test_var" + mock_minstr_entry = MagicMock() + mock_minstr_entry.minstr = mock_minstr + mock_minstr_entry.action = InstrAct.SKIP + mock_kernel.minstrs_map = [mock_minstr_entry] + + with patch("linker.steps.program_linker.search_minstrs_back", return_value=0): + with patch("linker.steps.program_linker_utils.calculate_instruction_latency_adjustment", return_value=3): + with patch("linker.steps.program_linker_utils.remove_csyncm", return_value=(-1, 2)): + self.program.prune_cinst_kernel_hbm(mock_kernel) + + # CLoad should be marked as SKIP + self.assertEqual(mock_kernel.cinstrs_map[0].action, InstrAct.SKIP) + # Variable name should be updated + self.assertEqual(mock_cload.var_name, "test_var") + + def test_prune_cinst_kernel_hbm_cload_with_intermediate_var(self): + """@brief Test CLoad handling with intermediate variable in HBM mode.""" + # Set up intermediate variables + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock CLoad + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.spad_address = 10 + mock_cload.var_name = "intermediate_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cload] + mock_kernel.cinstrs_map = [MagicMock()] + + # Mock minstr + mock_minstr = MagicMock() + mock_minstr.var_name = "intermediate_var" + mock_minstr_entry = MagicMock() + mock_minstr_entry.minstr = mock_minstr + mock_minstr_entry.action = InstrAct.KEEP_HBM + mock_kernel.minstrs_map = [mock_minstr_entry] + + with patch("linker.steps.program_linker.search_minstrs_back", return_value=0): + with patch("linker.steps.program_linker.remove_csyncm", return_value=(-1, 2)) as mock_remove: + self.program.prune_cinst_kernel_hbm(mock_kernel) + + # Should call remove_csyncm for intermediate variable + mock_remove.assert_called_with(mock_kernel.cinstrs, mock_kernel.cinstrs_map, -1) + + def test_prune_cinst_kernel_hbm_cstore_with_skipped_minstr(self): + """@brief Test CStore handling when corresponding minstr is skipped in HBM mode.""" + # Create mock CStore + mock_cstore = MagicMock(spec=cinst.CStore) + mock_cstore.spad_address = 20 + mock_cstore.var_name = "output_var" + mock_cstore.idx = 1 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cstore] + mock_kernel.cinstrs_map = [MagicMock()] + + # Mock minstr that is skipped + mock_minstr = MagicMock() + mock_minstr.var_name = "output_var" + mock_minstr_entry = MagicMock() + mock_minstr_entry.minstr = mock_minstr + mock_minstr_entry.action = InstrAct.SKIP + mock_kernel.minstrs_map = [mock_minstr_entry] + + with patch("linker.steps.program_linker.search_minstrs_forward", return_value=0): + with patch("assembler.instructions.cinst.CStore.get_latency", return_value=4): + self.program.prune_cinst_kernel_hbm(mock_kernel) + + # CStore should be marked as SKIP + self.assertEqual(mock_kernel.cinstrs_map[0].action, InstrAct.SKIP) + + def test_prune_cinst_kernel_hbm_cstore_with_intermediate_var(self): + """@brief Test CStore handling with intermediate variable in HBM mode.""" + # Set up intermediate variables + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock CStore + mock_cstore = MagicMock(spec=cinst.CStore) + mock_cstore.var_name = "intermediate_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cstore] + mock_kernel.cinstrs_map = [MagicMock()] + + # Mock minstr + mock_minstr = MagicMock() + mock_minstr.var_name = "intermediate_var" + mock_minstr_entry = MagicMock() + mock_minstr_entry.minstr = mock_minstr + mock_minstr_entry.action = InstrAct.KEEP_HBM + mock_kernel.minstrs_map = [mock_minstr_entry] + + with patch("linker.steps.program_linker.search_minstrs_forward", return_value=0): + with patch("linker.steps.program_linker.remove_csyncm", return_value=(-1, 2)) as mock_remove: + self.program.prune_cinst_kernel_hbm(mock_kernel) + + # Should call remove_csyncm for intermediate variable + mock_remove.assert_called_with(mock_kernel.cinstrs, mock_kernel.cinstrs_map, 1) + + def test_prune_cinst_kernel_no_hbm_with_keep_hbm_boundary(self): + """@brief Test that prune_cinst_kernel_no_hbm returns early when keep_hbm_boundary is True.""" + # Set keep_hbm_boundary to True + program = LinkedProgram(keep_hbm_boundary=True) + program.initialize( + self.streams["minst"], + self.streams["cinst"], + self.streams["xinst"], + self.mem_model, + ) + + mock_kernel = MagicMock() + mock_kernel.cinstrs = [MagicMock()] + + # Should return early without processing + program.prune_cinst_kernel_no_hbm(mock_kernel) + + # No changes should be made to the kernel + self.assertIsNotNone(mock_kernel.cinstrs) + + def test_prune_cinst_kernel_no_hbm_ifetch_resets_cycles(self): + """@brief Test that IFetch resets adjust_cycles in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Create mock instructions + mock_ifetch = MagicMock(spec=cinst.IFetch) + mock_cnop = MagicMock(spec=cinst.CNop) + mock_cnop.cycles = 5 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_ifetch, mock_cnop] + mock_kernel.cinstrs_map = [MagicMock(), MagicMock()] + + self.program.prune_cinst_kernel_no_hbm(mock_kernel) + + # CNop cycles should remain unchanged since adjust_cycles is reset by IFetch + self.assertEqual(mock_cnop.cycles, 5) + + def test_prune_cinst_kernel_no_hbm_bload_processing(self): + """@brief Test BLoad processing in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Create mock BLoad + mock_bload = MagicMock(spec=cinst.BLoad) + mock_bload.var_name = "test_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_bload] + mock_kernel.cinstrs_map = [MagicMock()] + + with patch("linker.steps.program_linker.process_bload_instructions", return_value=0) as mock_process: + self.program.prune_cinst_kernel_no_hbm(mock_kernel) + + # Should call process_bload_instructions + mock_process.assert_called_with(mock_kernel.cinstrs, mock_kernel.cinstrs_map, self.program._cinst_in_var_tracker, 0) + + # Variable should be added to tracker + self.assertEqual(self.program._cinst_in_var_tracker["test_var"], 0) + + def test_prune_cinst_kernel_no_hbm_cload_already_loaded(self): + """@brief Test CLoad handling when variable already loaded in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Set up variable tracker + self.program._cinst_in_var_tracker = {"loaded_var": 5} + + # Create mock CLoad + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.var_name = "loaded_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cload] + mock_kernel.cinstrs_map = [MagicMock()] + + with patch("linker.steps.program_linker_utils.calculate_instruction_latency_adjustment", return_value=3): + self.program.prune_cinst_kernel_no_hbm(mock_kernel) + + # CLoad should be marked as SKIP + self.assertEqual(mock_kernel.cinstrs_map[0].action, InstrAct.SKIP) + + def test_prune_cinst_kernel_no_hbm_cload_intermediate_var(self): + """@brief Test CLoad handling with intermediate variable in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Set up intermediate variables + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock CLoad + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.var_name = "intermediate_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cload] + mock_kernel.cinstrs_map = [MagicMock()] + + self.program.prune_cinst_kernel_no_hbm(mock_kernel) + + # CLoad should be marked as SKIP + self.assertEqual(mock_kernel.cinstrs_map[0].action, InstrAct.SKIP) + + def test_prune_cinst_kernel_no_hbm_cload_keep_instruction(self): + """@brief Test CLoad when instruction should be kept in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Create mock CLoad + mock_cload = MagicMock(spec=cinst.CLoad) + mock_cload.var_name = "new_var" + mock_cload.spad_address = 10 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cload] + mock_kernel.cinstrs_map = [MagicMock()] + + self.program.prune_cinst_kernel_no_hbm(mock_kernel) + + # Variable should be added to tracker + self.assertEqual(self.program._cinst_in_var_tracker["new_var"], 10) + + def test_prune_cinst_kernel_no_hbm_bones_already_loaded(self): + """@brief Test BOnes handling when variable already loaded in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Set up variable tracker + self.program._cinst_in_var_tracker = {"loaded_var": 5} + + # Create mock BOnes + mock_bones = MagicMock(spec=cinst.BOnes) + mock_bones.var_name = "loaded_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_bones] + mock_kernel.cinstrs_map = [MagicMock()] + + with patch("linker.steps.program_linker_utils.calculate_instruction_latency_adjustment", return_value=2): + self.program.prune_cinst_kernel_no_hbm(mock_kernel) + + # BOnes should be marked as SKIP + self.assertEqual(mock_kernel.cinstrs_map[0].action, InstrAct.SKIP) + + def test_prune_cinst_kernel_no_hbm_cstore_intermediate_var(self): + """@brief Test CStore handling with intermediate variable in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Set up intermediate variables + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock CStore + mock_cstore = MagicMock(spec=cinst.CStore) + mock_cstore.var_name = "intermediate_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cstore] + mock_kernel.cinstrs_map = [MagicMock()] + + self.program.prune_cinst_kernel_no_hbm(mock_kernel) + + # CStore should be marked as SKIP + self.assertEqual(mock_kernel.cinstrs_map[0].action, InstrAct.SKIP) + + def test_prune_cinst_kernel_no_hbm_cstore_with_spad_boundary(self): + """@brief Test CStore with intermediate variable but keep_spad_boundary=True in no-HBM mode.""" + with patch.object(GlobalConfig, "hasHBM", False): + # Create program with keep_spad_boundary=True + program = LinkedProgram(keep_spad_boundary=True) + program.initialize( + self.streams["minst"], + self.streams["cinst"], + self.streams["xinst"], + self.mem_model, + ) + program._intermediate_vars = ["intermediate_var"] + + # Create mock CStore + mock_cstore = MagicMock(spec=cinst.CStore) + mock_cstore.var_name = "intermediate_var" + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.cinstrs = [mock_cstore] + mock_kernel.cinstrs_map = [MagicMock()] + + program.prune_cinst_kernel_no_hbm(mock_kernel) + + # CStore should NOT be marked as SKIP due to keep_spad_boundary + self.assertNotEqual(mock_kernel.cinstrs_map[0].action, InstrAct.SKIP) + + +class TestPruneMinstKernel(unittest.TestCase): + """@brief Tests for the prune_minst_kernel method.""" + + def setUp(self): + """@brief Set up test fixtures.""" + self.streams = { + "minst": io.StringIO(), + "cinst": io.StringIO(), + "xinst": io.StringIO(), + } + self.mem_model = MagicMock(spec=MemoryModel) + + # Mock the hasHBM property to return True by default + self.has_hbm_patcher = patch.object(GlobalConfig, "hasHBM", True) + self.mock_has_hbm = self.has_hbm_patcher.start() + + self.program = LinkedProgram() + self.program.initialize( + self.streams["minst"], + self.streams["cinst"], + self.streams["xinst"], + self.mem_model, + ) + + def tearDown(self): + """@brief Tear down test fixtures.""" + self.has_hbm_patcher.stop() + + def test_prune_minst_kernel_with_keep_hbm_boundary(self): + """@brief Test that prune_minst_kernel returns early when keep_hbm_boundary is True.""" + # Set keep_hbm_boundary to True + program = LinkedProgram(keep_hbm_boundary=True) + program.initialize( + self.streams["minst"], + self.streams["cinst"], + self.streams["xinst"], + self.mem_model, + ) + + mock_kernel = MagicMock() + mock_kernel.minstrs = [MagicMock()] + + # Should return early without processing + program.prune_minst_kernel(mock_kernel) + + # No changes should be made to the kernel + self.assertIsNotNone(mock_kernel.minstrs) + + def test_prune_minst_kernel_msyncc_tracking(self): + """@brief Test that MSyncc instructions are tracked correctly.""" + # Create mock MSyncc instruction + mock_msyncc = MagicMock(spec=minst.MSyncc) + mock_msyncc.idx = 0 + + mock_mload = MagicMock(spec=minst.MLoad) + mock_mload.var_name = "test_var" + mock_mload.spad_address = 10 + mock_mload.idx = 1 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_msyncc, mock_mload] + mock_kernel.minstrs_map = [MagicMock(), MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # MSyncc should be tracked but not modified + self.assertIsNotNone(mock_msyncc) + + def test_prune_minst_kernel_mstore_intermediate_var(self): + """@brief Test MStore handling with intermediate variable.""" + # Set up intermediate variables + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock MStore + mock_mstore = MagicMock(spec=minst.MStore) + mock_mstore.var_name = "intermediate_var" + mock_mstore.spad_address = 20 + mock_mstore.idx = 0 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mstore] + mock_kernel.minstrs_map = [MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # MStore should be marked as SKIP (since keep_spad_boundary is False by default) + self.assertEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) + + def test_prune_minst_kernel_mstore_intermediate_var_with_spad_boundary(self): + """@brief Test MStore with intermediate variable but keep_spad_boundary=True.""" + # Create program with keep_spad_boundary=True + program = LinkedProgram(keep_spad_boundary=True) + program.initialize( + self.streams["minst"], + self.streams["cinst"], + self.streams["xinst"], + self.mem_model, + ) + program._intermediate_vars = ["intermediate_var"] + + # Create mock MStore + mock_mstore = MagicMock(spec=minst.MStore) + mock_mstore.var_name = "intermediate_var" + mock_mstore.spad_address = 20 + mock_mstore.idx = 0 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mstore] + mock_kernel.minstrs_map = [MagicMock()] + mock_kernel.spad_size = 0 + + program.prune_minst_kernel(mock_kernel) + + # MStore should be marked as KEEP_SPAD due to keep_spad_boundary + self.assertEqual(mock_kernel.minstrs_map[0].action, InstrAct.KEEP_SPAD) + + def test_prune_minst_kernel_mstore_with_preceding_msyncc(self): + """@brief Test MStore intermediate variable with preceding MSyncc removal.""" + # Set up intermediate variables + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock MSyncc and MStore + mock_msyncc = MagicMock(spec=minst.MSyncc) + mock_msyncc.idx = 0 + + mock_mstore = MagicMock(spec=minst.MStore) + mock_mstore.var_name = "intermediate_var" + mock_mstore.spad_address = 15 + mock_mstore.idx = 1 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_msyncc, mock_mstore] + mock_kernel.minstrs_map = [MagicMock(), MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # Both MSyncc and MStore should be marked as SKIP + self.assertEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) # MSyncc + self.assertEqual(mock_kernel.minstrs_map[1].action, InstrAct.SKIP) # MStore + + def test_prune_minst_kernel_mstore_keep_instruction(self): + """@brief Test MStore when instruction should be kept.""" + # Create mock MStore with non-intermediate variable + mock_mstore = MagicMock(spec=minst.MStore) + mock_mstore.var_name = "output_var" + mock_mstore.spad_address = 20 + mock_mstore.idx = 0 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mstore] + mock_kernel.minstrs_map = [MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # MStore should not be marked as SKIP + self.assertNotEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) + # SPAD address should be adjusted (starts at 0, no adjustment needed) + self.assertEqual(mock_mstore.spad_address, 20) + + def test_prune_minst_kernel_mload_already_loaded(self): + """@brief Test MLoad handling when variable already loaded.""" + # Set up variable tracker + self.program._minst_in_var_tracker = {"loaded_var": 5} + + # Create mock MLoad + mock_mload = MagicMock(spec=minst.MLoad) + mock_mload.var_name = "loaded_var" + mock_mload.spad_address = 10 + mock_mload.idx = 0 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mload] + mock_kernel.minstrs_map = [MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # MLoad should be marked as SKIP + self.assertEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) + # SPAD address should be updated to tracked address + self.assertEqual(mock_mload.spad_address, 5) + + def test_prune_minst_kernel_mload_intermediate_var(self): + """@brief Test MLoad handling with intermediate variable.""" + # Set up intermediate variables + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock MLoad + mock_mload = MagicMock(spec=minst.MLoad) + mock_mload.var_name = "intermediate_var" + mock_mload.spad_address = 10 + mock_mload.idx = 0 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mload] + mock_kernel.minstrs_map = [MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # MLoad should be marked as SKIP (since keep_spad_boundary is False by default) + self.assertEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) + + def test_prune_minst_kernel_mload_intermediate_var_with_spad_boundary(self): + """@brief Test MLoad with intermediate variable but keep_spad_boundary=True.""" + # Create program with keep_spad_boundary=True + program = LinkedProgram(keep_spad_boundary=True) + program.initialize( + self.streams["minst"], + self.streams["cinst"], + self.streams["xinst"], + self.mem_model, + ) + program._intermediate_vars = ["intermediate_var"] + + # Create mock MLoad + mock_mload = MagicMock(spec=minst.MLoad) + mock_mload.var_name = "intermediate_var" + mock_mload.spad_address = 10 + mock_mload.idx = 0 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mload] + mock_kernel.minstrs_map = [MagicMock()] + mock_kernel.spad_size = 0 + + program.prune_minst_kernel(mock_kernel) + + # MLoad should be marked as KEEP_SPAD due to keep_spad_boundary + self.assertEqual(mock_kernel.minstrs_map[0].action, InstrAct.KEEP_SPAD) + + def test_prune_minst_kernel_mload_keep_instruction(self): + """@brief Test MLoad when instruction should be kept.""" + # Create mock MLoad with new variable + mock_mload = MagicMock(spec=minst.MLoad) + mock_mload.var_name = "new_var" + mock_mload.spad_address = 10 + mock_mload.idx = 0 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mload] + mock_kernel.minstrs_map = [MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # MLoad should not be marked as SKIP + self.assertNotEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) + # Variable should be added to tracker + self.assertEqual(self.program._minst_in_var_tracker["new_var"], 10) + + def test_prune_minst_kernel_mixed_instructions(self): + """@brief Test processing multiple mixed instruction types.""" + # Set up trackers and intermediate variables + self.program._minst_in_var_tracker = {"already_loaded": 5} + self.program._intermediate_vars = ["intermediate_var"] + + # Create mock instructions + mock_msyncc = MagicMock(spec=minst.MSyncc) + mock_msyncc.idx = 0 + + mock_mload1 = MagicMock(spec=minst.MLoad) # Already loaded + mock_mload1.var_name = "already_loaded" + mock_mload1.spad_address = 10 + mock_mload1.idx = 1 + + mock_mstore = MagicMock(spec=minst.MStore) # Intermediate variable + mock_mstore.var_name = "intermediate_var" + mock_mstore.spad_address = 15 + mock_mstore.idx = 2 + + mock_mload2 = MagicMock(spec=minst.MLoad) # New variable + mock_mload2.var_name = "new_var" + mock_mload2.spad_address = 20 + mock_mload2.idx = 3 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_msyncc, mock_mload1, mock_mstore, mock_mload2] + mock_kernel.minstrs_map = [MagicMock(), MagicMock(), MagicMock(), MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # Check actions + self.assertNotEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) # MSyncc (no action change) + self.assertEqual(mock_kernel.minstrs_map[1].action, InstrAct.SKIP) # MLoad1 (already loaded) + self.assertEqual(mock_kernel.minstrs_map[2].action, InstrAct.SKIP) # MStore (intermediate) + self.assertNotEqual(mock_kernel.minstrs_map[3].action, InstrAct.SKIP) # MLoad2 (new var) + + # Check variable tracking + self.assertEqual(self.program._minst_in_var_tracker["new_var"], 18) # 20 - 2 (adjust_spad) + + def test_prune_minst_kernel_spad_size_tracking(self): + """@brief Test that SPAD size is correctly tracked and updated.""" + # Create mock instructions with different SPAD addresses + mock_mload1 = MagicMock(spec=minst.MLoad) + mock_mload1.var_name = "var1" + mock_mload1.spad_address = 10 + mock_mload1.idx = 0 + + mock_mstore = MagicMock(spec=minst.MStore) + mock_mstore.var_name = "var2" + mock_mstore.spad_address = 25 + mock_mstore.idx = 1 + + mock_mload2 = MagicMock(spec=minst.MLoad) + mock_mload2.var_name = "var3" + mock_mload2.spad_address = 15 + mock_mload2.idx = 2 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mload1, mock_mstore, mock_mload2] + mock_kernel.minstrs_map = [MagicMock(), MagicMock(), MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # SPAD size should be the maximum SPAD address encountered + self.assertEqual(mock_kernel.spad_size, 25) + + def test_prune_minst_kernel_adjustment_calculations(self): + """@brief Test that SPAD address adjustments are calculated correctly.""" + # Set up intermediate variables to cause adjustments + self.program._intermediate_vars = ["intermediate_var1", "intermediate_var2"] + + # Create mock instructions that will cause adjustments + mock_mload1 = MagicMock(spec=minst.MLoad) # Intermediate - will be skipped + mock_mload1.var_name = "intermediate_var1" + mock_mload1.spad_address = 10 + mock_mload1.idx = 0 + + mock_mstore = MagicMock(spec=minst.MStore) # Intermediate - will be skipped + mock_mstore.var_name = "intermediate_var2" + mock_mstore.spad_address = 15 + mock_mstore.idx = 1 + + mock_mload2 = MagicMock(spec=minst.MLoad) # Regular - should be adjusted + mock_mload2.var_name = "regular_var" + mock_mload2.spad_address = 20 + mock_mload2.idx = 2 + + # Create mock kernel + mock_kernel = MagicMock() + mock_kernel.minstrs = [mock_mload1, mock_mstore, mock_mload2] + mock_kernel.minstrs_map = [MagicMock(), MagicMock(), MagicMock()] + mock_kernel.spad_size = 0 + + self.program.prune_minst_kernel(mock_kernel) + + # First two instructions should be skipped + self.assertEqual(mock_kernel.minstrs_map[0].action, InstrAct.SKIP) + self.assertEqual(mock_kernel.minstrs_map[1].action, InstrAct.SKIP) + + # Third instruction should have adjusted SPAD address + # adjust_spad should be -2 (from two skipped instructions) + expected_spad = 20 - 2 # Original 20, minus 2 for adjustments + self.assertEqual(mock_mload2.spad_address, expected_spad) + + # Variable should be tracked with adjusted address + self.assertEqual(self.program._minst_in_var_tracker["regular_var"], expected_spad) + + if __name__ == "__main__": unittest.main() diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker_utils.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker_utils.py new file mode 100644 index 00000000..6e8b78a5 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker_utils.py @@ -0,0 +1,396 @@ +# Copyright (C) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +# These contents may have been developed with support from one or more Intel-operated +# generative artificial intelligence solutions + +""" +@brief Unit tests for the program_linker_utils module. +""" + +from unittest.mock import MagicMock, patch + +import pytest +from linker.instructions import cinst, minst +from linker.kern_trace.kernel_info import InstrAct +from linker.steps.program_linker_utils import ( + calculate_instruction_latency_adjustment, + process_bload_instructions, + remove_csyncm, + search_minstrs_back, + search_minstrs_forward, +) + + +class TestCalculateInstructionLatencyAdjustment: + """@brief Tests for calculate_instruction_latency_adjustment function.""" + + @patch("assembler.instructions.cinst.CLoad.get_latency", return_value=5) + def test_cload_latency(self, mock_get_latency): + """@brief Test latency calculation for CLoad instruction.""" + mock_cload = MagicMock(spec=cinst.CLoad) + + result = calculate_instruction_latency_adjustment(mock_cload) + + assert result == 5 + mock_get_latency.assert_called_once() + + @patch("assembler.instructions.cinst.BLoad.get_latency", return_value=3) + def test_bload_latency(self, mock_get_latency): + """@brief Test latency calculation for BLoad instruction.""" + mock_bload = MagicMock(spec=cinst.BLoad) + + result = calculate_instruction_latency_adjustment(mock_bload) + + assert result == 3 + mock_get_latency.assert_called_once() + + @patch("assembler.instructions.cinst.BOnes.get_latency", return_value=2) + def test_bones_latency(self, mock_get_latency): + """@brief Test latency calculation for BOnes instruction.""" + mock_bones = MagicMock(spec=cinst.BOnes) + + result = calculate_instruction_latency_adjustment(mock_bones) + + assert result == 2 + mock_get_latency.assert_called_once() + + def test_unknown_instruction_latency(self): + """@brief Test latency calculation for unknown instruction type.""" + mock_unknown = MagicMock() + + result = calculate_instruction_latency_adjustment(mock_unknown) + + assert result == 0 + + def test_none_instruction(self): + """@brief Test latency calculation for None instruction.""" + result = calculate_instruction_latency_adjustment(None) + + assert result == 0 + + +class TestProcessBloadInstructions: + """@brief Tests for process_bload_instructions function.""" + + def test_process_single_bload_not_in_tracker(self): + """@brief Test processing single BLoad not in tracker.""" + mock_bload = MagicMock(spec=cinst.BLoad) + mock_bload.var_name = "var1" + + kernel_cinstrs = [mock_bload] + + mock_map_entry = MagicMock() + kernel_cinstrs_map = [mock_map_entry] + + cinst_in_var_tracker = {} + + result = process_bload_instructions(kernel_cinstrs, kernel_cinstrs_map, cinst_in_var_tracker, 0) + + assert result == 0 # idx - 1 + # Action should not be modified since var not in tracker + assert mock_map_entry.action != InstrAct.SKIP + + def test_process_single_bload_in_tracker(self): + """@brief Test processing single BLoad in tracker.""" + mock_bload = MagicMock(spec=cinst.BLoad) + mock_bload.var_name = "var1" + + kernel_cinstrs = [mock_bload] + + mock_map_entry = MagicMock() + kernel_cinstrs_map = [mock_map_entry] + + cinst_in_var_tracker = {"var1": 0} + + result = process_bload_instructions(kernel_cinstrs, kernel_cinstrs_map, cinst_in_var_tracker, 0) + + assert result == 0 # idx - 1 + assert mock_map_entry.action == InstrAct.SKIP + + def test_process_multiple_bload_instructions(self): + """@brief Test processing multiple consecutive BLoad instructions.""" + mock_bload1 = MagicMock(spec=cinst.BLoad) + mock_bload1.var_name = "var1" + + mock_bload2 = MagicMock(spec=cinst.BLoad) + mock_bload2.var_name = "var2" + + mock_bload3 = MagicMock(spec=cinst.BLoad) + mock_bload3.var_name = "var3" + + kernel_cinstrs = [mock_bload1, mock_bload2, mock_bload3] + + mock_map_entries = [MagicMock(), MagicMock(), MagicMock()] + kernel_cinstrs_map = mock_map_entries + + cinst_in_var_tracker = {"var2": 1} # Only var2 is tracked + + result = process_bload_instructions(kernel_cinstrs, kernel_cinstrs_map, cinst_in_var_tracker, 0) + + assert result == 2 # 3 - 1 + # Only var2 should be marked as SKIP + assert mock_map_entries[1].action == InstrAct.SKIP + assert mock_map_entries[0].action != InstrAct.SKIP + assert mock_map_entries[2].action != InstrAct.SKIP + + def test_process_bload_mixed_with_other_instructions(self): + """@brief Test processing BLoad when followed by non-BLoad instruction.""" + mock_bload = MagicMock(spec=cinst.BLoad) + mock_bload.var_name = "var1" + + mock_cload = MagicMock(spec=cinst.CLoad) + + kernel_cinstrs = [mock_bload, mock_cload] + + mock_map_entries = [MagicMock(), MagicMock()] + kernel_cinstrs_map = mock_map_entries + + cinst_in_var_tracker = {} + + result = process_bload_instructions(kernel_cinstrs, kernel_cinstrs_map, cinst_in_var_tracker, 0) + + assert result == 0 # Stopped at first non-BLoad, so 1 - 1 = 0 + + +class TestRemoveCsyncm: + """@brief Tests for remove_csyncm function.""" + + @patch("assembler.instructions.cinst.CSyncm.get_throughput", return_value=4) + def test_remove_valid_csyncm(self, mock_get_throughput): + """@brief Test removing valid CSyncm instruction.""" + mock_csyncm = MagicMock(spec=cinst.CSyncm) + + kernel_cinstrs = [mock_csyncm] + + mock_map_entry = MagicMock() + kernel_cinstrs_map = [mock_map_entry] + + adjust_idx, adjust_cycles = remove_csyncm(kernel_cinstrs, kernel_cinstrs_map, 0) + + assert adjust_idx == -1 + assert adjust_cycles == 4 + assert mock_map_entry.action == InstrAct.SKIP + mock_get_throughput.assert_called_once() + + def test_remove_non_csyncm_instruction(self): + """@brief Test attempting to remove non-CSyncm instruction.""" + mock_cload = MagicMock(spec=cinst.CLoad) + + kernel_cinstrs = [mock_cload] + + mock_map_entry = MagicMock() + kernel_cinstrs_map = [mock_map_entry] + + adjust_idx, adjust_cycles = remove_csyncm(kernel_cinstrs, kernel_cinstrs_map, 0) + + assert adjust_idx == 0 + assert adjust_cycles == 0 + assert mock_map_entry.action != InstrAct.SKIP + + def test_remove_csyncm_invalid_index_negative(self): + """@brief Test removing CSyncm with negative index.""" + kernel_cinstrs = [] + kernel_cinstrs_map = [] + + adjust_idx, adjust_cycles = remove_csyncm(kernel_cinstrs, kernel_cinstrs_map, -1) + + assert adjust_idx == 0 + assert adjust_cycles == 0 + + def test_remove_csyncm_invalid_index_too_large(self): + """@brief Test removing CSyncm with index larger than list.""" + mock_cload = MagicMock(spec=cinst.CLoad) + + kernel_cinstrs = [mock_cload] + kernel_cinstrs_map = [MagicMock()] + + adjust_idx, adjust_cycles = remove_csyncm(kernel_cinstrs, kernel_cinstrs_map, 5) + + assert adjust_idx == 0 + assert adjust_cycles == 0 + + def test_remove_csyncm_empty_lists(self): + """@brief Test removing CSyncm from empty lists.""" + adjust_idx, adjust_cycles = remove_csyncm([], [], 0) + + assert adjust_idx == 0 + assert adjust_cycles == 0 + + +class TestSearchMinstrsBack: + """@brief Tests for search_minstrs_back function.""" + + def test_search_minstrs_back_found(self): + """@brief Test searching backwards and finding MLoad.""" + mock_mload = MagicMock(spec=minst.MLoad) + mock_msyncc = MagicMock(spec=minst.MSyncc) + + mock_entry1 = MagicMock() + mock_entry1.minstr = mock_msyncc + mock_entry1.spad_addr = -1 + + mock_entry2 = MagicMock() + mock_entry2.minstr = mock_mload + mock_entry2.spad_addr = 10 + + minstrs_map = [mock_entry1, mock_entry2] + + result = search_minstrs_back(minstrs_map, 1, 10) + + assert result == 1 + + def test_search_minstrs_back_found_earlier_index(self): + """@brief Test searching backwards and finding MLoad at earlier index.""" + mock_mload1 = MagicMock(spec=minst.MLoad) + mock_mload2 = MagicMock(spec=minst.MLoad) + mock_mstore = MagicMock(spec=minst.MStore) + + mock_entry1 = MagicMock() + mock_entry1.minstr = mock_mload1 + mock_entry1.spad_addr = 5 + + mock_entry2 = MagicMock() + mock_entry2.minstr = mock_mload2 + mock_entry2.spad_addr = 10 + + mock_entry3 = MagicMock() + mock_entry3.minstr = mock_mstore + mock_entry3.spad_addr = 15 + + minstrs_map = [mock_entry1, mock_entry2, mock_entry3] + + result = search_minstrs_back(minstrs_map, 2, 5) + + assert result == 0 + + def test_search_minstrs_back_not_found(self): + """@brief Test searching backwards when MLoad not found.""" + mock_mstore = MagicMock(spec=minst.MStore) + + mock_entry = MagicMock() + mock_entry.minstr = mock_mstore + mock_entry.spad_addr = 10 + + minstrs_map = [mock_entry] + + with pytest.raises(RuntimeError, match="Could not find MLoad with SPAD address 20"): + search_minstrs_back(minstrs_map, 0, 20) + + def test_search_minstrs_back_wrong_spad_address(self): + """@brief Test searching backwards with wrong SPAD address.""" + mock_mload = MagicMock(spec=minst.MLoad) + + mock_entry = MagicMock() + mock_entry.minstr = mock_mload + mock_entry.spad_addr = 5 + + minstrs_map = [mock_entry] + + with pytest.raises(RuntimeError, match="Could not find MLoad with SPAD address 10"): + search_minstrs_back(minstrs_map, 0, 10) + + def test_search_minstrs_back_empty_map(self): + """@brief Test searching backwards in empty map.""" + with pytest.raises(IndexError, match="Index 0 is out of bounds for minstrs_map"): + search_minstrs_back([], 0, 10) + + +class TestSearchMinstrsForward: + """@brief Tests for search_minstrs_forward function.""" + + def test_search_minstrs_forward_found_mstore(self): + """@brief Test searching forward and finding MStore.""" + mock_mload = MagicMock(spec=minst.MLoad) + mock_mstore = MagicMock(spec=minst.MStore) + + mock_entry1 = MagicMock() + mock_entry1.minstr = mock_mload + mock_entry1.spad_addr = 5 + + mock_entry2 = MagicMock() + mock_entry2.minstr = mock_mstore + mock_entry2.spad_addr = 10 + + minstrs_map = [mock_entry1, mock_entry2] + + result = search_minstrs_forward(minstrs_map, 0, 10) + + assert result == 1 + + def test_search_minstrs_forward_found_mload(self): + """@brief Test searching forward and finding MLoad.""" + mock_mload1 = MagicMock(spec=minst.MLoad) + mock_mload2 = MagicMock(spec=minst.MLoad) + + mock_entry1 = MagicMock() + mock_entry1.minstr = mock_mload1 + mock_entry1.spad_addr = 5 + + mock_entry2 = MagicMock() + mock_entry2.minstr = mock_mload2 + mock_entry2.spad_addr = 10 + + minstrs_map = [mock_entry1, mock_entry2] + + result = search_minstrs_forward(minstrs_map, 0, 10) + + assert result == 1 + + def test_search_minstrs_forward_found_at_start_index(self): + """@brief Test searching forward and finding at start index.""" + mock_mstore = MagicMock(spec=minst.MStore) + + mock_entry = MagicMock() + mock_entry.minstr = mock_mstore + mock_entry.spad_addr = 10 + + minstrs_map = [mock_entry] + + result = search_minstrs_forward(minstrs_map, 0, 10) + + assert result == 0 + + def test_search_minstrs_forward_not_found(self): + """@brief Test searching forward when instruction not found.""" + mock_msyncc = MagicMock(spec=minst.MSyncc) + + mock_entry = MagicMock() + mock_entry.minstr = mock_msyncc + mock_entry.spad_addr = -1 + + minstrs_map = [mock_entry] + + with pytest.raises(RuntimeError, match="Could not find MStore with SPAD address 10"): + search_minstrs_forward(minstrs_map, 0, 10) + + def test_search_minstrs_forward_wrong_spad_address(self): + """@brief Test searching forward with wrong SPAD address.""" + mock_mstore = MagicMock(spec=minst.MStore) + + mock_entry = MagicMock() + mock_entry.minstr = mock_mstore + mock_entry.spad_addr = 5 + + minstrs_map = [mock_entry] + + with pytest.raises(RuntimeError, match="Could not find MStore with SPAD address 10"): + search_minstrs_forward(minstrs_map, 0, 10) + + def test_search_minstrs_forward_start_beyond_range(self): + """@brief Test searching forward starting beyond map range.""" + mock_mstore = MagicMock(spec=minst.MStore) + + mock_entry = MagicMock() + mock_entry.minstr = mock_mstore + mock_entry.spad_addr = 10 + + minstrs_map = [mock_entry] + + with pytest.raises(RuntimeError, match="Could not find MStore with SPAD address 10"): + search_minstrs_forward(minstrs_map, 5, 10) + + def test_search_minstrs_forward_empty_map(self): + """@brief Test searching forward in empty map.""" + with pytest.raises(RuntimeError, match="Could not find MStore with SPAD address 10"): + search_minstrs_forward([], 0, 10) From 1309f62030f14838287a0d127bf82fd828c18544 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Tue, 19 Aug 2025 18:08:44 +0000 Subject: [PATCH 05/12] Adding integration tests --- .../linker/steps/program_linker.py | 38 +- .../tests/integration_tests/test_he_link.py | 735 +++++++++++++++--- .../test_steps/test_program_linker.py | 23 +- 3 files changed, 683 insertions(+), 113 deletions(-) diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py index 42cb3a31..d1f7d40c 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py @@ -234,6 +234,7 @@ def _update_minsts(self, kernel: KernelInfo): # Update msyncc if isinstance(minstr, minst.MSyncc): + # If not the last MSyncc if idx < len(kernel.minstrs) - 1: # Update msyncc target to new cinst and global program offset minstr.target = kernel.cinstrs_map[minstr.target].cinstr.idx @@ -369,7 +370,7 @@ def _update_cinsts_addresses_and_offsets(self, kernel_cinstrs: list): if self.__mem_model is None: raise RuntimeError("Memory model is not initialized.") - for cinstr in kernel_cinstrs: + for i, cinstr in enumerate(kernel_cinstrs): # Update ifetch if isinstance(cinstr, cinst.IFetch): cinstr.bundle = cinstr.bundle + self._bundle_offset @@ -378,7 +379,8 @@ def _update_cinsts_addresses_and_offsets(self, kernel_cinstrs: list): raise NotImplementedError("`xinstfetch` not currently supported by linker.") # Update csyncm if isinstance(cinstr, cinst.CSyncm): - if cinstr.target > 4 or self._keep_hbm_boundary: + # If not a NLoad CSyncm or not keeping HBM boundary, update target + if i + 1 < len(kernel_cinstrs) and not isinstance(kernel_cinstrs[i + 1], cinst.NLoad) or self._keep_hbm_boundary: cinstr.target = cinstr.target + self._minst_line_offset if not GlobalConfig.hasHBM: @@ -403,6 +405,10 @@ def _update_cinst_kernel_hbm(self, kernel: KernelInfo): @param kernel (KernelInfo): The kernel to update. """ + # Nothing to update in cinst if we are keeping the HBM boundary + if self._keep_hbm_boundary: + return + idx: int = 0 syncm_idx = 0 while idx < len(kernel.cinstrs): @@ -544,7 +550,7 @@ def link_kernel(self, kernel: KernelInfo): print(f" #{minstr.comment}", end="", file=self._minst_ostream) print(file=self._minst_ostream) - self._minst_line_offset += len(minstrs_list) - 1 # Subtract last line that is getting removed + self._minst_line_offset += (len(minstrs_list) - 1) if minstrs_list else 0 # Subtract last line that is getting removed self._cinst_line_offset += len(cinstrs_list) - 1 # Subtract last line that is getting removed self._kernel_count += 1 # Count the appended kernel @@ -625,6 +631,7 @@ def prune_minst_kernel(self, kernel_info: KernelInfo): last_msyncc = None for idx, minstr in enumerate(kernel_info.minstrs): + print(f"ROCHA ({idx}): PRUNE MINST -> {minstr.to_line()} # {minstr.comment}") if isinstance(minstr, minst.MSyncc): last_msyncc = minstr elif isinstance(minstr, minst.MStore): @@ -645,14 +652,24 @@ def prune_minst_kernel(self, kernel_info: KernelInfo): adjust_spad -= 1 adjust_idx -= 1 + # Keep instruction else: + # Calculate new SPAD Address + new_spad = minstr.spad_address + adjust_spad + # Adjust spad address if negative, this could leave gaps in the spad address space + if new_spad < 0: + adjust_spad -= new_spad + new_spad = 0 + minstr.idx = minstr.idx + adjust_idx # Update line number minstr.spad_address += adjust_spad # Adjust source spad address spad_size = minstr.spad_address + print(f"ROCHA ({idx}): PRUNE MINST -> Keeping {minstr.var_name} MStore - SPAD address {minstr.spad_address}") elif isinstance(minstr, minst.MLoad): # Remove mload instructions if variables already loaded if minstr.var_name in self._minst_in_var_tracker: + print(f"ROCHA ({idx}): PRUNE MINST -> Removing MLoad - already loaded {minstr.var_name}") kernel_info.minstrs_map[idx].action = InstrAct.SKIP minstr.spad_address = self._minst_in_var_tracker[minstr.var_name] # Adjust dest spad address adjust_spad -= 1 @@ -666,10 +683,18 @@ def prune_minst_kernel(self, kernel_info: KernelInfo): adjust_idx -= 1 continue + # Calculate new SPAD Address + new_spad = minstr.spad_address + adjust_spad + # Adjust spad address if negative, this could leave gaps in the spad address space + if new_spad < 0: + adjust_spad -= new_spad + new_spad = 0 + # Keep instruction - minstr.spad_address += adjust_spad # Adjust dest spad address + minstr.spad_address = new_spad # Adjust dest spad address minstr.idx = minstr.idx + adjust_idx # Update line number spad_size = minstr.spad_address + print(f"ROCHA ({idx}): PRUNE MINST -> Keeping {minstr.var_name} MLoad - SPAD address {minstr.spad_address}") # Track loaded variables self._minst_in_var_tracker[minstr.var_name] = minstr.spad_address @@ -681,6 +706,10 @@ def prune_cinst_kernel_hbm(self, kernel: KernelInfo): """ @brief Prunes and updates CInsts for HBM mode, handling synchronization and address mapping. """ + # Nothing to prune in cinst if we are keeping the HBM boundary + if self._keep_hbm_boundary: + return + adjust_idx: int = 0 # Used to adjust the index when removing CInsts adjust_cycles: int = 0 @@ -735,6 +764,7 @@ def prune_cinst_kernel_hbm(self, kernel: KernelInfo): # Check if the variable is an intermediate variable if cinstr.var_name in self._intermediate_vars: # CSyncm no needed for intermediate variables + print(f"ROCHA ({idx}): PRUNE CINST -> Removing intermediate {cinstr.var_name} CStore") _idx, _cycles = remove_csyncm(kernel.cinstrs, kernel.cinstrs_map, idx + 1) adjust_idx += _idx adjust_cycles += _cycles diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py index b4da3eaf..5104e3dd 100644 --- a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py @@ -8,14 +8,15 @@ @file test_he_link.py @brief Integration tests for the he_link module """ -import tempfile + import shutil +import tempfile from pathlib import Path -import pytest import he_link -from linker.linker_run_config import LinkerRunConfig +import pytest from linker.kern_trace.trace_info import TraceInfo +from linker.linker_run_config import LinkerRunConfig class TestHeIntegration: @@ -83,9 +84,7 @@ def test_run_he_link_on_single_op_hbm(self, temp_dir, fixture_dir, input_prefix) in_file = input_dir / f"{input_prefix}{ext}" assert out_file.exists() assert in_file.exists() - with open(out_file, "r", encoding="utf-8") as fout, open( - in_file, "r", encoding="utf-8" - ) as fin: + with open(out_file, encoding="utf-8") as fout, open(in_file, encoding="utf-8") as fin: assert sum(1 for _ in fout) == sum(1 for _ in fin) @pytest.mark.parametrize( @@ -99,9 +98,7 @@ def test_run_he_link_on_single_op_no_hbm(self, temp_dir, fixture_dir, input_pref """ @brief Test he_link.py with .cinst/.minst/.xinst input files from linking_fixtures """ - fixtures_root = ( - Path(__file__).parent / "linking_fixtures" / fixture_dir / "no_hbm" - ) + fixtures_root = Path(__file__).parent / "linking_fixtures" / fixture_dir / "no_hbm" input_files = { "minst": fixtures_root / f"{input_prefix}.minst", "cinst": fixtures_root / f"{input_prefix}.cinst", @@ -138,24 +135,20 @@ def test_run_he_link_on_single_op_no_hbm(self, temp_dir, fixture_dir, input_pref out_file = output_dir / f"{cfg_kwargs['output_prefix']}.xinst" assert out_file.exists() assert input_files["xinst"].exists() - with open(out_file, "r", encoding="utf-8") as fout, open( - input_files["xinst"], "r", encoding="utf-8" - ) as fin: + with open(out_file, encoding="utf-8") as fout, open(input_files["xinst"], encoding="utf-8") as fin: assert sum(1 for _ in fout) == sum(1 for _ in fin) # Assert no csyncm instructions in cinst output file out_file = output_dir / f"{cfg_kwargs['output_prefix']}.cinst" assert out_file.exists() - with open(out_file, "r", encoding="utf-8") as f: + with open(out_file, encoding="utf-8") as f: content = f.read() - assert ( - "csyncm" not in content - ), "Found csyncm instruction in cinst output file" + assert "csyncm" not in content, "Found csyncm instruction in cinst output file" # Assert minst is one line out_file = output_dir / f"{cfg_kwargs['output_prefix']}.minst" assert out_file.exists() - with open(out_file, "r", encoding="utf-8") as f: + with open(out_file, encoding="utf-8") as f: content = f.read() assert content.count("\n") == 1, "Expected minst output to be a single line" @@ -175,52 +168,147 @@ def _extract_trace_vars(self, kernel_ops): intermediate_vars = input_vars & output_vars return overall_input_vars, overall_output_vars, intermediate_vars - def _parse_mem_file(self, mem_file): + def _parse_n_test_mem_file(self, mem_file): """ Helper to parse mem file and return dload/dstore vars and labels. Also checks address uniqueness/consecutiveness and duplicates. """ assert mem_file.exists() - with open(mem_file, "r", encoding="utf-8") as f: + with open(mem_file, encoding="utf-8") as f: split_lines = f.read().splitlines() dload_vars, dload_var_labels = [], set() dstore_vars, dstore_var_labels = [], set() for idx, line in enumerate(split_lines): - tokenized_line = line.split(",") - if line.startswith("dload"): - var_name = tokenized_line[3].strip() + tokens = line.split(",") + if tokens[0].startswith("dload"): + var_name = tokens[3].strip() dload_vars.append(var_name) if var_name.startswith("ct") or var_name.startswith("pt"): dload_var_labels.add(var_name.split("_")[0]) - if line.startswith("dstore"): - var_name = tokenized_line[1].strip() + if tokens[0].startswith("dstore"): + var_name = tokens[1].strip() dstore_vars.append(var_name) if var_name.startswith("ct") or var_name.startswith("pt"): dstore_var_labels.add(var_name.split("_")[0]) + + # Assert addresses are digits + assert tokens[2].strip().isdigit(), f"Expected address {tokens[2]} to be digit in line: {line}" # Assert addresses are unique and consecutive - assert idx == int( - tokenized_line[2] - ), f"Expected address {idx + 1} but found {tokenized_line[2]} in line: {line}" - assert len(dload_vars) == len( - set(dload_vars) - ), "Found duplicate dload variables in mem file" - assert len(dstore_vars) == len( - set(dstore_vars) - ), "Found duplicate dstore variables in mem file" + assert idx == int(tokens[2]), f"Expected address {idx + 1} but found {tokens[2]} in line: {line}" + + # Assert no duplicates in dload/dstore vars + assert len(dload_vars) == len(set(dload_vars)), "Found duplicate dload variables in mem file" + assert len(dstore_vars) == len(set(dstore_vars)), "Found duplicate dstore variables in mem file" + return dload_var_labels, dstore_var_labels - @pytest.mark.parametrize( - "fixture_dir", - ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], - ) - def test_run_he_link_on_trace_file_hbm(self, temp_dir, fixture_dir): + def _get_mem_hbm_addresses(self, mem_file): """ - @brief Test he_link.py with a trace file input from linking_fixtures + Helper to extract mload and mstore addresses from mem file. + """ + assert mem_file.exists() + + with open(mem_file, encoding="utf-8") as f: + split_lines = f.read().splitlines() + dload_addresses, dstore_addresses = set(), set() + for line in split_lines: + instr, _ = line.split("#", 1) if "#" in line else (line, "") + if line.startswith("dload"): + dload_addresses.add(instr.split(",")[2].strip()) + elif line.startswith("dstore"): + dstore_addresses.add(instr.split(",")[2].strip()) + + return dload_addresses, dstore_addresses + + def _get_minst_spad_addresses(self, minstrs): + """ + @brief Helper to extract mload and mstore addresses from minst instructions. + + @param minstrs List of MInstructions as lists of tokens. + @return tuple (mload_addresses, mstore_addresses) Sets of addresses. + """ + mload_addresses, mstore_addresses = set(), set() + for minst in minstrs: + if minst[1].startswith("mload"): + mload_addresses.add(minst[2]) + elif minst[1].startswith("mstore"): + mstore_addresses.add(minst[3]) + return mload_addresses, mstore_addresses + + def _parse_cinst_file(self, cinst_file): + """ + @brief Helper to parse cinst file and return a list of CInstructions. + + @param cinst_file Path to the cinst file. + @return List of CInstructions as lists of tokens. + """ + assert cinst_file.exists() + + # Save tokenized cinsts + with open(cinst_file, encoding="utf-8") as f: + lines = f.read().splitlines() + + cinstrs: list[list] = [] + for line in lines: + instr, _ = line.split("#", 1) if "#" in line else (line, "") + tokens = [token.strip() for token in instr.split(",")] + cinstrs.append(tokens) + + return cinstrs + + def _parse_minst_file(self, minst_file): + """ + @brief Helper to parse minst file and return a list of MInstructions. + + @param minst_file Path to the minst file. + @return List of MInstructions as lists of tokens. + """ + assert minst_file.exists() + # Save tokenized minst instructions + with open(minst_file, encoding="utf-8") as f: + lines = f.read().splitlines() + + minstrs: list[list] = [] + for line in lines: + instr, _ = line.split("#", 1) if "#" in line else (line, "") + tokens = [token.strip() for token in instr.split(",")] + minstrs.append(tokens) + + return minstrs + + def _parse_xinst_file(self, xinst_file): + """ + @brief Helper to parse xinst file and return a list of XInstructions. + + @param xinst_file Path to the xinst file. + @return List of XInstructions as lists of tokens. + """ + assert xinst_file.exists() + # Save tokenized xinst instructions + with open(xinst_file, encoding="utf-8") as f: + lines = f.read().splitlines() + xinstrs: list[list] = [] + for line in lines: + instr, _ = line.split("#", 1) if "#" in line else (line, "") + tokens = [token.strip() for token in instr.split(",")] + xinstrs.append(tokens) + return xinstrs + + def run_he_link_with_trace_file(self, temp_dir, fixture_dir, hbm_enabled, keep_hbm_boundary, keep_spad_boundary): + """ + @brief Helper to run he_link with trace file input + + @param temp_dir Temporary directory for input/output files + @param fixture_dir Directory containing fixture files + @param hbm_enabled Whether to enable HBM + @param keep_hbm_boundary Whether to keep HBM boundary + @param keep_spad_boundary Whether to keep SPAD boundary + + @return tuple containing (output_dir, output_prefix, kernel_ops) """ fixtures_root = Path(__file__).parent / "linking_fixtures" / fixture_dir trace_file_name = f"{fixture_dir}_program_trace.csv" - cfg_kwargs = { "input_prefixes": [], "output_prefix": "linked_output_trace", @@ -230,7 +318,9 @@ def test_run_he_link_on_trace_file_hbm(self, temp_dir, fixture_dir): "trace_file": str(Path(temp_dir) / "input" / trace_file_name), "using_trace_file": True, "use_xinstfetch": False, - "has_hbm": True, + "keep_hbm_boundary": keep_hbm_boundary, + "keep_spad_boundary": keep_spad_boundary, + "has_hbm": hbm_enabled, "hbm_size": 2048, } @@ -238,9 +328,9 @@ def test_run_he_link_on_trace_file_hbm(self, temp_dir, fixture_dir): Path(cfg_kwargs["input_dir"]).mkdir(parents=True, exist_ok=True) shutil.copy(fixtures_root / trace_file_name, cfg_kwargs["input_dir"]) - # Copy hbm folder content to input_dir - hbm_dir = fixtures_root / "hbm" - for item in hbm_dir.iterdir(): + # Copy hbm or no_hbm folder content to input_dir + content_dir = fixtures_root / ("hbm" if hbm_enabled else "no_hbm") + for item in content_dir.iterdir(): if item.is_file(): shutil.copy(item, cfg_kwargs["input_dir"]) @@ -250,22 +340,91 @@ def test_run_he_link_on_trace_file_hbm(self, temp_dir, fixture_dir): # Run he_link he_link.main(LinkerRunConfig(**cfg_kwargs)) - # Check output .xinst files exist - out_file = ( - Path(cfg_kwargs["output_dir"]) / f"{cfg_kwargs['output_prefix']}.xinst" - ) - assert out_file.exists() + # Check all output files exist + output_dir = Path(cfg_kwargs["output_dir"]) + output_prefix = cfg_kwargs["output_prefix"] + for ext in [".xinst", ".minst", ".cinst", ".mem"]: + out_file = output_dir / f"{output_prefix}{ext}" + assert out_file.exists(), f"Output file {out_file} does not exist" - # Extract trace vars + # Extract trace vars for tests kernel_ops = TraceInfo.parse_kernel_ops_from_file(cfg_kwargs["trace_file"]) - overall_input_vars, overall_output_vars, intermediate_vars = ( - self._extract_trace_vars(kernel_ops) - ) + + # Return needed information for tests + return (output_dir, output_prefix, kernel_ops) + + @pytest.fixture + def run_he_link_trace_hbm_no_boundary(self, temp_dir, fixture_dir): + """ + @brief Fixture to run he_link once with trace file input and HBM enabled + + @return tuple containing (output_dir, output_prefix, trace_file, kernel_ops) + """ + return self.run_he_link_with_trace_file(temp_dir, fixture_dir, hbm_enabled=True, keep_hbm_boundary=False, keep_spad_boundary=False) + + @pytest.fixture + def run_he_link_trace_hbm_spad_boundary(self, temp_dir, fixture_dir): + """ + @brief Fixture to run he_link once with trace file input and HBM enabled + + @return tuple containing (output_dir, output_prefix, trace_file, kernel_ops) + """ + return self.run_he_link_with_trace_file(temp_dir, fixture_dir, hbm_enabled=True, keep_hbm_boundary=False, keep_spad_boundary=True) + + @pytest.fixture + def run_he_link_trace_hbm_with_boundary(self, temp_dir, fixture_dir): + """ + @brief Fixture to run he_link once with trace file input and HBM enabled + + @return tuple containing (output_dir, output_prefix, trace_file, kernel_ops) + """ + return self.run_he_link_with_trace_file(temp_dir, fixture_dir, hbm_enabled=True, keep_hbm_boundary=True, keep_spad_boundary=True) + + @pytest.fixture + def run_he_link_trace_no_hbm_no_boundary(self, temp_dir, fixture_dir): + """ + @brief Fixture to run he_link once with trace file input and HBM disabled + + @return tuple containing (output_dir, output_prefix, trace_file, kernel_ops) + """ + return self.run_he_link_with_trace_file(temp_dir, fixture_dir, hbm_enabled=False, keep_hbm_boundary=False, keep_spad_boundary=False) + + @pytest.fixture + def run_he_link_trace_no_hbm_spad_boundary(self, temp_dir, fixture_dir): + """ + @brief Fixture to run he_link once with trace file input and HBM disabled + + @return tuple containing (output_dir, output_prefix, trace_file, kernel_ops) + """ + return self.run_he_link_with_trace_file(temp_dir, fixture_dir, hbm_enabled=False, keep_hbm_boundary=False, keep_spad_boundary=True) + + @pytest.fixture + def run_he_link_trace_no_hbm_with_boundary(self, temp_dir, fixture_dir): + """ + @brief Fixture to run he_link once with trace file input and HBM disabled + + @return tuple containing (output_dir, output_prefix, trace_file, kernel_ops) + """ + return self.run_he_link_with_trace_file(temp_dir, fixture_dir, hbm_enabled=False, keep_hbm_boundary=True, keep_spad_boundary=True) + + @pytest.mark.parametrize( + "fixture_dir", + ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], + ) + @pytest.mark.parametrize("run_fixture", ["run_he_link_trace_hbm_no_boundary", "run_he_link_trace_no_hbm_no_boundary"]) + def test_mem_output_trace_file(self, fixture_dir, run_fixture, request): + """ + @brief Test he_link.py with a trace file input from linking_fixtures + """ + # Get the fixture function by name and call it + run_func = request.getfixturevalue(run_fixture) + output_dir, output_prefix, kernel_ops = run_func + + # Extract trace vars + overall_input_vars, overall_output_vars, intermediate_vars = self._extract_trace_vars(kernel_ops) # Check output *.mem - dload_var_labels, dstore_var_labels = self._parse_mem_file( - Path(cfg_kwargs["output_dir"]) / f"{cfg_kwargs['output_prefix']}.mem" - ) + dload_var_labels, dstore_var_labels = self._parse_n_test_mem_file(output_dir / f"{output_prefix}.mem") # Assert dload and dstore vars match overall input/output trace vars assert dload_var_labels == overall_input_vars @@ -273,73 +432,433 @@ def test_run_he_link_on_trace_file_hbm(self, temp_dir, fixture_dir): # Assert no intermediate variables in *.mem file assert not dload_var_labels.intersection(intermediate_vars), ( - "Found intermediate variables in dload_var_labels: " - f"{dload_var_labels.intersection(intermediate_vars)}" + "Found intermediate variables in dload_var_labels: " f"{dload_var_labels.intersection(intermediate_vars)}" ) assert not dstore_var_labels.intersection(intermediate_vars), ( - "Found intermediate variables in dstore_var_labels: " - f"{dstore_var_labels.intersection(intermediate_vars)}" + "Found intermediate variables in dstore_var_labels: " f"{dstore_var_labels.intersection(intermediate_vars)}" ) + def _validate_minst_file_common(self, output_dir, output_prefix): + """ + Helper to validate common aspects of minst files in both boundary and no-boundary tests. + Returns parsed data for additional specific validations. + """ + # .mem info + dload_addresses, dstore_addresses = self._get_mem_hbm_addresses(output_dir / f"{output_prefix}.mem") + + # .cinst info + cinstrs = self._parse_cinst_file(output_dir / f"{output_prefix}.cinst") + + # Check output .minst file + minst_file = output_dir / f"{output_prefix}.minst" + + # Read minst file content + minstrs = self._parse_minst_file(minst_file) + + # Assert minst file has content (should contain MInstructions) + assert len(minstrs) > 0, "Expected minst file to have content" + + # Assert last line contains msyncc (termination instruction) + last_tokens = minstrs[-1] + assert "msyncc" in last_tokens[1], "Expected last line to contain msyncc termination instruction" + + last_cinst_spad = 0 + spad_address_resets = 0 + for i, tokens in enumerate(minstrs[:-1]): + # Assert no empty lines in between (except possibly the last one) + assert tokens, f"Found empty line at index {i} in minst file" + # Assert index is consecutive + assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {", ".join(tokens)}" + # Assert mload/mstore addresses are digits + if tokens[1].startswith("mstore") or tokens[1].startswith("mload"): + assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line: {", ".join(tokens)}" + assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line: {", ".join(tokens)}" + + if tokens[1].startswith("mload") and tokens[3] == "0": + # If mload address is 0, it should be a reset + spad_address_resets += 1 + + elif tokens[1].startswith("mstore"): + # Assert previous instruction was an msyncc + assert minstrs[i - 1][1].startswith( + "msyncc" + ), f"Expected mstore to follow msyncc in line: {", ".join(tokens)} - prev: {", ".join(minstrs[i - 1])}" + # Assert mstore's SPAD address is its cstore's SPAD address + assert tokens[3] == last_cinst_spad, ( + f"Expected mstore SPAD address {tokens[3]} to match last cstore SPAD address " + f"{last_cinst_spad} in line: {", ".join(tokens)}" + ) + + elif tokens[1].startswith("msyncc"): + target = tokens[2].strip() + # Assert msyncc targets are digits + assert target.isdigit(), f"Expected msyncc target to be digit in line: {", ".join(tokens)}" + # Assert targeted cinst is a cstore + assert cinstrs[int(target)][1].startswith( + "cstore" + ), f"Expected msyncc target {target} to be a cstore in line: {", ".join(tokens)}" + last_cinst_spad = cinstrs[int(target)][2].strip() + + return { + "minstrs": minstrs, + "cinstrs": cinstrs, + "dload_addresses": dload_addresses, + "dstore_addresses": dstore_addresses, + "spad_address_resets": spad_address_resets, + } + + @pytest.mark.parametrize( + "fixture_dir", + ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], + ) + def test_minst_output_trace_file_hbm_no_boundary(self, run_he_link_trace_hbm_no_boundary): + """ + @brief Test .minst file output from he_link.py with trace file input and HBM enabled + """ + output_dir, output_prefix, _ = run_he_link_trace_hbm_no_boundary + + # Validate common aspects and get validation data + validation_data = self._validate_minst_file_common(output_dir, output_prefix) + + minstrs = validation_data["minstrs"] + dload_addresses = validation_data["dload_addresses"] + dstore_addresses = validation_data["dstore_addresses"] + spad_address_resets = validation_data["spad_address_resets"] + mload_spad_addresses = set() + + # No-boundary specific validations: + # Check each instruction's addresses are in expected sets + for tokens in minstrs[:-1]: + if tokens[1].startswith("mload"): + # Assert mload's hbm addresses are in expected set + assert ( + tokens[3] in dload_addresses + ), f"Expected mload HBM address {tokens[3]} to be in {dload_addresses} in line: {", ".join(tokens)}" + # Assert spad address is not duplicate in mload sequence + assert ( + tokens[2] not in mload_spad_addresses + ), f"Expected mload SPAD address {tokens[2]} to be unique within mload sequence for line: {", ".join(tokens)}" + mload_spad_addresses.add(tokens[2]) + elif tokens[1].startswith("mstore"): + # Assert mstore's hbm addresses are in expected set + assert ( + tokens[2] in dstore_addresses + ), f"Expected mstore HBM address {tokens[2]} to be in {dstore_addresses} in line: {", ".join(tokens)}" + + # Assert spad resets count matches 1 + assert spad_address_resets == 1, f"Expected 1 spad resets but found {spad_address_resets} in minst file" + + @pytest.mark.parametrize( + "fixture_dir", + ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], + ) + def test_minst_output_trace_file_hbm_with_boundary(self, run_he_link_trace_hbm_with_boundary): + """ + @brief Test .minst file output from he_link.py with trace file input and HBM enabled + """ + output_dir, output_prefix, kernel_ops = run_he_link_trace_hbm_with_boundary + + # Validate common aspects and get validation data + validation_data = self._validate_minst_file_common(output_dir, output_prefix) + + minstrs = validation_data["minstrs"] + dload_addresses = validation_data["dload_addresses"] + spad_address_resets = validation_data["spad_address_resets"] + mload_spad_addresses = set() + mstore_hbm_addresses = set() + + # With-boundary specific validations: + # We need to track HBM addresses across the file + for tokens in minstrs[:-1]: + if tokens[1].startswith("mload"): + # Assert mload's hbm addresses are in expected set + assert tokens[3] in ( + dload_addresses | mstore_hbm_addresses + ), f"Expected mload HBM address {tokens[3]} to be in {dload_addresses | mstore_hbm_addresses} in line: {", ".join(tokens)}" + # Reset tracking for each new kernel + if tokens[3] == "0": + mload_spad_addresses = set() + + # Assert spad address is not duplicate in mload sequence + assert ( + tokens[2] not in mload_spad_addresses + ), f"Expected mload SPAD address {tokens[2]} to be unique within mload sequence for line: {", ".join(tokens)}" + mload_spad_addresses.add(tokens[2]) + elif tokens[1].startswith("mstore"): + # Track intermediate mstore addresses for later mloads + if tokens[2] not in dload_addresses: + mstore_hbm_addresses.add(tokens[2]) + + # Assert spad resets count matches expected kernel ops + assert spad_address_resets == len( + kernel_ops + ), f"Expected {len(kernel_ops)} spad resets but found {spad_address_resets} in minst file" + @pytest.mark.parametrize( "fixture_dir", ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], ) - def test_run_he_link_on_trace_file_no_hbm(self, temp_dir, fixture_dir): + @pytest.mark.parametrize("run_fixture", ["run_he_link_trace_no_hbm_no_boundary", "run_he_link_trace_no_hbm_with_boundary"]) + def test_minst_output_trace_file_no_hbm(self, fixture_dir, run_fixture, request): """ @brief Test he_link.py with a trace file input from linking_fixtures """ - fixtures_root = Path(__file__).parent / "linking_fixtures" / fixture_dir - trace_file_name = f"{fixture_dir}_program_trace.csv" - in_trace_file = fixtures_root / trace_file_name + # Get the fixture function by name and call it + run_func = request.getfixturevalue(run_fixture) + output_dir, output_prefix, _ = run_func - # Copy to temp input dir - input_dir = Path(temp_dir) / "input" - input_dir.mkdir(parents=True, exist_ok=True) - shutil.copy(in_trace_file, input_dir) + # Assert minst is one line + out_file = output_dir / f"{output_prefix}.minst" + assert out_file.exists() + with open(out_file, encoding="utf-8") as f: + content = f.read() + assert content.count("\n") == 1, "Expected minst output to be a single line" - # Copy hbm folder content to input_dir - hbm_dir = fixtures_root / "no_hbm" - for item in hbm_dir.iterdir(): - if item.is_file(): - shutil.copy(item, input_dir) + def _validate_cinst_file_hbm_common(self, output_dir, output_prefix): + """ + @brief Common validation logic for cinst files with HBM enabled - # Prepare config - output_dir = Path(temp_dir) / "output" - output_dir.mkdir(exist_ok=True) - trace_file = input_dir / trace_file_name - cfg_kwargs = { - "input_prefixes": [], - "output_prefix": "linked_output_trace", - "input_mem_file": None, - "input_dir": str(input_dir), - "output_dir": str(output_dir), - "trace_file": str(trace_file), - "using_trace_file": True, - "use_xinstfetch": False, - "has_hbm": False, - "hbm_size": 2048, - } + @param output_dir Path to output directory + @param output_prefix Prefix for output files + @param kernel_ops List of kernel operations (optional) + @param check_kernel_count Whether to validate kernel count against kernel_ops + @return Dictionary of validation counts and data for specific test assertions + """ + # Get instructions from cinst/minst files + cinstrs = self._parse_cinst_file(output_dir / f"{output_prefix}.cinst") + minstrs = self._parse_minst_file(output_dir / f"{output_prefix}.minst") + xinstrs = self._parse_xinst_file(output_dir / f"{output_prefix}.xinst") + + mload_addresses, mstore_addresses = self._get_minst_spad_addresses(minstrs) + last_bundle = int(xinstrs[-1][0][1:]) # Remove 'F' prefix from last bundle + + # Assert cinst file has content (should contain CInstructions) + assert len(cinstrs) > 0, "Expected cinst file to have content" + + # Validation data + last_minstr_spad = 0 + cstore_spad_addresses = set() + csyncm_count = 0 + + # Validate cinst file content + for i, tokens in enumerate(cinstrs[:-1]): + if tokens[1].startswith("csyncm"): + csyncm_count += 1 + # Assert csyncm targets are digits + assert tokens[2].isdigit(), f"Expected csyncm target to be digit in line: {", ".join(tokens)}" + # Not second last instruction + if i < len(cinstrs) - 2: + target_minst = minstrs[int(tokens[2])] + last_minstr_spad = target_minst[2] + + elif tokens[1] in ["cload", "bload", "nload", "bones"]: + # Assert cload/bload/nload/bones SPAD address is digits + assert tokens[3].isdigit(), f"Expected SPAD address {tokens[3]} to be digit in line: {", ".join(tokens)}" + # Assert SPAD address is in mload_addresses or cstore_spad_addresses + assert tokens[3] in (mload_addresses | cstore_spad_addresses), ( + f"Expected SPAD address {tokens[3]} to be in mload or mstore addresses " + f"in line: {", ".join(tokens)} cstore addresses: {cstore_spad_addresses}" + ) + if tokens[1] in ["cload", "bload"] and tokens[3] in mload_addresses: + # Assert cload/bload SPAD address is last mload's SPAD address + assert tokens[3] == last_minstr_spad, ( + f"Expected SPAD address {tokens[3]} to match last mload's SPAD " + f"address {last_minstr_spad} in line: {", ".join(tokens)}" + ) + + if tokens[1].startswith("bones") and tokens[2] in mload_addresses: + # Assert bones SPAD address is last mload's SPAD address + assert tokens[2] == last_minstr_spad, ( + f"Expected SPAD address {tokens[2]} to match last mload's SPAD " + f"address {last_minstr_spad} in line: {", ".join(tokens)}" + ) + + elif tokens[1].startswith("cstore"): + # Assert cstore SPAD address is digits + assert tokens[2].isdigit(), f"Expected SPAD address {tokens[2]} to be digit in line: {", ".join(tokens)}" + if tokens[2] not in mstore_addresses: + cstore_spad_addresses.add(tokens[2]) + + elif tokens[1].startswith("ifetch"): + # Assert ifetch target is digits + assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line: {", ".join(tokens)}" + # Assert ifetch target is a valid xinst bundle + assert ( + int(tokens[2]) <= last_bundle + ), f"Expected ifetch target {tokens[2]} to be less than or equal to last bundle {last_bundle} in line: {", ".join(tokens)}" + + # Assert no empty lines in between (except possibly the last one) + assert tokens, "Found empty line in cinst file" + + # Assert index is consecutive + assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {", ".join(tokens)}" + + # Assert last line contains cexit (termination instruction) + last_tokens = cinstrs[-1] + assert "cexit" in last_tokens[1], "Expected last line to contain cexit termination instruction" + + # Assert last csyncm (second last instruction) is present + csyncm_tokens = cinstrs[-2] + assert csyncm_tokens[1].startswith("csyncm"), "Expected second last line to contain csyncm instruction" + # Assert last csyncm's target is digits + assert csyncm_tokens[2].isdigit(), f"Expected last csyncm target {csyncm_tokens[2]} to be digit in line: {", ".join(csyncm_tokens)}" + # Assert last csyncm's target is the second last minst + assert int(csyncm_tokens[2]) == len(minstrs) - 2, "Expected last csyncm target to be the second last minst" + # Assert csyncm instructions are present in HBM mode (they should be kept) + assert csyncm_count > 0, "Expected to find csyncm instructions in cinst output file for HBM mode" + + # Return validation data for any additional test-specific assertions + return {"csyncm_count": csyncm_count, "cinstrs": cinstrs, "minstrs": minstrs} - # Run he_link - he_link.main(LinkerRunConfig(**cfg_kwargs)) + @pytest.mark.parametrize( + "fixture_dir", + ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], + ) + def test_cinst_output_trace_file_hbm_no_boundary(self, run_he_link_trace_hbm_no_boundary): + """ + @brief Test .cinst file output from he_link.py with trace file input and HBM enabled + """ + output_dir, output_prefix, _ = run_he_link_trace_hbm_no_boundary - # Check output .xinst files exist - out_file = output_dir / f"{cfg_kwargs['output_prefix']}.xinst" - assert out_file.exists() + # Validate common aspects and get validation data + validation_data = self._validate_cinst_file_hbm_common(output_dir, output_prefix) - # Assert no csyncm instructions in cinst output file - out_file = output_dir / f"{cfg_kwargs['output_prefix']}.cinst" - assert out_file.exists() - with open(out_file, "r", encoding="utf-8") as f: - content = f.read() - assert ( - "csyncm" not in content - ), "Found csyncm instruction in cinst output file" + # Get instructions from cinst/minst files + cinstrs = validation_data["cinstrs"] + minstrs = validation_data["minstrs"] - # Assert minst is one line - out_file = output_dir / f"{cfg_kwargs['output_prefix']}.minst" - assert out_file.exists() - with open(out_file, "r", encoding="utf-8") as f: - content = f.read() - assert content.count("\n") == 1, "Expected minst output to be a single line" + # Validate specific cinst file content + for i, tokens in enumerate(cinstrs[:-1]): + if tokens[1].startswith("csyncm"): + # Not second last instruction + if i < len(cinstrs) - 2: + # Assert targeted minst is an mload + assert minstrs[int(tokens[2])][1].startswith( + "mload" + ), f"Expected csyncm target {tokens[2]} to be a mload in line: {", ".join(tokens)}" + + @pytest.mark.parametrize( + "fixture_dir", + ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], + ) + def test_cinst_output_trace_file_hbm_spad_boundary(self, run_he_link_trace_hbm_spad_boundary): + """ + @brief Test .cinst file output from he_link.py with trace file input and HBM enabled + """ + output_dir, output_prefix, _ = run_he_link_trace_hbm_spad_boundary + + # Validate common aspects and get validation data + validation_data = self._validate_cinst_file_hbm_common(output_dir, output_prefix) + + # Get instructions from cinst/minst files + cinstrs = validation_data["cinstrs"] + minstrs = validation_data["minstrs"] + + # Validate specific cinst file content + for i, tokens in enumerate(cinstrs[:-1]): + if tokens[1].startswith("csyncm"): + # Not second last instruction + if i < len(cinstrs) - 2: + # Assert targeted minst is an mload + assert minstrs[int(tokens[2])][1].startswith( + "mload" + ), f"Expected csyncm target {tokens[2]} to be a mload in line: {", ".join(tokens)}" + + @pytest.mark.parametrize( + "fixture_dir", + ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], + ) + def test_cinst_output_trace_file_hbm_with_boundary(self, run_he_link_trace_hbm_with_boundary): + """ + @brief Test .cinst file output from he_link.py with trace file input and HBM enabled + """ + output_dir, output_prefix, kernel_ops = run_he_link_trace_hbm_with_boundary + + # Validate common aspects and get validation data + validation_data = self._validate_cinst_file_hbm_common(output_dir, output_prefix) + + # Get instructions from cinst/minst files + cinstrs = validation_data["cinstrs"] + minstrs = validation_data["minstrs"] + + # Validate specific cinst file content + kernels_count = 0 + for tokens in cinstrs[:-1]: + if tokens[1].startswith("csyncm"): + # Assert targeted minst is an mload/mstore + assert minstrs[int(tokens[2])][1] in ( + "mload", + "mstore", + ), f"Expected csyncm target {tokens[2]} to be a mload in line: {", ".join(tokens)}" + + elif tokens[1].startswith("cload"): + if tokens[3] == "13": + # If cload/bload SPAD address is 13, it should be a new kernel operation + kernels_count += 1 + + # Assert kernels count matches expected + assert kernels_count == len(kernel_ops), f"Expected {len(kernel_ops)} kernels but found {kernels_count} in cinst file" + + @pytest.mark.parametrize( + "fixture_dir", + ["bgv_multi_add_add_mul_8192_l1_m2", "bgv_multi_mul_relin_16384_l1_m2"], + ) + @pytest.mark.parametrize( + "run_fixture", + ["run_he_link_trace_no_hbm_spad_boundary", "run_he_link_trace_no_hbm_with_boundary", "run_he_link_trace_no_hbm_no_boundary"], + ) + def test_cinst_output_trace_file_no_hbm(self, fixture_dir, run_fixture, request): + """ + @brief Test .cinst file output from he_link.py with trace file input and no HBM + """ + # Get the fixture function by name and call it + run_func = request.getfixturevalue(run_fixture) + output_dir, output_prefix, _ = run_func + + # .mem info + dload_addresses, _ = self._get_mem_hbm_addresses(output_dir / f"{output_prefix}.mem") + + # Read cinst/xinst file content + cinstrs = self._parse_cinst_file(output_dir / f"{output_prefix}.cinst") + xinstrs = self._parse_xinst_file(output_dir / f"{output_prefix}.xinst") + + last_bundle = int(xinstrs[-1][0][1:]) # Remove 'F' prefix from last bundle + + # Assert cinst file has content (should contain CInstructions) + assert len(cinstrs) > 0, "Expected cinst file to have content" + + cstore_spad_addresses = set() + + # Check each instruction's addresses are in expected sets + for i, tokens in enumerate(cinstrs[:-1]): + # Assert no empty lines in between (except possibly the last one) + assert tokens, f"Found empty line at index {i} in minst file" + # Assert index is consecutive + assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {", ".join(tokens)}" + + if tokens[1].startswith("cstore"): + # Assert cstore's spad addresses are digits + assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line: {", ".join(tokens)}" + cstore_spad_addresses.add(tokens[2]) + elif tokens[1].startswith("cload"): + # Assert cload's spad addresses are digits + assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line: {", ".join(tokens)}" + # Assert cload's spad addresses are in expected set + assert tokens[3] in (dload_addresses | cstore_spad_addresses), ( + f"Expected cload SPAD address {tokens[3]} to be in {dload_addresses | cstore_spad_addresses} " + f"in line: {", ".join(tokens)}" + ) + elif tokens[1].startswith("ifetch"): + # Assert ifetch target is digits + assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line: {", ".join(tokens)}" + # Assert ifetch target is a valid xinst bundle + assert ( + int(tokens[2]) <= last_bundle + ), f"Expected ifetch target {tokens[2]} to be less than or equal to last bundle {last_bundle} in line: {", ".join(tokens)}" + + # Assert last line contains cexit (termination instruction) + last_tokens = cinstrs[-1] + assert "cexit" in last_tokens[1], "Expected last line to contain cexit termination instruction" + + # Assert no csyncm instructions are present in cinsts + assert not any("csyncm" in tokens[1] for tokens in cinstrs), "Expected no csyncm instructions in cinst output file for no HBM mode" diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py index 2212dc24..22e091cf 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_linker/test_steps/test_program_linker.py @@ -317,7 +317,7 @@ def test_update_cinsts_addresses_and_offsets(self): mock_cstore.comment = None # Execute the method with HBM enabled - kernel_cinstrs = [mock_ifetch, mock_csyncm] + kernel_cinstrs = [mock_ifetch, mock_csyncm, mock_csyncm] self.program._bundle_offset = 10 self.program._minst_line_offset = 20 self.program._update_cinsts_addresses_and_offsets(kernel_cinstrs) @@ -1472,10 +1472,12 @@ def test_prune_minst_kernel_msyncc_tracking(self): # Create mock MSyncc instruction mock_msyncc = MagicMock(spec=minst.MSyncc) mock_msyncc.idx = 0 + mock_msyncc.comment = "" mock_mload = MagicMock(spec=minst.MLoad) mock_mload.var_name = "test_var" mock_mload.spad_address = 10 + mock_mload.comment = "" mock_mload.idx = 1 # Create mock kernel @@ -1498,6 +1500,7 @@ def test_prune_minst_kernel_mstore_intermediate_var(self): mock_mstore = MagicMock(spec=minst.MStore) mock_mstore.var_name = "intermediate_var" mock_mstore.spad_address = 20 + mock_mstore.comment = "" mock_mstore.idx = 0 # Create mock kernel @@ -1527,6 +1530,7 @@ def test_prune_minst_kernel_mstore_intermediate_var_with_spad_boundary(self): mock_mstore = MagicMock(spec=minst.MStore) mock_mstore.var_name = "intermediate_var" mock_mstore.spad_address = 20 + mock_mstore.comment = "" mock_mstore.idx = 0 # Create mock kernel @@ -1548,10 +1552,12 @@ def test_prune_minst_kernel_mstore_with_preceding_msyncc(self): # Create mock MSyncc and MStore mock_msyncc = MagicMock(spec=minst.MSyncc) mock_msyncc.idx = 0 + mock_msyncc.comment = "" mock_mstore = MagicMock(spec=minst.MStore) mock_mstore.var_name = "intermediate_var" mock_mstore.spad_address = 15 + mock_mstore.comment = "" mock_mstore.idx = 1 # Create mock kernel @@ -1572,6 +1578,7 @@ def test_prune_minst_kernel_mstore_keep_instruction(self): mock_mstore = MagicMock(spec=minst.MStore) mock_mstore.var_name = "output_var" mock_mstore.spad_address = 20 + mock_mstore.comment = "" mock_mstore.idx = 0 # Create mock kernel @@ -1596,6 +1603,7 @@ def test_prune_minst_kernel_mload_already_loaded(self): mock_mload = MagicMock(spec=minst.MLoad) mock_mload.var_name = "loaded_var" mock_mload.spad_address = 10 + mock_mload.comment = "" mock_mload.idx = 0 # Create mock kernel @@ -1620,6 +1628,7 @@ def test_prune_minst_kernel_mload_intermediate_var(self): mock_mload = MagicMock(spec=minst.MLoad) mock_mload.var_name = "intermediate_var" mock_mload.spad_address = 10 + mock_mload.comment = "" mock_mload.idx = 0 # Create mock kernel @@ -1649,6 +1658,7 @@ def test_prune_minst_kernel_mload_intermediate_var_with_spad_boundary(self): mock_mload = MagicMock(spec=minst.MLoad) mock_mload.var_name = "intermediate_var" mock_mload.spad_address = 10 + mock_mload.comment = "" mock_mload.idx = 0 # Create mock kernel @@ -1668,6 +1678,7 @@ def test_prune_minst_kernel_mload_keep_instruction(self): mock_mload = MagicMock(spec=minst.MLoad) mock_mload.var_name = "new_var" mock_mload.spad_address = 10 + mock_mload.comment = "" mock_mload.idx = 0 # Create mock kernel @@ -1692,20 +1703,24 @@ def test_prune_minst_kernel_mixed_instructions(self): # Create mock instructions mock_msyncc = MagicMock(spec=minst.MSyncc) mock_msyncc.idx = 0 + mock_msyncc.comment = "MSyncc instruction" mock_mload1 = MagicMock(spec=minst.MLoad) # Already loaded mock_mload1.var_name = "already_loaded" mock_mload1.spad_address = 10 + mock_mload1.comment = "" mock_mload1.idx = 1 mock_mstore = MagicMock(spec=minst.MStore) # Intermediate variable mock_mstore.var_name = "intermediate_var" mock_mstore.spad_address = 15 + mock_mstore.comment = "" mock_mstore.idx = 2 mock_mload2 = MagicMock(spec=minst.MLoad) # New variable mock_mload2.var_name = "new_var" mock_mload2.spad_address = 20 + mock_mload2.comment = "" mock_mload2.idx = 3 # Create mock kernel @@ -1731,16 +1746,19 @@ def test_prune_minst_kernel_spad_size_tracking(self): mock_mload1 = MagicMock(spec=minst.MLoad) mock_mload1.var_name = "var1" mock_mload1.spad_address = 10 + mock_mload1.comment = "" mock_mload1.idx = 0 mock_mstore = MagicMock(spec=minst.MStore) mock_mstore.var_name = "var2" mock_mstore.spad_address = 25 + mock_mstore.comment = "" mock_mstore.idx = 1 mock_mload2 = MagicMock(spec=minst.MLoad) mock_mload2.var_name = "var3" mock_mload2.spad_address = 15 + mock_mload2.comment = "" mock_mload2.idx = 2 # Create mock kernel @@ -1763,16 +1781,19 @@ def test_prune_minst_kernel_adjustment_calculations(self): mock_mload1 = MagicMock(spec=minst.MLoad) # Intermediate - will be skipped mock_mload1.var_name = "intermediate_var1" mock_mload1.spad_address = 10 + mock_mload1.comment = "" mock_mload1.idx = 0 mock_mstore = MagicMock(spec=minst.MStore) # Intermediate - will be skipped mock_mstore.var_name = "intermediate_var2" mock_mstore.spad_address = 15 + mock_mstore.comment = "" mock_mstore.idx = 1 mock_mload2 = MagicMock(spec=minst.MLoad) # Regular - should be adjusted mock_mload2.var_name = "regular_var" mock_mload2.spad_address = 20 + mock_mload2.comment = "" mock_mload2.idx = 2 # Create mock kernel From 3c21e58302df4542d6bc3729cee33285b2e0ff60 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Thu, 21 Aug 2025 18:20:07 +0000 Subject: [PATCH 06/12] Cleaning --- .../linker/linker_run_config.py | 1 - .../linker/steps/program_linker.py | 36 ++++++------------- .../linker/steps/variable_discovery.py | 3 -- 3 files changed, 11 insertions(+), 29 deletions(-) diff --git a/assembler_tools/hec-assembler-tools/linker/linker_run_config.py b/assembler_tools/hec-assembler-tools/linker/linker_run_config.py index 7e57ab56..4aeb78a4 100644 --- a/assembler_tools/hec-assembler-tools/linker/linker_run_config.py +++ b/assembler_tools/hec-assembler-tools/linker/linker_run_config.py @@ -82,7 +82,6 @@ def __init__(self, **kwargs): # class members based on configuration for config_name, default_value in self.__default_config.items(): value = kwargs.get(config_name, default_value) - print(f"Config: {config_name} = {value} default: {default_value}") if value is not None: setattr(self, config_name, value) else: diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py index d1f7d40c..8ff97571 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py @@ -230,8 +230,6 @@ def _update_minsts(self, kernel: KernelInfo): while idx < len(kernel.minstrs): minstr = kernel.minstrs[idx] - print(f"ROCHA ({idx}): processing minst {minstr.to_line()} token 0 {minstr.idx} id {minstr.id}") - # Update msyncc if isinstance(minstr, minst.MSyncc): # If not the last MSyncc @@ -264,7 +262,6 @@ def _update_minsts(self, kernel: KernelInfo): minstr.hbm_address = hbm_address minstr.comment = f" var: {var_name} - HBM({hbm_address})" + f";{minstr.comment}" if minstr.comment else "" - print(f"ROCHA ({idx}) NEW minst {minstr.to_line()}") idx += 1 # next instruction def _remove_and_merge_csyncm_cnop(self, kernel: KernelInfo): @@ -277,8 +274,6 @@ def _remove_and_merge_csyncm_cnop(self, kernel: KernelInfo): current_bundle = 0 csyncm_count = 0 while i < len(kernel.cinstrs): - print(f"ROCHA ({i}): CINST -> {kernel.cinstrs[i].to_line()}") - cinstr = kernel.cinstrs[i] cinstr.idx = str(i) # Update the line number @@ -345,15 +340,18 @@ def _remove_and_merge_csyncm_cnop(self, kernel: KernelInfo): # Merge continuous cnop i = 0 while i < len(kernel.cinstrs): - print(f"ROCHA ({i}): CINST -> {kernel.cinstrs[i].to_line()}") - cinstr = kernel.cinstrs[i] - cinstr.idx = str(i) - if isinstance(cinstr, cinst.CNop): - # Do look ahead - if i + 1 < len(kernel.cinstrs): - if isinstance(kernel.cinstrs[i + 1], cinst.CNop): + if kernel.cinstrs_map[i].action != InstrAct.SKIP: + cinstr = kernel.cinstrs[i] + cinstr.idx = str(i) + if isinstance(cinstr, cinst.CNop): + # Do look ahead + _next = i + 1 + while kernel.cinstrs_map[_next].action == InstrAct.SKIP and _next < len(kernel.cinstrs): + _next += 1 + + if isinstance(kernel.cinstrs[_next], cinst.CNop): # Add 1 because cnop n, waits for n+1 cycles - kernel.cinstrs[i + 1].cycles += cinstr.cycles + 1 + kernel.cinstrs[_next].cycles += cinstr.cycles + 1 kernel.cinstrs_map[i].action = InstrAct.SKIP i += 1 @@ -413,7 +411,6 @@ def _update_cinst_kernel_hbm(self, kernel: KernelInfo): syncm_idx = 0 while idx < len(kernel.cinstrs): cinstr = kernel.cinstrs[idx] - print(f"ROCHA ({idx}): CINST -> {cinstr.to_line()} # {cinstr.comment}") if isinstance(cinstr, cinst.CSyncm): syncm_idx = cinstr.target @@ -421,12 +418,10 @@ def _update_cinst_kernel_hbm(self, kernel: KernelInfo): if kernel.cinstrs_map[idx].action != InstrAct.SKIP: minstr = kernel.minstrs_map[syncm_idx].minstr cinstr.target = minstr.idx - print(f"ROCHA ({idx}): CSyncm target {cinstr.target}") elif isinstance(cinstr, (cinst.CLoad, cinst.BLoad, cinst.BOnes)): # Update CLoad/BLoad/BOnes SPAD addresses to new minst if kernel.cinstrs_map[idx].action != InstrAct.SKIP: - print(f"ROCHA ({idx}): Updating CLoad/BLoad/BOnes syncm_idx {syncm_idx} source {cinstr.var_name}") minstr_idx = search_minstrs_back(kernel.minstrs_map, syncm_idx, cinstr.spad_address) minstr = kernel.minstrs_map[minstr_idx].minstr cinstr.var_name = minstr.var_name @@ -456,7 +451,6 @@ def _update_cinst_kernel_hbm(self, kernel: KernelInfo): cinstr.spad_address = minstr.spad_address self._cinst_in_var_tracker[cinstr.var_name] = cinstr.spad_address - print(f"ROCHA ({idx}): NEW CINST -> {cinstr.to_line()} # {cinstr.comment}") idx += 1 # next instruction def _update_cinsts(self, kernel: KernelInfo): @@ -518,11 +512,8 @@ def link_kernel(self, kernel: KernelInfo): # extract all instructions from minstrs marked as KEEP_HBM in minstrs_map minstrs_list = [minstr_map.minstr for minstr_map in kernel.minstrs_map if minstr_map.action == InstrAct.KEEP_HBM] - print(f"\nROCHA UPATADE MINST {kernel.minst} spad offset {self._spad_offset}\n") self._update_minsts(kernel) - print(f"\nROCHA UPATADE CINST {kernel.cinst} spad offset {self._spad_offset}\n") self._update_cinsts(kernel) - print(f"\nROCHA UPATADE xINST {kernel.xinst} spad offset {self._spad_offset}\n") self._bundle_offset = self._update_xinsts(kernel.xinstrs) + 1 self._spad_offset += (kernel.spad_size + 1) if not self._keep_hbm_boundary else 0 @@ -631,7 +622,6 @@ def prune_minst_kernel(self, kernel_info: KernelInfo): last_msyncc = None for idx, minstr in enumerate(kernel_info.minstrs): - print(f"ROCHA ({idx}): PRUNE MINST -> {minstr.to_line()} # {minstr.comment}") if isinstance(minstr, minst.MSyncc): last_msyncc = minstr elif isinstance(minstr, minst.MStore): @@ -665,11 +655,9 @@ def prune_minst_kernel(self, kernel_info: KernelInfo): minstr.idx = minstr.idx + adjust_idx # Update line number minstr.spad_address += adjust_spad # Adjust source spad address spad_size = minstr.spad_address - print(f"ROCHA ({idx}): PRUNE MINST -> Keeping {minstr.var_name} MStore - SPAD address {minstr.spad_address}") elif isinstance(minstr, minst.MLoad): # Remove mload instructions if variables already loaded if minstr.var_name in self._minst_in_var_tracker: - print(f"ROCHA ({idx}): PRUNE MINST -> Removing MLoad - already loaded {minstr.var_name}") kernel_info.minstrs_map[idx].action = InstrAct.SKIP minstr.spad_address = self._minst_in_var_tracker[minstr.var_name] # Adjust dest spad address adjust_spad -= 1 @@ -694,7 +682,6 @@ def prune_minst_kernel(self, kernel_info: KernelInfo): minstr.spad_address = new_spad # Adjust dest spad address minstr.idx = minstr.idx + adjust_idx # Update line number spad_size = minstr.spad_address - print(f"ROCHA ({idx}): PRUNE MINST -> Keeping {minstr.var_name} MLoad - SPAD address {minstr.spad_address}") # Track loaded variables self._minst_in_var_tracker[minstr.var_name] = minstr.spad_address @@ -764,7 +751,6 @@ def prune_cinst_kernel_hbm(self, kernel: KernelInfo): # Check if the variable is an intermediate variable if cinstr.var_name in self._intermediate_vars: # CSyncm no needed for intermediate variables - print(f"ROCHA ({idx}): PRUNE CINST -> Removing intermediate {cinstr.var_name} CStore") _idx, _cycles = remove_csyncm(kernel.cinstrs, kernel.cinstrs_map, idx + 1) adjust_idx += _idx adjust_cycles += _cycles diff --git a/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py b/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py index ae4c4e0d..90da2e82 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/variable_discovery.py @@ -93,7 +93,6 @@ def scan_variables( kernel_info.cinstrs = Loader.load_cinst_kernel_from_file(kernel_info.cinst) remap_m_c_instrs_vars(kernel_info.cinstrs, kernel_info.hbm_remap_dict) - print(f"\nROCHA Pruning Cinst {kernel_info.cinst}\n") p_linker.prune_cinst_kernel_no_hbm(kernel_info) for var_name in discover_variables_spad(kernel_info.cinstrs): @@ -108,8 +107,6 @@ def scan_variables( ) kernel_info.minstrs = Loader.load_minst_kernel_from_file(kernel_info.minst) remap_m_c_instrs_vars(kernel_info.minstrs, kernel_info.hbm_remap_dict) - - print(f"\nROCHA Pruning Minst {kernel_info.minst}\n") p_linker.prune_minst_kernel(kernel_info) for var_name in discover_variables(kernel_info.minstrs): From 3e49d93f81234377efb3ee30a2d137210bc02367 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Thu, 21 Aug 2025 20:17:39 +0000 Subject: [PATCH 07/12] Fix on CNOP merge --- .../hec-assembler-tools/linker/steps/program_linker.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py index 8ff97571..f988b52d 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py @@ -346,10 +346,10 @@ def _remove_and_merge_csyncm_cnop(self, kernel: KernelInfo): if isinstance(cinstr, cinst.CNop): # Do look ahead _next = i + 1 - while kernel.cinstrs_map[_next].action == InstrAct.SKIP and _next < len(kernel.cinstrs): + while _next < len(kernel.cinstrs) and kernel.cinstrs_map[_next].action == InstrAct.SKIP: _next += 1 - if isinstance(kernel.cinstrs[_next], cinst.CNop): + if _next < len(kernel.cinstrs) and isinstance(kernel.cinstrs[_next], cinst.CNop): # Add 1 because cnop n, waits for n+1 cycles kernel.cinstrs[_next].cycles += cinstr.cycles + 1 kernel.cinstrs_map[i].action = InstrAct.SKIP From de5cf49bf41d95f19bba05a3419c2adb3fed8a74 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Thu, 21 Aug 2025 21:20:11 +0000 Subject: [PATCH 08/12] Fixing nested blocks --- .../tests/integration_tests/test_he_link.py | 17 +-- .../tests/unit_tests/test_he_link.py | 116 ++++++++---------- 2 files changed, 63 insertions(+), 70 deletions(-) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py index 5104e3dd..3e84104f 100644 --- a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py @@ -834,27 +834,28 @@ def test_cinst_output_trace_file_no_hbm(self, fixture_dir, run_fixture, request) # Assert no empty lines in between (except possibly the last one) assert tokens, f"Found empty line at index {i} in minst file" # Assert index is consecutive - assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {", ".join(tokens)}" + assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line ({i}): {', '.join(tokens)}" if tokens[1].startswith("cstore"): # Assert cstore's spad addresses are digits - assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line: {", ".join(tokens)}" + assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line ({i}): {', '.join(tokens)}" cstore_spad_addresses.add(tokens[2]) elif tokens[1].startswith("cload"): # Assert cload's spad addresses are digits - assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line: {", ".join(tokens)}" + assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line ({i}): {', '.join(tokens)}" # Assert cload's spad addresses are in expected set assert tokens[3] in (dload_addresses | cstore_spad_addresses), ( f"Expected cload SPAD address {tokens[3]} to be in {dload_addresses | cstore_spad_addresses} " - f"in line: {", ".join(tokens)}" + f"in line ({i}): {', '.join(tokens)}" ) elif tokens[1].startswith("ifetch"): # Assert ifetch target is digits - assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line: {", ".join(tokens)}" + assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line ({i}): {', '.join(tokens)}" # Assert ifetch target is a valid xinst bundle - assert ( - int(tokens[2]) <= last_bundle - ), f"Expected ifetch target {tokens[2]} to be less than or equal to last bundle {last_bundle} in line: {", ".join(tokens)}" + assert int(tokens[2]) <= last_bundle, ( + f"Expected ifetch target {tokens[2]} to be less than or equal to " + f"last bundle {last_bundle} in line ({i}): {', '.join(tokens)}" + ) # Assert last line contains cexit (termination instruction) last_tokens = cinstrs[-1] diff --git a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py index 6d7528a7..2eccc718 100644 --- a/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py +++ b/assembler_tools/hec-assembler-tools/tests/unit_tests/test_he_link.py @@ -11,6 +11,7 @@ import argparse import io +from contextlib import ExitStack from unittest.mock import MagicMock, mock_open, patch import he_link @@ -105,52 +106,41 @@ def test_main(self, using_trace_file): mock_config.trace_file = "mock_trace.txt" if using_trace_file else "" # Act - with ( - patch("assembler.common.constants.convertBytes2Words", return_value=1024), - patch("he_link.prepare_output_files", mocks["prepare_output"]), - patch("he_link.prepare_input_files", mocks["prepare_input"]), - patch("assembler.common.counter.Counter.reset"), - patch("he_link.Loader.load_dinst_kernel_from_file", mocks["load_dinst"]), - patch( - "linker.instructions.BaseInstruction.dump_instructions_to_file", - mocks["dump_instructions"], - ), - patch("he_link.LinkedProgram", return_value=mocks["linked_program"]), - patch.object(mocks["linked_program"], "join_n_prune_dinst_kernels", mocks["join_dinst"]), - patch( - "assembler.memory_model.mem_info.MemInfo.from_dinstrs", - mocks["from_dinstrs"], - ), - patch( - "assembler.memory_model.mem_info.MemInfo.from_file_iter", - mocks["from_file_iter"], - ), - patch("linker.MemoryModel"), - patch("he_link.scan_variables", mocks["scan_variables"]), - patch("he_link.check_unused_variables", mocks["check_unused_variables"]), - patch( - "linker.kern_trace.TraceInfo.parse_kernel_ops_from_file", - mocks["parse_kernel_ops"], - ), - patch( - "os.path.isfile", - return_value=True, # Make all file existence checks return True - ), - patch("linker.kern_trace.remap_dinstrs_vars", mocks["remap_dinstrs_vars"]), - patch("he_link.update_input_prefixes", mocks["update_input_prefixes"]), - patch("he_link.remap_vars", mocks["remap_vars"]), - patch("he_link.initialize_memory_model", mocks["initialize_memory_model"]), - patch("he_link.Loader.flush_cache"), - patch( - "builtins.open", - mocks["mock_open"], # Mock all file opens to prevent actual file operations - ), - ): + with ExitStack() as stack: + stack.enter_context(patch("assembler.common.constants.convertBytes2Words", return_value=1024)) + stack.enter_context(patch("he_link.prepare_output_files", mocks["prepare_output"])) + stack.enter_context(patch("he_link.prepare_input_files", mocks["prepare_input"])) + stack.enter_context(patch("assembler.common.counter.Counter.reset")) + stack.enter_context(patch("he_link.Loader.load_dinst_kernel_from_file", mocks["load_dinst"])) + stack.enter_context( + patch( + "linker.instructions.BaseInstruction.dump_instructions_to_file", + mocks["dump_instructions"], + ) + ) + stack.enter_context(patch("he_link.LinkedProgram", return_value=mocks["linked_program"])) + stack.enter_context(patch.object(mocks["linked_program"], "join_n_prune_dinst_kernels", mocks["join_dinst"])) + stack.enter_context(patch("assembler.memory_model.mem_info.MemInfo.from_dinstrs", mocks["from_dinstrs"])) + stack.enter_context(patch("assembler.memory_model.mem_info.MemInfo.from_file_iter", mocks["from_file_iter"])) + stack.enter_context(patch("linker.MemoryModel")) + stack.enter_context(patch("he_link.scan_variables", mocks["scan_variables"])) + stack.enter_context(patch("he_link.check_unused_variables", mocks["check_unused_variables"])) + stack.enter_context( + patch( + "linker.kern_trace.TraceInfo.parse_kernel_ops_from_file", + mocks["parse_kernel_ops"], + ) + ) + stack.enter_context(patch("os.path.isfile", return_value=True)) + stack.enter_context(patch("linker.kern_trace.remap_dinstrs_vars", mocks["remap_dinstrs_vars"])) + stack.enter_context(patch("he_link.update_input_prefixes", mocks["update_input_prefixes"])) + stack.enter_context(patch("he_link.remap_vars", mocks["remap_vars"])) + stack.enter_context(patch("he_link.initialize_memory_model", mocks["initialize_memory_model"])) + stack.enter_context(patch("he_link.Loader.flush_cache")) + stack.enter_context(patch("builtins.open", mocks["mock_open"])) + # Mock link_kernels_to_files directly instead of patching the method - # This avoids the internal file operations while still tracking the call mocks["linked_program"].link_kernels_to_files = mocks["link_kernels"] - - # Run the main function with all patches in place he_link.main(mock_config, MagicMock()) # Assert pipeline is run as expected @@ -203,24 +193,26 @@ def test_warning_on_use_xinstfetch(self): mock_file_open = mock_open() # Act & Assert - with ( - patch("warnings.warn") as mock_warn, - patch("assembler.common.constants.convertBytes2Words", return_value=1024), - patch("he_link.prepare_output_files", return_value=mock_output_files), - patch("he_link.prepare_input_files", return_value=[]), - patch("assembler.common.counter.Counter.reset"), - patch( - "linker.steps.program_linker.LinkedProgram", - return_value=mock_linked_program, - ), - patch("assembler.memory_model.mem_info.MemInfo.from_file_iter"), - patch("linker.MemoryModel"), - patch("he_link.scan_variables"), - patch("he_link.check_unused_variables"), - patch("he_link.initialize_memory_model"), - patch("he_link.Loader.flush_cache"), - patch("builtins.open", mock_file_open), # Mock all file operations - ): + with ExitStack() as stack: + mock_warn = stack.enter_context(patch("warnings.warn")) + stack.enter_context(patch("assembler.common.constants.convertBytes2Words", return_value=1024)) + stack.enter_context(patch("he_link.prepare_output_files", return_value=mock_output_files)) + stack.enter_context(patch("he_link.prepare_input_files", return_value=[])) + stack.enter_context(patch("assembler.common.counter.Counter.reset")) + stack.enter_context( + patch( + "linker.steps.program_linker.LinkedProgram", + return_value=mock_linked_program, + ) + ) + stack.enter_context(patch("assembler.memory_model.mem_info.MemInfo.from_file_iter")) + stack.enter_context(patch("linker.MemoryModel")) + stack.enter_context(patch("he_link.scan_variables")) + stack.enter_context(patch("he_link.check_unused_variables")) + stack.enter_context(patch("he_link.initialize_memory_model")) + stack.enter_context(patch("he_link.Loader.flush_cache")) + stack.enter_context(patch("builtins.open", mock_file_open)) + # Set link_kernels_to_files method directly to avoid internal file operations mock_linked_program.link_kernels_to_files = mock_link_kernels From a5da355c32b2226cfd5b8f53859c8210be0bf943 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Thu, 21 Aug 2025 21:56:12 +0000 Subject: [PATCH 09/12] Format fix --- .../tests/integration_tests/test_he_link.py | 62 +++++++++---------- 1 file changed, 31 insertions(+), 31 deletions(-) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py index 3e84104f..886acdce 100644 --- a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py @@ -468,11 +468,11 @@ def _validate_minst_file_common(self, output_dir, output_prefix): # Assert no empty lines in between (except possibly the last one) assert tokens, f"Found empty line at index {i} in minst file" # Assert index is consecutive - assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {", ".join(tokens)}" + assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {', '.join(tokens)}" # Assert mload/mstore addresses are digits if tokens[1].startswith("mstore") or tokens[1].startswith("mload"): - assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line: {", ".join(tokens)}" - assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line: {", ".join(tokens)}" + assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line: {', '.join(tokens)}" + assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line: {', '.join(tokens)}" if tokens[1].startswith("mload") and tokens[3] == "0": # If mload address is 0, it should be a reset @@ -482,21 +482,21 @@ def _validate_minst_file_common(self, output_dir, output_prefix): # Assert previous instruction was an msyncc assert minstrs[i - 1][1].startswith( "msyncc" - ), f"Expected mstore to follow msyncc in line: {", ".join(tokens)} - prev: {", ".join(minstrs[i - 1])}" + ), f"Expected mstore to follow msyncc in line: {', '.join(tokens)} - prev: {', '.join(minstrs[i - 1])}" # Assert mstore's SPAD address is its cstore's SPAD address assert tokens[3] == last_cinst_spad, ( f"Expected mstore SPAD address {tokens[3]} to match last cstore SPAD address " - f"{last_cinst_spad} in line: {", ".join(tokens)}" + f"{last_cinst_spad} in line: {', '.join(tokens)}" ) elif tokens[1].startswith("msyncc"): target = tokens[2].strip() # Assert msyncc targets are digits - assert target.isdigit(), f"Expected msyncc target to be digit in line: {", ".join(tokens)}" + assert target.isdigit(), f"Expected msyncc target to be digit in line: {', '.join(tokens)}" # Assert targeted cinst is a cstore assert cinstrs[int(target)][1].startswith( "cstore" - ), f"Expected msyncc target {target} to be a cstore in line: {", ".join(tokens)}" + ), f"Expected msyncc target {target} to be a cstore in line: {', '.join(tokens)}" last_cinst_spad = cinstrs[int(target)][2].strip() return { @@ -533,17 +533,17 @@ def test_minst_output_trace_file_hbm_no_boundary(self, run_he_link_trace_hbm_no_ # Assert mload's hbm addresses are in expected set assert ( tokens[3] in dload_addresses - ), f"Expected mload HBM address {tokens[3]} to be in {dload_addresses} in line: {", ".join(tokens)}" + ), f"Expected mload HBM address {tokens[3]} to be in {dload_addresses} in line: {', '.join(tokens)}" # Assert spad address is not duplicate in mload sequence assert ( tokens[2] not in mload_spad_addresses - ), f"Expected mload SPAD address {tokens[2]} to be unique within mload sequence for line: {", ".join(tokens)}" + ), f"Expected mload SPAD address {tokens[2]} to be unique within mload sequence for line: {', '.join(tokens)}" mload_spad_addresses.add(tokens[2]) elif tokens[1].startswith("mstore"): # Assert mstore's hbm addresses are in expected set assert ( tokens[2] in dstore_addresses - ), f"Expected mstore HBM address {tokens[2]} to be in {dstore_addresses} in line: {", ".join(tokens)}" + ), f"Expected mstore HBM address {tokens[2]} to be in {dstore_addresses} in line: {', '.join(tokens)}" # Assert spad resets count matches 1 assert spad_address_resets == 1, f"Expected 1 spad resets but found {spad_address_resets} in minst file" @@ -574,7 +574,7 @@ def test_minst_output_trace_file_hbm_with_boundary(self, run_he_link_trace_hbm_w # Assert mload's hbm addresses are in expected set assert tokens[3] in ( dload_addresses | mstore_hbm_addresses - ), f"Expected mload HBM address {tokens[3]} to be in {dload_addresses | mstore_hbm_addresses} in line: {", ".join(tokens)}" + ), f"Expected mload HBM address {tokens[3]} to be in {dload_addresses | mstore_hbm_addresses} in line: {', '.join(tokens)}" # Reset tracking for each new kernel if tokens[3] == "0": mload_spad_addresses = set() @@ -582,7 +582,7 @@ def test_minst_output_trace_file_hbm_with_boundary(self, run_he_link_trace_hbm_w # Assert spad address is not duplicate in mload sequence assert ( tokens[2] not in mload_spad_addresses - ), f"Expected mload SPAD address {tokens[2]} to be unique within mload sequence for line: {", ".join(tokens)}" + ), f"Expected mload SPAD address {tokens[2]} to be unique within mload sequence for line: {', '.join(tokens)}" mload_spad_addresses.add(tokens[2]) elif tokens[1].startswith("mstore"): # Track intermediate mstore addresses for later mloads @@ -645,7 +645,7 @@ def _validate_cinst_file_hbm_common(self, output_dir, output_prefix): if tokens[1].startswith("csyncm"): csyncm_count += 1 # Assert csyncm targets are digits - assert tokens[2].isdigit(), f"Expected csyncm target to be digit in line: {", ".join(tokens)}" + assert tokens[2].isdigit(), f"Expected csyncm target to be digit in line: {', '.join(tokens)}" # Not second last instruction if i < len(cinstrs) - 2: target_minst = minstrs[int(tokens[2])] @@ -653,45 +653,45 @@ def _validate_cinst_file_hbm_common(self, output_dir, output_prefix): elif tokens[1] in ["cload", "bload", "nload", "bones"]: # Assert cload/bload/nload/bones SPAD address is digits - assert tokens[3].isdigit(), f"Expected SPAD address {tokens[3]} to be digit in line: {", ".join(tokens)}" + assert tokens[3].isdigit(), f"Expected SPAD address {tokens[3]} to be digit in line: {', '.join(tokens)}" # Assert SPAD address is in mload_addresses or cstore_spad_addresses assert tokens[3] in (mload_addresses | cstore_spad_addresses), ( f"Expected SPAD address {tokens[3]} to be in mload or mstore addresses " - f"in line: {", ".join(tokens)} cstore addresses: {cstore_spad_addresses}" + f"in line: {', '.join(tokens)} cstore addresses: {cstore_spad_addresses}" ) if tokens[1] in ["cload", "bload"] and tokens[3] in mload_addresses: # Assert cload/bload SPAD address is last mload's SPAD address assert tokens[3] == last_minstr_spad, ( f"Expected SPAD address {tokens[3]} to match last mload's SPAD " - f"address {last_minstr_spad} in line: {", ".join(tokens)}" + f"address {last_minstr_spad} in line: {', '.join(tokens)}" ) if tokens[1].startswith("bones") and tokens[2] in mload_addresses: # Assert bones SPAD address is last mload's SPAD address assert tokens[2] == last_minstr_spad, ( f"Expected SPAD address {tokens[2]} to match last mload's SPAD " - f"address {last_minstr_spad} in line: {", ".join(tokens)}" + f"address {last_minstr_spad} in line: {', '.join(tokens)}" ) elif tokens[1].startswith("cstore"): # Assert cstore SPAD address is digits - assert tokens[2].isdigit(), f"Expected SPAD address {tokens[2]} to be digit in line: {", ".join(tokens)}" + assert tokens[2].isdigit(), f"Expected SPAD address {tokens[2]} to be digit in line: {', '.join(tokens)}" if tokens[2] not in mstore_addresses: cstore_spad_addresses.add(tokens[2]) elif tokens[1].startswith("ifetch"): # Assert ifetch target is digits - assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line: {", ".join(tokens)}" + assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line: {', '.join(tokens)}" # Assert ifetch target is a valid xinst bundle assert ( int(tokens[2]) <= last_bundle - ), f"Expected ifetch target {tokens[2]} to be less than or equal to last bundle {last_bundle} in line: {", ".join(tokens)}" + ), f"Expected ifetch target {tokens[2]} to be less than or equal to last bundle {last_bundle} in line: {', '.join(tokens)}" # Assert no empty lines in between (except possibly the last one) assert tokens, "Found empty line in cinst file" # Assert index is consecutive - assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {", ".join(tokens)}" + assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {', '.join(tokens)}" # Assert last line contains cexit (termination instruction) last_tokens = cinstrs[-1] @@ -701,7 +701,7 @@ def _validate_cinst_file_hbm_common(self, output_dir, output_prefix): csyncm_tokens = cinstrs[-2] assert csyncm_tokens[1].startswith("csyncm"), "Expected second last line to contain csyncm instruction" # Assert last csyncm's target is digits - assert csyncm_tokens[2].isdigit(), f"Expected last csyncm target {csyncm_tokens[2]} to be digit in line: {", ".join(csyncm_tokens)}" + assert csyncm_tokens[2].isdigit(), f"Expected last csyncm target {csyncm_tokens[2]} to be digit in line: {', '.join(csyncm_tokens)}" # Assert last csyncm's target is the second last minst assert int(csyncm_tokens[2]) == len(minstrs) - 2, "Expected last csyncm target to be the second last minst" # Assert csyncm instructions are present in HBM mode (they should be kept) @@ -735,7 +735,7 @@ def test_cinst_output_trace_file_hbm_no_boundary(self, run_he_link_trace_hbm_no_ # Assert targeted minst is an mload assert minstrs[int(tokens[2])][1].startswith( "mload" - ), f"Expected csyncm target {tokens[2]} to be a mload in line: {", ".join(tokens)}" + ), f"Expected csyncm target {tokens[2]} to be a mload in line: {', '.join(tokens)}" @pytest.mark.parametrize( "fixture_dir", @@ -762,7 +762,7 @@ def test_cinst_output_trace_file_hbm_spad_boundary(self, run_he_link_trace_hbm_s # Assert targeted minst is an mload assert minstrs[int(tokens[2])][1].startswith( "mload" - ), f"Expected csyncm target {tokens[2]} to be a mload in line: {", ".join(tokens)}" + ), f"Expected csyncm target {tokens[2]} to be a mload in line: {', '.join(tokens)}" @pytest.mark.parametrize( "fixture_dir", @@ -789,7 +789,7 @@ def test_cinst_output_trace_file_hbm_with_boundary(self, run_he_link_trace_hbm_w assert minstrs[int(tokens[2])][1] in ( "mload", "mstore", - ), f"Expected csyncm target {tokens[2]} to be a mload in line: {", ".join(tokens)}" + ), f"Expected csyncm target {tokens[2]} to be a mload in line: {', '.join(tokens)}" elif tokens[1].startswith("cload"): if tokens[3] == "13": @@ -834,27 +834,27 @@ def test_cinst_output_trace_file_no_hbm(self, fixture_dir, run_fixture, request) # Assert no empty lines in between (except possibly the last one) assert tokens, f"Found empty line at index {i} in minst file" # Assert index is consecutive - assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line ({i}): {', '.join(tokens)}" + assert int(tokens[0]) == i, f"Expected index {i} but found {tokens[0]} in line: {', '.join(tokens)}" if tokens[1].startswith("cstore"): # Assert cstore's spad addresses are digits - assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line ({i}): {', '.join(tokens)}" + assert tokens[2].isdigit(), f"Expected address {tokens[2]} to be digit in line: {', '.join(tokens)}" cstore_spad_addresses.add(tokens[2]) elif tokens[1].startswith("cload"): # Assert cload's spad addresses are digits - assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line ({i}): {', '.join(tokens)}" + assert tokens[3].isdigit(), f"Expected address {tokens[3]} to be digit in line: {', '.join(tokens)}" # Assert cload's spad addresses are in expected set assert tokens[3] in (dload_addresses | cstore_spad_addresses), ( f"Expected cload SPAD address {tokens[3]} to be in {dload_addresses | cstore_spad_addresses} " - f"in line ({i}): {', '.join(tokens)}" + f"in line: {', '.join(tokens)}" ) elif tokens[1].startswith("ifetch"): # Assert ifetch target is digits - assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line ({i}): {', '.join(tokens)}" + assert tokens[2].isdigit(), f"Expected ifetch target {tokens[2]} to be digit in line: {', '.join(tokens)}" # Assert ifetch target is a valid xinst bundle assert int(tokens[2]) <= last_bundle, ( f"Expected ifetch target {tokens[2]} to be less than or equal to " - f"last bundle {last_bundle} in line ({i}): {', '.join(tokens)}" + f"last bundle {last_bundle} in line: {', '.join(tokens)}" ) # Assert last line contains cexit (termination instruction) From 0670c5865f5079381948083b1d6fb96c37dbf0fa Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Thu, 21 Aug 2025 22:07:06 +0000 Subject: [PATCH 10/12] Adding input fixtures --- ...i_add_add_mul_8192_l1_m2_program_trace.csv | 4 + .../hbm/bgv_add_8192_l1_m2_pisa.tw.cinst | 55 ++ .../hbm/bgv_add_8192_l1_m2_pisa.tw.mem | 19 + .../hbm/bgv_add_8192_l1_m2_pisa.tw.minst | 22 + .../hbm/bgv_add_8192_l1_m2_pisa.tw.xinst | 64 ++ .../hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst | 56 ++ .../hbm/bgv_mul_8192_l1_m2_pisa.tw.mem | 20 + .../hbm/bgv_mul_8192_l1_m2_pisa.tw.minst | 24 + .../hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst | 64 ++ .../no_hbm/bgv_add_8192_l1_m2_pisa.tw.cinst | 55 ++ .../no_hbm/bgv_add_8192_l1_m2_pisa.tw.mem | 19 + .../no_hbm/bgv_add_8192_l1_m2_pisa.tw.minst | 22 + .../no_hbm/bgv_add_8192_l1_m2_pisa.tw.xinst | 64 ++ .../no_hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst | 56 ++ .../no_hbm/bgv_mul_8192_l1_m2_pisa.tw.mem | 20 + .../no_hbm/bgv_mul_8192_l1_m2_pisa.tw.minst | 24 + .../no_hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst | 64 ++ ...ti_mul_relin_16384_l1_m2_program_trace.csv | 3 + .../hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst | 67 ++ .../hbm/bgv_mul_16384_l1_m2_pisa.tw.mem | 27 + .../hbm/bgv_mul_16384_l1_m2_pisa.tw.minst | 34 + .../hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst | 64 ++ .../hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst | 125 ++++ .../hbm/bgv_relin_16384_l1_m2_pisa.tw.mem | 39 + .../hbm/bgv_relin_16384_l1_m2_pisa.tw.minst | 44 ++ .../hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst | 704 ++++++++++++++++++ .../no_hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst | 67 ++ .../no_hbm/bgv_mul_16384_l1_m2_pisa.tw.mem | 27 + .../no_hbm/bgv_mul_16384_l1_m2_pisa.tw.minst | 34 + .../no_hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst | 64 ++ .../bgv_relin_16384_l1_m2_pisa.tw.cinst | 125 ++++ .../no_hbm/bgv_relin_16384_l1_m2_pisa.tw.mem | 39 + .../bgv_relin_16384_l1_m2_pisa.tw.minst | 44 ++ .../bgv_relin_16384_l1_m2_pisa.tw.xinst | 704 ++++++++++++++++++ 34 files changed, 2863 insertions(+) create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/bgv_multi_add_add_mul_8192_l1_m2_program_trace.csv create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.xinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.xinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/bgv_multi_mul_relin_16384_l1_m2_program_trace.csv create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.mem create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.minst create mode 100644 assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/bgv_multi_add_add_mul_8192_l1_m2_program_trace.csv b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/bgv_multi_add_add_mul_8192_l1_m2_program_trace.csv new file mode 100644 index 00000000..e9ed0c09 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/bgv_multi_add_add_mul_8192_l1_m2_program_trace.csv @@ -0,0 +1,4 @@ +instruction,scheme,poly_modulus_degree,keyrns_terms,arg0,arg1,arg2,arg3,arg4,arg5,arg6,arg7,arg8,arg9 +add,BGV,8192,2,ct4-2-1,ct0-2-1,ct1-2-1 +add,BGV,8192,2,ct5-2-1,ct2-2-1,ct3-2-1 +mul,BGV,8192,2,ct6-3-1,ct4-2-1,ct5-2-1 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..c185f264 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.cinst @@ -0,0 +1,55 @@ +0, csyncm, 4 # id: (0, 14) +1, bload, 0, 4, 0 # id: (0, 15); loading twid metadata for residuals [0, 64) +2, bload, 1, 4, 1 # id: (0, 16); loading twid metadata for residuals [0, 64) +3, bload, 2, 4, 2 # id: (0, 17); loading twid metadata for residuals [0, 64) +4, bload, 3, 4, 3 # id: (0, 18); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 19) +6, bload, 4, 5, 0 # id: (0, 20); loading twid metadata for residuals [0, 64) +7, bload, 5, 5, 1 # id: (0, 21); loading twid metadata for residuals [0, 64) +8, bload, 6, 5, 2 # id: (0, 22); loading twid metadata for residuals [0, 64) +9, bload, 7, 5, 3 # id: (0, 23); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 24) +11, bload, 8, 6, 0 # id: (0, 25); loading twid metadata for residuals [0, 64) +12, bload, 9, 6, 1 # id: (0, 26); loading twid metadata for residuals [0, 64) +13, bload, 10, 6, 2 # id: (0, 27); loading twid metadata for residuals [0, 64) +14, bload, 11, 6, 3 # id: (0, 28); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 29) +16, bload, 12, 7, 0 # id: (0, 30); loading twid metadata for residuals [0, 64) +17, bload, 13, 7, 1 # id: (0, 31); loading twid metadata for residuals [0, 64) +18, bload, 14, 7, 2 # id: (0, 32); loading twid metadata for residuals [0, 64) +19, bload, 15, 7, 3 # id: (0, 33); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 34) +21, bload, 16, 8, 0 # id: (0, 35); loading twid metadata for residuals [0, 64) +22, bload, 17, 8, 1 # id: (0, 36); loading twid metadata for residuals [0, 64) +23, bload, 18, 8, 2 # id: (0, 37); loading twid metadata for residuals [0, 64) +24, bload, 19, 8, 3 # id: (0, 38); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 39) +26, bload, 20, 9, 0 # id: (0, 40); loading twid metadata for residuals [0, 64) +27, bload, 21, 9, 1 # id: (0, 41); loading twid metadata for residuals [0, 64) +28, bload, 22, 9, 2 # id: (0, 42); loading twid metadata for residuals [0, 64) +29, bload, 23, 9, 3 # id: (0, 43); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 44) +31, bload, 24, 10, 0 # id: (0, 45); loading twid metadata for residuals [0, 64) +32, bload, 25, 10, 1 # id: (0, 46); loading twid metadata for residuals [0, 64) +33, bload, 26, 10, 2 # id: (0, 47); loading twid metadata for residuals [0, 64) +34, bload, 27, 10, 3 # id: (0, 48); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 49) +36, bload, 28, 11, 0 # id: (0, 50); loading twid metadata for residuals [0, 64) +37, bload, 29, 11, 1 # id: (0, 51); loading twid metadata for residuals [0, 64) +38, bload, 30, 11, 2 # id: (0, 52); loading twid metadata for residuals [0, 64) +39, bload, 31, 11, 3 # id: (0, 53); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 55) +41, bones, 12, 0 # id: (0, 56); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 59) +43, cload, r0b0, 13 # id: (1, 60); dep id: (1, 0); ct0_0_0_0 +44, csyncm, 14 # id: (1, 63) +45, cload, r1b0, 14 # id: (1, 64); dep id: (1, 0); ct1_0_0_0 +46, csyncm, 15 # id: (2, 67) +47, cload, r2b0, 15 # id: (2, 68); dep id: (2, 1); ct0_1_0_0 +48, csyncm, 16 # id: (2, 71) +49, cload, r3b0, 16 # id: (2, 72); dep id: (2, 1); ct1_1_0_0 +50, ifetch, 0 # id: (61, 134) +51, cstore, 17 # id: (1, 79); id: (1, 75); flushing output; variable "ct2_0_0_0": SPAD(17) <- r1b1; ct2_0_0_0 +52, cstore, 18 # id: (2, 81); id: (2, 77); flushing output; variable "ct2_1_0_0": SPAD(18) <- r3b1; ct2_1_0_0 +53, csyncm, 20 # id: (2, 139) +54, cexit # id: (54, 140) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..e3645604 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.mem @@ -0,0 +1,19 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_0_0_0 +dload, poly, 14, ct1_0_0_0 +dload, poly, 15, ct0_1_0_0 +dload, poly, 16, ct1_1_0_0 +dstore, ct2_0_0_0, 17 +dstore, ct2_1_0_0, 18 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..4a5f85f9 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.minst @@ -0,0 +1,22 @@ +0, mload, 0, ntt_auxiliary_table_0 # id: (0, 2) +1, mload, 1, ntt_routing_table_1 # id: (0, 3) +2, mload, 2, intt_auxiliary_table_2 # id: (0, 4) +3, mload, 3, intt_routing_table_3 # id: (0, 5) +4, mload, 4, twid_4 # id: (0, 6); loading twid metadata for residuals [0, 64) +5, mload, 5, twid_5 # id: (0, 7); loading twid metadata for residuals [0, 64) +6, mload, 6, twid_6 # id: (0, 8); loading twid metadata for residuals [0, 64) +7, mload, 7, twid_7 # id: (0, 9); loading twid metadata for residuals [0, 64) +8, mload, 8, twid_8 # id: (0, 10); loading twid metadata for residuals [0, 64) +9, mload, 9, twid_9 # id: (0, 11); loading twid metadata for residuals [0, 64) +10, mload, 10, twid_10 # id: (0, 12); loading twid metadata for residuals [0, 64) +11, mload, 11, twid_11 # id: (0, 13); loading twid metadata for residuals [0, 64) +12, mload, 12, ones_12 # id: (0, 54); loading ones metadata for residuals [0, 64) +13, mload, 13, ct0_0_0_0 # id: (1, 58); dep id: (1, 0) +14, mload, 14, ct1_0_0_0 # id: (1, 62); dep id: (1, 0) +15, mload, 15, ct0_1_0_0 # id: (2, 66); dep id: (2, 1) +16, mload, 16, ct1_1_0_0 # id: (2, 70); dep id: (2, 1) +17, msyncc, 51 # id: (1, 135) +18, mstore, ct2_0_0_0, 17 # id: (1, 136); id: (1, 79) - flushing; variable "ct2_0_0_0" <- SPAD(17) +19, msyncc, 52 # id: (2, 137) +20, mstore, ct2_1_0_0, 18 # id: (2, 138); id: (2, 81) - flushing; variable "ct2_1_0_0" <- SPAD(18) +21, msyncc, 55 # id: (54, 141); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..9fd619b2 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_add_8192_l1_m2_pisa.tw.xinst @@ -0,0 +1,64 @@ +F0, 1, move, r0b1, r0b0 # id: (1, 61); variable "ct0_0_0_0" +F0, 1, move, r0b2, r1b0 # id: (1, 65); variable "ct1_0_0_0" +F0, 2, move, r2b1, r2b0 # id: (2, 69); variable "ct0_1_0_0" +F0, 2, move, r1b2, r3b0 # id: (2, 73); variable "ct1_1_0_0" +F0, 1, nop, 2 # id: (1, 74); nop for not ready instr (1, 0) +F0, 1, add, r1b1, r0b1, r0b2, 0 # id: (1, 0); id: (1, 0) +F0, 2, nop, 0 # id: (2, 76); nop for not ready instr (2, 1) +F0, 2, add, r3b1, r2b1, r1b2, 0 # id: (2, 1); id: (2, 1) +F0, 1, nop, 2 # id: (1, 78); nop for not ready instr (1, 75) +F0, 1, xstore, r1b1 # id: (1, 75); flushing output; variable "ct2_0_0_0": SPAD(17) <- r1b1 +F0, 2, nop, 4 # id: (2, 80); nop for not ready instr (2, 77) +F0, 2, xstore, r3b1 # id: (2, 77); flushing output; variable "ct2_1_0_0": SPAD(18) <- r3b1 +F0, 0, bexit # id: (0, 82); terminating bundle 0: short bundle +F0, 0, nop, 0 # id: (0, 83) +F0, 0, nop, 0 # id: (0, 84) +F0, 0, nop, 0 # id: (0, 85) +F0, 0, nop, 0 # id: (0, 86) +F0, 0, nop, 0 # id: (0, 87) +F0, 0, nop, 0 # id: (0, 88) +F0, 0, nop, 0 # id: (0, 89) +F0, 0, nop, 0 # id: (0, 90) +F0, 0, nop, 0 # id: (0, 91) +F0, 0, nop, 0 # id: (0, 92) +F0, 0, nop, 0 # id: (0, 93) +F0, 0, nop, 0 # id: (0, 94) +F0, 0, nop, 0 # id: (0, 95) +F0, 0, nop, 0 # id: (0, 96) +F0, 0, nop, 0 # id: (0, 97) +F0, 0, nop, 0 # id: (0, 98) +F0, 0, nop, 0 # id: (0, 99) +F0, 0, nop, 0 # id: (0, 100) +F0, 0, nop, 0 # id: (0, 101) +F0, 0, nop, 0 # id: (0, 102) +F0, 0, nop, 0 # id: (0, 103) +F0, 0, nop, 0 # id: (0, 104) +F0, 0, nop, 0 # id: (0, 105) +F0, 0, nop, 0 # id: (0, 106) +F0, 0, nop, 0 # id: (0, 107) +F0, 0, nop, 0 # id: (0, 108) +F0, 0, nop, 0 # id: (0, 109) +F0, 0, nop, 0 # id: (0, 110) +F0, 0, nop, 0 # id: (0, 111) +F0, 0, nop, 0 # id: (0, 112) +F0, 0, nop, 0 # id: (0, 113) +F0, 0, nop, 0 # id: (0, 114) +F0, 0, nop, 0 # id: (0, 115) +F0, 0, nop, 0 # id: (0, 116) +F0, 0, nop, 0 # id: (0, 117) +F0, 0, nop, 0 # id: (0, 118) +F0, 0, nop, 0 # id: (0, 119) +F0, 0, nop, 0 # id: (0, 120) +F0, 0, nop, 0 # id: (0, 121) +F0, 0, nop, 0 # id: (0, 122) +F0, 0, nop, 0 # id: (0, 123) +F0, 0, nop, 0 # id: (0, 124) +F0, 0, nop, 0 # id: (0, 125) +F0, 0, nop, 0 # id: (0, 126) +F0, 0, nop, 0 # id: (0, 127) +F0, 0, nop, 0 # id: (0, 128) +F0, 0, nop, 0 # id: (0, 129) +F0, 0, nop, 0 # id: (0, 130) +F0, 0, nop, 0 # id: (0, 131) +F0, 0, nop, 0 # id: (0, 132) +F0, 0, nop, 0 # id: (0, 133) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..6d4f8094 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst @@ -0,0 +1,56 @@ +0, csyncm, 4 # id: (0, 16) +1, bload, 0, 4, 0 # id: (0, 17); loading twid metadata for residuals [0, 64) +2, bload, 1, 4, 1 # id: (0, 18); loading twid metadata for residuals [0, 64) +3, bload, 2, 4, 2 # id: (0, 19); loading twid metadata for residuals [0, 64) +4, bload, 3, 4, 3 # id: (0, 20); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 21) +6, bload, 4, 5, 0 # id: (0, 22); loading twid metadata for residuals [0, 64) +7, bload, 5, 5, 1 # id: (0, 23); loading twid metadata for residuals [0, 64) +8, bload, 6, 5, 2 # id: (0, 24); loading twid metadata for residuals [0, 64) +9, bload, 7, 5, 3 # id: (0, 25); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 26) +11, bload, 8, 6, 0 # id: (0, 27); loading twid metadata for residuals [0, 64) +12, bload, 9, 6, 1 # id: (0, 28); loading twid metadata for residuals [0, 64) +13, bload, 10, 6, 2 # id: (0, 29); loading twid metadata for residuals [0, 64) +14, bload, 11, 6, 3 # id: (0, 30); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 31) +16, bload, 12, 7, 0 # id: (0, 32); loading twid metadata for residuals [0, 64) +17, bload, 13, 7, 1 # id: (0, 33); loading twid metadata for residuals [0, 64) +18, bload, 14, 7, 2 # id: (0, 34); loading twid metadata for residuals [0, 64) +19, bload, 15, 7, 3 # id: (0, 35); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 36) +21, bload, 16, 8, 0 # id: (0, 37); loading twid metadata for residuals [0, 64) +22, bload, 17, 8, 1 # id: (0, 38); loading twid metadata for residuals [0, 64) +23, bload, 18, 8, 2 # id: (0, 39); loading twid metadata for residuals [0, 64) +24, bload, 19, 8, 3 # id: (0, 40); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 41) +26, bload, 20, 9, 0 # id: (0, 42); loading twid metadata for residuals [0, 64) +27, bload, 21, 9, 1 # id: (0, 43); loading twid metadata for residuals [0, 64) +28, bload, 22, 9, 2 # id: (0, 44); loading twid metadata for residuals [0, 64) +29, bload, 23, 9, 3 # id: (0, 45); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 46) +31, bload, 24, 10, 0 # id: (0, 47); loading twid metadata for residuals [0, 64) +32, bload, 25, 10, 1 # id: (0, 48); loading twid metadata for residuals [0, 64) +33, bload, 26, 10, 2 # id: (0, 49); loading twid metadata for residuals [0, 64) +34, bload, 27, 10, 3 # id: (0, 50); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 51) +36, bload, 28, 11, 0 # id: (0, 52); loading twid metadata for residuals [0, 64) +37, bload, 29, 11, 1 # id: (0, 53); loading twid metadata for residuals [0, 64) +38, bload, 30, 11, 2 # id: (0, 54); loading twid metadata for residuals [0, 64) +39, bload, 31, 11, 3 # id: (0, 55); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 57) +41, bones, 12, 0 # id: (0, 58); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 61) +43, cload, r0b0, 13 # id: (1, 62); dep id: (1, 0); ct0_0_0_0 +44, csyncm, 14 # id: (1, 65) +45, cload, r1b0, 14 # id: (1, 66); dep id: (1, 0); ct1_1_0_0 +46, csyncm, 15 # id: (2, 69) +47, cload, r2b0, 15 # id: (2, 70); dep id: (2, 1); ct1_0_0_0 +48, csyncm, 16 # id: (3, 75) +49, cload, r3b0, 17 # id: (3, 76); dep id: (3, 2); ct0_1_0_0 +50, ifetch, 0 # id: (63, 135) +51, cstore, 16 # id: (2, 79); id: (2, 73); flushing output; variable "ct2_0_0_0": SPAD(16) <- r2b1; ct2_0_0_0 +52, cstore, 18 # id: (4, 83); id: (4, 80); flushing output; variable "ct2_1_0_0": SPAD(18) <- r0b3; ct2_1_0_0 +53, cstore, 19 # id: (3, 85); id: (3, 81); flushing output; variable "ct2_2_0_0": SPAD(19) <- r3b1; ct2_2_0_0 +54, csyncm, 22 # id: (3, 142) +55, cexit # id: (55, 143) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..b63d1e6d --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.mem @@ -0,0 +1,20 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_0_0_0 +dload, poly, 14, ct1_1_0_0 +dload, poly, 15, ct1_0_0_0 +dload, poly, 16, ct0_1_0_0 +dstore, ct2_0_0_0, 17 +dstore, ct2_2_0_0, 18 +dstore, ct2_1_0_0, 19 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..a3d0612f --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.minst @@ -0,0 +1,24 @@ +0, mload, 0, ntt_auxiliary_table_0 # id: (0, 4) +1, mload, 1, ntt_routing_table_1 # id: (0, 5) +2, mload, 2, intt_auxiliary_table_2 # id: (0, 6) +3, mload, 3, intt_routing_table_3 # id: (0, 7) +4, mload, 4, twid_4 # id: (0, 8); loading twid metadata for residuals [0, 64) +5, mload, 5, twid_5 # id: (0, 9); loading twid metadata for residuals [0, 64) +6, mload, 6, twid_6 # id: (0, 10); loading twid metadata for residuals [0, 64) +7, mload, 7, twid_7 # id: (0, 11); loading twid metadata for residuals [0, 64) +8, mload, 8, twid_8 # id: (0, 12); loading twid metadata for residuals [0, 64) +9, mload, 9, twid_9 # id: (0, 13); loading twid metadata for residuals [0, 64) +10, mload, 10, twid_10 # id: (0, 14); loading twid metadata for residuals [0, 64) +11, mload, 11, twid_11 # id: (0, 15); loading twid metadata for residuals [0, 64) +12, mload, 12, ones_12 # id: (0, 56); loading ones metadata for residuals [0, 64) +13, mload, 13, ct0_0_0_0 # id: (1, 60); dep id: (1, 0) +14, mload, 14, ct1_1_0_0 # id: (1, 64); dep id: (1, 0) +15, mload, 15, ct1_0_0_0 # id: (2, 68); dep id: (2, 1) +16, mload, 17, ct0_1_0_0 # id: (3, 74); dep id: (3, 2) +17, msyncc, 51 # id: (2, 136) +18, mstore, ct2_0_0_0, 16 # id: (2, 137); id: (2, 79) - flushing; variable "ct2_0_0_0" <- SPAD(16) +19, msyncc, 52 # id: (4, 138) +20, mstore, ct2_1_0_0, 18 # id: (4, 139); id: (4, 83) - flushing; variable "ct2_1_0_0" <- SPAD(18) +21, msyncc, 53 # id: (3, 140) +22, mstore, ct2_2_0_0, 19 # id: (3, 141); id: (3, 85) - flushing; variable "ct2_2_0_0" <- SPAD(19) +23, msyncc, 56 # id: (55, 144); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..55d73e8f --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst @@ -0,0 +1,64 @@ +F0, 1, move, r0b2, r0b0 # id: (1, 63); variable "ct0_0_0_0" +F0, 1, move, r0b1, r1b0 # id: (1, 67); variable "ct1_1_0_0" +F0, 2, move, r1b1, r2b0 # id: (2, 71); variable "ct1_0_0_0" +F0, 1, nop, 3 # id: (1, 72); nop for not ready instr (1, 0) +F0, 1, mul, r0b3, r0b2, r0b1, 0 # id: (1, 0); id: (1, 0) +F0, 2, mul, r2b1, r0b2, r1b1, 0 # id: (2, 1); id: (2, 1) +F0, 3, move, r1b2, r3b0 # id: (3, 77); variable "ct0_1_0_0" +F0, 2, nop, 3 # id: (2, 78); nop for not ready instr (2, 73) +F0, 2, xstore, r2b1 # id: (2, 73); flushing output; variable "ct2_0_0_0": SPAD(16) <- r2b1 +F0, 4, mac, r0b3, r0b3, r1b2, r1b1, 0 # id: (4, 3); id: (4, 3) +F0, 3, mul, r3b1, r1b2, r0b1, 0 # id: (3, 2); id: (3, 2) +F0, 4, nop, 3 # id: (4, 82); nop for not ready instr (4, 80) +F0, 4, xstore, r0b3 # id: (4, 80); flushing output; variable "ct2_1_0_0": SPAD(18) <- r0b3 +F0, 3, nop, 4 # id: (3, 84); nop for not ready instr (3, 81) +F0, 3, xstore, r3b1 # id: (3, 81); flushing output; variable "ct2_2_0_0": SPAD(19) <- r3b1 +F0, 0, bexit # id: (0, 86); terminating bundle 0: short bundle +F0, 0, nop, 0 # id: (0, 87) +F0, 0, nop, 0 # id: (0, 88) +F0, 0, nop, 0 # id: (0, 89) +F0, 0, nop, 0 # id: (0, 90) +F0, 0, nop, 0 # id: (0, 91) +F0, 0, nop, 0 # id: (0, 92) +F0, 0, nop, 0 # id: (0, 93) +F0, 0, nop, 0 # id: (0, 94) +F0, 0, nop, 0 # id: (0, 95) +F0, 0, nop, 0 # id: (0, 96) +F0, 0, nop, 0 # id: (0, 97) +F0, 0, nop, 0 # id: (0, 98) +F0, 0, nop, 0 # id: (0, 99) +F0, 0, nop, 0 # id: (0, 100) +F0, 0, nop, 0 # id: (0, 101) +F0, 0, nop, 0 # id: (0, 102) +F0, 0, nop, 0 # id: (0, 103) +F0, 0, nop, 0 # id: (0, 104) +F0, 0, nop, 0 # id: (0, 105) +F0, 0, nop, 0 # id: (0, 106) +F0, 0, nop, 0 # id: (0, 107) +F0, 0, nop, 0 # id: (0, 108) +F0, 0, nop, 0 # id: (0, 109) +F0, 0, nop, 0 # id: (0, 110) +F0, 0, nop, 0 # id: (0, 111) +F0, 0, nop, 0 # id: (0, 112) +F0, 0, nop, 0 # id: (0, 113) +F0, 0, nop, 0 # id: (0, 114) +F0, 0, nop, 0 # id: (0, 115) +F0, 0, nop, 0 # id: (0, 116) +F0, 0, nop, 0 # id: (0, 117) +F0, 0, nop, 0 # id: (0, 118) +F0, 0, nop, 0 # id: (0, 119) +F0, 0, nop, 0 # id: (0, 120) +F0, 0, nop, 0 # id: (0, 121) +F0, 0, nop, 0 # id: (0, 122) +F0, 0, nop, 0 # id: (0, 123) +F0, 0, nop, 0 # id: (0, 124) +F0, 0, nop, 0 # id: (0, 125) +F0, 0, nop, 0 # id: (0, 126) +F0, 0, nop, 0 # id: (0, 127) +F0, 0, nop, 0 # id: (0, 128) +F0, 0, nop, 0 # id: (0, 129) +F0, 0, nop, 0 # id: (0, 130) +F0, 0, nop, 0 # id: (0, 131) +F0, 0, nop, 0 # id: (0, 132) +F0, 0, nop, 0 # id: (0, 133) +F0, 0, nop, 0 # id: (0, 134) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..5510d1aa --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.cinst @@ -0,0 +1,55 @@ +0, csyncm, 4 # id: (0, 14) +1, bload, 0, twid_4, 0 # id: (0, 15); loading twid metadata for residuals [0, 64) +2, bload, 1, twid_4, 1 # id: (0, 16); loading twid metadata for residuals [0, 64) +3, bload, 2, twid_4, 2 # id: (0, 17); loading twid metadata for residuals [0, 64) +4, bload, 3, twid_4, 3 # id: (0, 18); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 19) +6, bload, 4, twid_5, 0 # id: (0, 20); loading twid metadata for residuals [0, 64) +7, bload, 5, twid_5, 1 # id: (0, 21); loading twid metadata for residuals [0, 64) +8, bload, 6, twid_5, 2 # id: (0, 22); loading twid metadata for residuals [0, 64) +9, bload, 7, twid_5, 3 # id: (0, 23); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 24) +11, bload, 8, twid_6, 0 # id: (0, 25); loading twid metadata for residuals [0, 64) +12, bload, 9, twid_6, 1 # id: (0, 26); loading twid metadata for residuals [0, 64) +13, bload, 10, twid_6, 2 # id: (0, 27); loading twid metadata for residuals [0, 64) +14, bload, 11, twid_6, 3 # id: (0, 28); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 29) +16, bload, 12, twid_7, 0 # id: (0, 30); loading twid metadata for residuals [0, 64) +17, bload, 13, twid_7, 1 # id: (0, 31); loading twid metadata for residuals [0, 64) +18, bload, 14, twid_7, 2 # id: (0, 32); loading twid metadata for residuals [0, 64) +19, bload, 15, twid_7, 3 # id: (0, 33); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 34) +21, bload, 16, twid_8, 0 # id: (0, 35); loading twid metadata for residuals [0, 64) +22, bload, 17, twid_8, 1 # id: (0, 36); loading twid metadata for residuals [0, 64) +23, bload, 18, twid_8, 2 # id: (0, 37); loading twid metadata for residuals [0, 64) +24, bload, 19, twid_8, 3 # id: (0, 38); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 39) +26, bload, 20, twid_9, 0 # id: (0, 40); loading twid metadata for residuals [0, 64) +27, bload, 21, twid_9, 1 # id: (0, 41); loading twid metadata for residuals [0, 64) +28, bload, 22, twid_9, 2 # id: (0, 42); loading twid metadata for residuals [0, 64) +29, bload, 23, twid_9, 3 # id: (0, 43); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 44) +31, bload, 24, twid_10, 0 # id: (0, 45); loading twid metadata for residuals [0, 64) +32, bload, 25, twid_10, 1 # id: (0, 46); loading twid metadata for residuals [0, 64) +33, bload, 26, twid_10, 2 # id: (0, 47); loading twid metadata for residuals [0, 64) +34, bload, 27, twid_10, 3 # id: (0, 48); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 49) +36, bload, 28, twid_11, 0 # id: (0, 50); loading twid metadata for residuals [0, 64) +37, bload, 29, twid_11, 1 # id: (0, 51); loading twid metadata for residuals [0, 64) +38, bload, 30, twid_11, 2 # id: (0, 52); loading twid metadata for residuals [0, 64) +39, bload, 31, twid_11, 3 # id: (0, 53); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 55) +41, bones, ones_12, 0 # id: (0, 56); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 59) +43, cload, r0b0, ct0_0_0_0 # id: (1, 60); dep id: (1, 0); ct0_0_0_0 +44, csyncm, 14 # id: (1, 63) +45, cload, r1b0, ct1_0_0_0 # id: (1, 64); dep id: (1, 0); ct1_0_0_0 +46, csyncm, 15 # id: (2, 67) +47, cload, r2b0, ct0_1_0_0 # id: (2, 68); dep id: (2, 1); ct0_1_0_0 +48, csyncm, 16 # id: (2, 71) +49, cload, r3b0, ct1_1_0_0 # id: (2, 72); dep id: (2, 1); ct1_1_0_0 +50, ifetch, 0 # id: (61, 134) +51, cstore, ct2_0_0_0 # id: (1, 79); id: (1, 75); flushing output; variable "ct2_0_0_0": SPAD(17) <- r1b1; ct2_0_0_0 +52, cstore, ct2_1_0_0 # id: (2, 81); id: (2, 77); flushing output; variable "ct2_1_0_0": SPAD(18) <- r3b1; ct2_1_0_0 +53, csyncm, 20 # id: (2, 139) +54, cexit # id: (54, 140) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..e3645604 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.mem @@ -0,0 +1,19 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_0_0_0 +dload, poly, 14, ct1_0_0_0 +dload, poly, 15, ct0_1_0_0 +dload, poly, 16, ct1_1_0_0 +dstore, ct2_0_0_0, 17 +dstore, ct2_1_0_0, 18 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..0c428f1e --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.minst @@ -0,0 +1,22 @@ +0, mload, ntt_auxiliary_table_0, ntt_auxiliary_table_0 # id: (0, 2) +1, mload, ntt_routing_table_1, ntt_routing_table_1 # id: (0, 3) +2, mload, intt_auxiliary_table_2, intt_auxiliary_table_2 # id: (0, 4) +3, mload, intt_routing_table_3, intt_routing_table_3 # id: (0, 5) +4, mload, twid_4, twid_4 # id: (0, 6); loading twid metadata for residuals [0, 64) +5, mload, twid_5, twid_5 # id: (0, 7); loading twid metadata for residuals [0, 64) +6, mload, twid_6, twid_6 # id: (0, 8); loading twid metadata for residuals [0, 64) +7, mload, twid_7, twid_7 # id: (0, 9); loading twid metadata for residuals [0, 64) +8, mload, twid_8, twid_8 # id: (0, 10); loading twid metadata for residuals [0, 64) +9, mload, twid_9, twid_9 # id: (0, 11); loading twid metadata for residuals [0, 64) +10, mload, twid_10, twid_10 # id: (0, 12); loading twid metadata for residuals [0, 64) +11, mload, twid_11, twid_11 # id: (0, 13); loading twid metadata for residuals [0, 64) +12, mload, ones_12, ones_12 # id: (0, 54); loading ones metadata for residuals [0, 64) +13, mload, ct0_0_0_0, ct0_0_0_0 # id: (1, 58); dep id: (1, 0) +14, mload, ct1_0_0_0, ct1_0_0_0 # id: (1, 62); dep id: (1, 0) +15, mload, ct0_1_0_0, ct0_1_0_0 # id: (2, 66); dep id: (2, 1) +16, mload, ct1_1_0_0, ct1_1_0_0 # id: (2, 70); dep id: (2, 1) +17, msyncc, 51 # id: (1, 135) +18, mstore, ct2_0_0_0, 17 # id: (1, 136); id: (1, 79) - flushing; variable "ct2_0_0_0" <- SPAD(17) +19, msyncc, 52 # id: (2, 137) +20, mstore, ct2_1_0_0, 18 # id: (2, 138); id: (2, 81) - flushing; variable "ct2_1_0_0" <- SPAD(18) +21, msyncc, 55 # id: (54, 141); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..9fd619b2 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_add_8192_l1_m2_pisa.tw.xinst @@ -0,0 +1,64 @@ +F0, 1, move, r0b1, r0b0 # id: (1, 61); variable "ct0_0_0_0" +F0, 1, move, r0b2, r1b0 # id: (1, 65); variable "ct1_0_0_0" +F0, 2, move, r2b1, r2b0 # id: (2, 69); variable "ct0_1_0_0" +F0, 2, move, r1b2, r3b0 # id: (2, 73); variable "ct1_1_0_0" +F0, 1, nop, 2 # id: (1, 74); nop for not ready instr (1, 0) +F0, 1, add, r1b1, r0b1, r0b2, 0 # id: (1, 0); id: (1, 0) +F0, 2, nop, 0 # id: (2, 76); nop for not ready instr (2, 1) +F0, 2, add, r3b1, r2b1, r1b2, 0 # id: (2, 1); id: (2, 1) +F0, 1, nop, 2 # id: (1, 78); nop for not ready instr (1, 75) +F0, 1, xstore, r1b1 # id: (1, 75); flushing output; variable "ct2_0_0_0": SPAD(17) <- r1b1 +F0, 2, nop, 4 # id: (2, 80); nop for not ready instr (2, 77) +F0, 2, xstore, r3b1 # id: (2, 77); flushing output; variable "ct2_1_0_0": SPAD(18) <- r3b1 +F0, 0, bexit # id: (0, 82); terminating bundle 0: short bundle +F0, 0, nop, 0 # id: (0, 83) +F0, 0, nop, 0 # id: (0, 84) +F0, 0, nop, 0 # id: (0, 85) +F0, 0, nop, 0 # id: (0, 86) +F0, 0, nop, 0 # id: (0, 87) +F0, 0, nop, 0 # id: (0, 88) +F0, 0, nop, 0 # id: (0, 89) +F0, 0, nop, 0 # id: (0, 90) +F0, 0, nop, 0 # id: (0, 91) +F0, 0, nop, 0 # id: (0, 92) +F0, 0, nop, 0 # id: (0, 93) +F0, 0, nop, 0 # id: (0, 94) +F0, 0, nop, 0 # id: (0, 95) +F0, 0, nop, 0 # id: (0, 96) +F0, 0, nop, 0 # id: (0, 97) +F0, 0, nop, 0 # id: (0, 98) +F0, 0, nop, 0 # id: (0, 99) +F0, 0, nop, 0 # id: (0, 100) +F0, 0, nop, 0 # id: (0, 101) +F0, 0, nop, 0 # id: (0, 102) +F0, 0, nop, 0 # id: (0, 103) +F0, 0, nop, 0 # id: (0, 104) +F0, 0, nop, 0 # id: (0, 105) +F0, 0, nop, 0 # id: (0, 106) +F0, 0, nop, 0 # id: (0, 107) +F0, 0, nop, 0 # id: (0, 108) +F0, 0, nop, 0 # id: (0, 109) +F0, 0, nop, 0 # id: (0, 110) +F0, 0, nop, 0 # id: (0, 111) +F0, 0, nop, 0 # id: (0, 112) +F0, 0, nop, 0 # id: (0, 113) +F0, 0, nop, 0 # id: (0, 114) +F0, 0, nop, 0 # id: (0, 115) +F0, 0, nop, 0 # id: (0, 116) +F0, 0, nop, 0 # id: (0, 117) +F0, 0, nop, 0 # id: (0, 118) +F0, 0, nop, 0 # id: (0, 119) +F0, 0, nop, 0 # id: (0, 120) +F0, 0, nop, 0 # id: (0, 121) +F0, 0, nop, 0 # id: (0, 122) +F0, 0, nop, 0 # id: (0, 123) +F0, 0, nop, 0 # id: (0, 124) +F0, 0, nop, 0 # id: (0, 125) +F0, 0, nop, 0 # id: (0, 126) +F0, 0, nop, 0 # id: (0, 127) +F0, 0, nop, 0 # id: (0, 128) +F0, 0, nop, 0 # id: (0, 129) +F0, 0, nop, 0 # id: (0, 130) +F0, 0, nop, 0 # id: (0, 131) +F0, 0, nop, 0 # id: (0, 132) +F0, 0, nop, 0 # id: (0, 133) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..1a2b904c --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.cinst @@ -0,0 +1,56 @@ +0, csyncm, 4 # id: (0, 16) +1, bload, 0, twid_4, 0 # id: (0, 17); loading twid metadata for residuals [0, 64) +2, bload, 1, twid_4, 1 # id: (0, 18); loading twid metadata for residuals [0, 64) +3, bload, 2, twid_4, 2 # id: (0, 19); loading twid metadata for residuals [0, 64) +4, bload, 3, twid_4, 3 # id: (0, 20); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 21) +6, bload, 4, twid_5, 0 # id: (0, 22); loading twid metadata for residuals [0, 64) +7, bload, 5, twid_5, 1 # id: (0, 23); loading twid metadata for residuals [0, 64) +8, bload, 6, twid_5, 2 # id: (0, 24); loading twid metadata for residuals [0, 64) +9, bload, 7, twid_5, 3 # id: (0, 25); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 26) +11, bload, 8, twid_6, 0 # id: (0, 27); loading twid metadata for residuals [0, 64) +12, bload, 9, twid_6, 1 # id: (0, 28); loading twid metadata for residuals [0, 64) +13, bload, 10, twid_6, 2 # id: (0, 29); loading twid metadata for residuals [0, 64) +14, bload, 11, twid_6, 3 # id: (0, 30); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 31) +16, bload, 12, twid_7, 0 # id: (0, 32); loading twid metadata for residuals [0, 64) +17, bload, 13, twid_7, 1 # id: (0, 33); loading twid metadata for residuals [0, 64) +18, bload, 14, twid_7, 2 # id: (0, 34); loading twid metadata for residuals [0, 64) +19, bload, 15, twid_7, 3 # id: (0, 35); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 36) +21, bload, 16, twid_8, 0 # id: (0, 37); loading twid metadata for residuals [0, 64) +22, bload, 17, twid_8, 1 # id: (0, 38); loading twid metadata for residuals [0, 64) +23, bload, 18, twid_8, 2 # id: (0, 39); loading twid metadata for residuals [0, 64) +24, bload, 19, twid_8, 3 # id: (0, 40); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 41) +26, bload, 20, twid_9, 0 # id: (0, 42); loading twid metadata for residuals [0, 64) +27, bload, 21, twid_9, 1 # id: (0, 43); loading twid metadata for residuals [0, 64) +28, bload, 22, twid_9, 2 # id: (0, 44); loading twid metadata for residuals [0, 64) +29, bload, 23, twid_9, 3 # id: (0, 45); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 46) +31, bload, 24, twid_10, 0 # id: (0, 47); loading twid metadata for residuals [0, 64) +32, bload, 25, twid_10, 1 # id: (0, 48); loading twid metadata for residuals [0, 64) +33, bload, 26, twid_10, 2 # id: (0, 49); loading twid metadata for residuals [0, 64) +34, bload, 27, twid_10, 3 # id: (0, 50); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 51) +36, bload, 28, twid_11, 0 # id: (0, 52); loading twid metadata for residuals [0, 64) +37, bload, 29, twid_11, 1 # id: (0, 53); loading twid metadata for residuals [0, 64) +38, bload, 30, twid_11, 2 # id: (0, 54); loading twid metadata for residuals [0, 64) +39, bload, 31, twid_11, 3 # id: (0, 55); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 57) +41, bones, ones_12, 0 # id: (0, 58); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 61) +43, cload, r0b0, ct0_0_0_0 # id: (1, 62); dep id: (1, 0); ct0_0_0_0 +44, csyncm, 14 # id: (1, 65) +45, cload, r1b0, ct1_1_0_0 # id: (1, 66); dep id: (1, 0); ct1_1_0_0 +46, csyncm, 15 # id: (2, 69) +47, cload, r2b0, ct1_0_0_0 # id: (2, 70); dep id: (2, 1); ct1_0_0_0 +48, csyncm, 16 # id: (3, 75) +49, cload, r3b0, ct0_1_0_0 # id: (3, 76); dep id: (3, 2); ct0_1_0_0 +50, ifetch, 0 # id: (63, 135) +51, cstore, ct2_0_0_0 # id: (2, 79); id: (2, 73); flushing output; variable "ct2_0_0_0": SPAD(16) <- r2b1; ct2_0_0_0 +52, cstore, ct2_1_0_0 # id: (4, 83); id: (4, 80); flushing output; variable "ct2_1_0_0": SPAD(18) <- r0b3; ct2_1_0_0 +53, cstore, ct2_2_0_0 # id: (3, 85); id: (3, 81); flushing output; variable "ct2_2_0_0": SPAD(19) <- r3b1; ct2_2_0_0 +54, csyncm, 22 # id: (3, 142) +55, cexit # id: (55, 143) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..b63d1e6d --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.mem @@ -0,0 +1,20 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_0_0_0 +dload, poly, 14, ct1_1_0_0 +dload, poly, 15, ct1_0_0_0 +dload, poly, 16, ct0_1_0_0 +dstore, ct2_0_0_0, 17 +dstore, ct2_2_0_0, 18 +dstore, ct2_1_0_0, 19 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..340cb942 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.minst @@ -0,0 +1,24 @@ +0, mload, ntt_auxiliary_table_0, ntt_auxiliary_table_0 # id: (0, 4) +1, mload, ntt_routing_table_1, ntt_routing_table_1 # id: (0, 5) +2, mload, intt_auxiliary_table_2, intt_auxiliary_table_2 # id: (0, 6) +3, mload, intt_routing_table_3, intt_routing_table_3 # id: (0, 7) +4, mload, twid_4, twid_4 # id: (0, 8); loading twid metadata for residuals [0, 64) +5, mload, twid_5, twid_5 # id: (0, 9); loading twid metadata for residuals [0, 64) +6, mload, twid_6, twid_6 # id: (0, 10); loading twid metadata for residuals [0, 64) +7, mload, twid_7, twid_7 # id: (0, 11); loading twid metadata for residuals [0, 64) +8, mload, twid_8, twid_8 # id: (0, 12); loading twid metadata for residuals [0, 64) +9, mload, twid_9, twid_9 # id: (0, 13); loading twid metadata for residuals [0, 64) +10, mload, twid_10, twid_10 # id: (0, 14); loading twid metadata for residuals [0, 64) +11, mload, twid_11, twid_11 # id: (0, 15); loading twid metadata for residuals [0, 64) +12, mload, ones_12, ones_12 # id: (0, 56); loading ones metadata for residuals [0, 64) +13, mload, ct0_0_0_0, ct0_0_0_0 # id: (1, 60); dep id: (1, 0) +14, mload, ct1_1_0_0, ct1_1_0_0 # id: (1, 64); dep id: (1, 0) +15, mload, ct1_0_0_0, ct1_0_0_0 # id: (2, 68); dep id: (2, 1) +16, mload, ct0_1_0_0, ct0_1_0_0 # id: (3, 74); dep id: (3, 2) +17, msyncc, 51 # id: (2, 136) +18, mstore, ct2_0_0_0, 16 # id: (2, 137); id: (2, 79) - flushing; variable "ct2_0_0_0" <- SPAD(16) +19, msyncc, 52 # id: (4, 138) +20, mstore, ct2_1_0_0, 18 # id: (4, 139); id: (4, 83) - flushing; variable "ct2_1_0_0" <- SPAD(18) +21, msyncc, 53 # id: (3, 140) +22, mstore, ct2_2_0_0, 19 # id: (3, 141); id: (3, 85) - flushing; variable "ct2_2_0_0" <- SPAD(19) +23, msyncc, 56 # id: (55, 144); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..55d73e8f --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_add_add_mul_8192_l1_m2/no_hbm/bgv_mul_8192_l1_m2_pisa.tw.xinst @@ -0,0 +1,64 @@ +F0, 1, move, r0b2, r0b0 # id: (1, 63); variable "ct0_0_0_0" +F0, 1, move, r0b1, r1b0 # id: (1, 67); variable "ct1_1_0_0" +F0, 2, move, r1b1, r2b0 # id: (2, 71); variable "ct1_0_0_0" +F0, 1, nop, 3 # id: (1, 72); nop for not ready instr (1, 0) +F0, 1, mul, r0b3, r0b2, r0b1, 0 # id: (1, 0); id: (1, 0) +F0, 2, mul, r2b1, r0b2, r1b1, 0 # id: (2, 1); id: (2, 1) +F0, 3, move, r1b2, r3b0 # id: (3, 77); variable "ct0_1_0_0" +F0, 2, nop, 3 # id: (2, 78); nop for not ready instr (2, 73) +F0, 2, xstore, r2b1 # id: (2, 73); flushing output; variable "ct2_0_0_0": SPAD(16) <- r2b1 +F0, 4, mac, r0b3, r0b3, r1b2, r1b1, 0 # id: (4, 3); id: (4, 3) +F0, 3, mul, r3b1, r1b2, r0b1, 0 # id: (3, 2); id: (3, 2) +F0, 4, nop, 3 # id: (4, 82); nop for not ready instr (4, 80) +F0, 4, xstore, r0b3 # id: (4, 80); flushing output; variable "ct2_1_0_0": SPAD(18) <- r0b3 +F0, 3, nop, 4 # id: (3, 84); nop for not ready instr (3, 81) +F0, 3, xstore, r3b1 # id: (3, 81); flushing output; variable "ct2_2_0_0": SPAD(19) <- r3b1 +F0, 0, bexit # id: (0, 86); terminating bundle 0: short bundle +F0, 0, nop, 0 # id: (0, 87) +F0, 0, nop, 0 # id: (0, 88) +F0, 0, nop, 0 # id: (0, 89) +F0, 0, nop, 0 # id: (0, 90) +F0, 0, nop, 0 # id: (0, 91) +F0, 0, nop, 0 # id: (0, 92) +F0, 0, nop, 0 # id: (0, 93) +F0, 0, nop, 0 # id: (0, 94) +F0, 0, nop, 0 # id: (0, 95) +F0, 0, nop, 0 # id: (0, 96) +F0, 0, nop, 0 # id: (0, 97) +F0, 0, nop, 0 # id: (0, 98) +F0, 0, nop, 0 # id: (0, 99) +F0, 0, nop, 0 # id: (0, 100) +F0, 0, nop, 0 # id: (0, 101) +F0, 0, nop, 0 # id: (0, 102) +F0, 0, nop, 0 # id: (0, 103) +F0, 0, nop, 0 # id: (0, 104) +F0, 0, nop, 0 # id: (0, 105) +F0, 0, nop, 0 # id: (0, 106) +F0, 0, nop, 0 # id: (0, 107) +F0, 0, nop, 0 # id: (0, 108) +F0, 0, nop, 0 # id: (0, 109) +F0, 0, nop, 0 # id: (0, 110) +F0, 0, nop, 0 # id: (0, 111) +F0, 0, nop, 0 # id: (0, 112) +F0, 0, nop, 0 # id: (0, 113) +F0, 0, nop, 0 # id: (0, 114) +F0, 0, nop, 0 # id: (0, 115) +F0, 0, nop, 0 # id: (0, 116) +F0, 0, nop, 0 # id: (0, 117) +F0, 0, nop, 0 # id: (0, 118) +F0, 0, nop, 0 # id: (0, 119) +F0, 0, nop, 0 # id: (0, 120) +F0, 0, nop, 0 # id: (0, 121) +F0, 0, nop, 0 # id: (0, 122) +F0, 0, nop, 0 # id: (0, 123) +F0, 0, nop, 0 # id: (0, 124) +F0, 0, nop, 0 # id: (0, 125) +F0, 0, nop, 0 # id: (0, 126) +F0, 0, nop, 0 # id: (0, 127) +F0, 0, nop, 0 # id: (0, 128) +F0, 0, nop, 0 # id: (0, 129) +F0, 0, nop, 0 # id: (0, 130) +F0, 0, nop, 0 # id: (0, 131) +F0, 0, nop, 0 # id: (0, 132) +F0, 0, nop, 0 # id: (0, 133) +F0, 0, nop, 0 # id: (0, 134) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/bgv_multi_mul_relin_16384_l1_m2_program_trace.csv b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/bgv_multi_mul_relin_16384_l1_m2_program_trace.csv new file mode 100644 index 00000000..ffeee5de --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/bgv_multi_mul_relin_16384_l1_m2_program_trace.csv @@ -0,0 +1,3 @@ +instruction,scheme,poly_modulus_degree,keyrns_terms,arg0,arg1,arg2,arg3,arg4,arg5,arg6,arg7,arg8,arg9 +mul,BGV,16384,2,ct2-3-1,ct0-2-1,ct1-2-1 +relin,BGV,16384,2,ct3-2-1,ct2-3-1 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..96e5ca42 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst @@ -0,0 +1,67 @@ +0, csyncm, 4 # id: (0, 20) +1, bload, 0, 4, 0 # id: (0, 21); loading twid metadata for residuals [0, 64) +2, bload, 1, 4, 1 # id: (0, 22); loading twid metadata for residuals [0, 64) +3, bload, 2, 4, 2 # id: (0, 23); loading twid metadata for residuals [0, 64) +4, bload, 3, 4, 3 # id: (0, 24); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 25) +6, bload, 4, 5, 0 # id: (0, 26); loading twid metadata for residuals [0, 64) +7, bload, 5, 5, 1 # id: (0, 27); loading twid metadata for residuals [0, 64) +8, bload, 6, 5, 2 # id: (0, 28); loading twid metadata for residuals [0, 64) +9, bload, 7, 5, 3 # id: (0, 29); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 30) +11, bload, 8, 6, 0 # id: (0, 31); loading twid metadata for residuals [0, 64) +12, bload, 9, 6, 1 # id: (0, 32); loading twid metadata for residuals [0, 64) +13, bload, 10, 6, 2 # id: (0, 33); loading twid metadata for residuals [0, 64) +14, bload, 11, 6, 3 # id: (0, 34); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 35) +16, bload, 12, 7, 0 # id: (0, 36); loading twid metadata for residuals [0, 64) +17, bload, 13, 7, 1 # id: (0, 37); loading twid metadata for residuals [0, 64) +18, bload, 14, 7, 2 # id: (0, 38); loading twid metadata for residuals [0, 64) +19, bload, 15, 7, 3 # id: (0, 39); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 40) +21, bload, 16, 8, 0 # id: (0, 41); loading twid metadata for residuals [0, 64) +22, bload, 17, 8, 1 # id: (0, 42); loading twid metadata for residuals [0, 64) +23, bload, 18, 8, 2 # id: (0, 43); loading twid metadata for residuals [0, 64) +24, bload, 19, 8, 3 # id: (0, 44); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 45) +26, bload, 20, 9, 0 # id: (0, 46); loading twid metadata for residuals [0, 64) +27, bload, 21, 9, 1 # id: (0, 47); loading twid metadata for residuals [0, 64) +28, bload, 22, 9, 2 # id: (0, 48); loading twid metadata for residuals [0, 64) +29, bload, 23, 9, 3 # id: (0, 49); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 50) +31, bload, 24, 10, 0 # id: (0, 51); loading twid metadata for residuals [0, 64) +32, bload, 25, 10, 1 # id: (0, 52); loading twid metadata for residuals [0, 64) +33, bload, 26, 10, 2 # id: (0, 53); loading twid metadata for residuals [0, 64) +34, bload, 27, 10, 3 # id: (0, 54); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 55) +36, bload, 28, 11, 0 # id: (0, 56); loading twid metadata for residuals [0, 64) +37, bload, 29, 11, 1 # id: (0, 57); loading twid metadata for residuals [0, 64) +38, bload, 30, 11, 2 # id: (0, 58); loading twid metadata for residuals [0, 64) +39, bload, 31, 11, 3 # id: (0, 59); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 61) +41, bones, 12, 0 # id: (0, 62); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 65) +43, cload, r0b0, 13 # id: (1, 66); dep id: (1, 0); ct0_0_0_0 +44, csyncm, 14 # id: (1, 69) +45, cload, r1b0, 14 # id: (1, 70); dep id: (1, 0); ct1_1_0_0 +46, csyncm, 15 # id: (2, 73) +47, cload, r2b0, 15 # id: (2, 74); dep id: (2, 1); ct0_0_0_1 +48, csyncm, 16 # id: (2, 77) +49, cload, r3b0, 16 # id: (2, 78); dep id: (2, 1); ct1_1_0_1 +50, csyncm, 17 # id: (3, 81) +51, cload, r4b0, 17 # id: (3, 82); dep id: (3, 2); ct1_0_0_0 +52, csyncm, 18 # id: (4, 86) +53, cload, r5b0, 18 # id: (4, 87); dep id: (4, 3); ct1_0_0_1 +54, csyncm, 19 # id: (5, 91) +55, cload, r6b0, 20 # id: (5, 92); dep id: (5, 4); ct0_1_0_0 +56, csyncm, 20 # id: (6, 95) +57, cload, r7b0, 21 # id: (6, 96); dep id: (6, 5); ct0_1_0_1 +58, ifetch, 0 # id: (67, 150) +59, cstore, 19 # id: (3, 101); id: (3, 89); flushing output; variable "ct2_0_0_0": SPAD(19) <- r3b1; ct2_0_0_0 +60, cstore, 22 # id: (4, 107); id: (4, 99); flushing output; variable "ct2_0_0_1": SPAD(22) <- r7b1; ct2_0_0_1 +61, cstore, 23 # id: (5, 109); id: (5, 102); flushing output; variable "ct2_2_0_0": SPAD(23) <- r5b1; ct2_2_0_0 +62, cstore, 24 # id: (6, 111); id: (6, 103); flushing output; variable "ct2_2_0_1": SPAD(24) <- r6b1; ct2_2_0_1 +63, cstore, 25 # id: (7, 113); id: (7, 104); flushing output; variable "ct2_1_0_0": SPAD(25) <- r0b3; ct2_1_0_0 +64, cstore, 26 # id: (8, 115); id: (8, 105); flushing output; variable "ct2_1_0_1": SPAD(26) <- r1b3; ct2_1_0_1 +65, csyncm, 32 # id: (8, 163) +66, cexit # id: (66, 164) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..f6625deb --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.mem @@ -0,0 +1,27 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_0_0_0 +dload, poly, 14, ct1_1_0_0 +dload, poly, 15, ct0_0_0_1 +dload, poly, 16, ct1_1_0_1 +dload, poly, 17, ct1_0_0_0 +dload, poly, 18, ct1_0_0_1 +dload, poly, 19, ct0_1_0_0 +dload, poly, 20, ct0_1_0_1 +dstore, ct2_0_0_0, 21 +dstore, ct2_0_0_1, 22 +dstore, ct2_2_0_0, 23 +dstore, ct2_2_0_1, 24 +dstore, ct2_1_0_0, 25 +dstore, ct2_1_0_1, 26 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..4bc169e6 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.minst @@ -0,0 +1,34 @@ +0, mload, 0, ntt_auxiliary_table_0 # id: (0, 8) +1, mload, 1, ntt_routing_table_1 # id: (0, 9) +2, mload, 2, intt_auxiliary_table_2 # id: (0, 10) +3, mload, 3, intt_routing_table_3 # id: (0, 11) +4, mload, 4, twid_4 # id: (0, 12); loading twid metadata for residuals [0, 64) +5, mload, 5, twid_5 # id: (0, 13); loading twid metadata for residuals [0, 64) +6, mload, 6, twid_6 # id: (0, 14); loading twid metadata for residuals [0, 64) +7, mload, 7, twid_7 # id: (0, 15); loading twid metadata for residuals [0, 64) +8, mload, 8, twid_8 # id: (0, 16); loading twid metadata for residuals [0, 64) +9, mload, 9, twid_9 # id: (0, 17); loading twid metadata for residuals [0, 64) +10, mload, 10, twid_10 # id: (0, 18); loading twid metadata for residuals [0, 64) +11, mload, 11, twid_11 # id: (0, 19); loading twid metadata for residuals [0, 64) +12, mload, 12, ones_12 # id: (0, 60); loading ones metadata for residuals [0, 64) +13, mload, 13, ct0_0_0_0 # id: (1, 64); dep id: (1, 0) +14, mload, 14, ct1_1_0_0 # id: (1, 68); dep id: (1, 0) +15, mload, 15, ct0_0_0_1 # id: (2, 72); dep id: (2, 1) +16, mload, 16, ct1_1_0_1 # id: (2, 76); dep id: (2, 1) +17, mload, 17, ct1_0_0_0 # id: (3, 80); dep id: (3, 2) +18, mload, 18, ct1_0_0_1 # id: (4, 85); dep id: (4, 3) +19, mload, 20, ct0_1_0_0 # id: (5, 90); dep id: (5, 4) +20, mload, 21, ct0_1_0_1 # id: (6, 94); dep id: (6, 5) +21, msyncc, 59 # id: (3, 151) +22, mstore, ct2_0_0_0, 19 # id: (3, 152); id: (3, 101) - flushing; variable "ct2_0_0_0" <- SPAD(19) +23, msyncc, 60 # id: (4, 153) +24, mstore, ct2_0_0_1, 22 # id: (4, 154); id: (4, 107) - flushing; variable "ct2_0_0_1" <- SPAD(22) +25, msyncc, 61 # id: (5, 155) +26, mstore, ct2_2_0_0, 23 # id: (5, 156); id: (5, 109) - flushing; variable "ct2_2_0_0" <- SPAD(23) +27, msyncc, 62 # id: (6, 157) +28, mstore, ct2_2_0_1, 24 # id: (6, 158); id: (6, 111) - flushing; variable "ct2_2_0_1" <- SPAD(24) +29, msyncc, 63 # id: (7, 159) +30, mstore, ct2_1_0_0, 25 # id: (7, 160); id: (7, 113) - flushing; variable "ct2_1_0_0" <- SPAD(25) +31, msyncc, 64 # id: (8, 161) +32, mstore, ct2_1_0_1, 26 # id: (8, 162); id: (8, 115) - flushing; variable "ct2_1_0_1" <- SPAD(26) +33, msyncc, 67 # id: (66, 165); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..06f07a53 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst @@ -0,0 +1,64 @@ +F0, 1, move, r0b2, r0b0 # id: (1, 67); variable "ct0_0_0_0" +F0, 1, move, r0b1, r1b0 # id: (1, 71); variable "ct1_1_0_0" +F0, 2, move, r1b2, r2b0 # id: (2, 75); variable "ct0_0_0_1" +F0, 2, move, r1b1, r3b0 # id: (2, 79); variable "ct1_1_0_1" +F0, 3, move, r2b1, r4b0 # id: (3, 83); variable "ct1_0_0_0" +F0, 1, nop, 1 # id: (1, 84); nop for not ready instr (1, 0) +F0, 1, mul, r0b3, r0b2, r0b1, 0 # id: (1, 0); id: (1, 0) +F0, 4, move, r4b1, r5b0 # id: (4, 88); variable "ct1_0_0_1" +F0, 2, mul, r1b3, r1b2, r1b1, 0 # id: (2, 1); id: (2, 1) +F0, 3, mul, r3b1, r0b2, r2b1, 0 # id: (3, 2); id: (3, 2) +F0, 5, move, r2b2, r6b0 # id: (5, 93); variable "ct0_1_0_0" +F0, 6, move, r3b2, r7b0 # id: (6, 97); variable "ct0_1_0_1" +F0, 4, nop, 0 # id: (4, 98); nop for not ready instr (4, 3) +F0, 4, mul, r7b1, r1b2, r4b1, 0 # id: (4, 3); id: (4, 3) +F0, 3, nop, 0 # id: (3, 100); nop for not ready instr (3, 89) +F0, 3, xstore, r3b1 # id: (3, 89); flushing output; variable "ct2_0_0_0": SPAD(19) <- r3b1 +F0, 5, mul, r5b1, r2b2, r0b1, 0 # id: (5, 4); id: (5, 4) +F0, 6, mul, r6b1, r3b2, r1b1, 0 # id: (6, 5); id: (6, 5) +F0, 7, mac, r0b3, r0b3, r2b2, r2b1, 0 # id: (7, 6); id: (7, 6) +F0, 8, mac, r1b3, r1b3, r3b2, r4b1, 0 # id: (8, 7); id: (8, 7) +F0, 4, nop, 0 # id: (4, 106); nop for not ready instr (4, 99) +F0, 4, xstore, r7b1 # id: (4, 99); flushing output; variable "ct2_0_0_1": SPAD(22) <- r7b1 +F0, 5, nop, 4 # id: (5, 108); nop for not ready instr (5, 102) +F0, 5, xstore, r5b1 # id: (5, 102); flushing output; variable "ct2_2_0_0": SPAD(23) <- r5b1 +F0, 6, nop, 4 # id: (6, 110); nop for not ready instr (6, 103) +F0, 6, xstore, r6b1 # id: (6, 103); flushing output; variable "ct2_2_0_1": SPAD(24) <- r6b1 +F0, 7, nop, 4 # id: (7, 112); nop for not ready instr (7, 104) +F0, 7, xstore, r0b3 # id: (7, 104); flushing output; variable "ct2_1_0_0": SPAD(25) <- r0b3 +F0, 8, nop, 4 # id: (8, 114); nop for not ready instr (8, 105) +F0, 8, xstore, r1b3 # id: (8, 105); flushing output; variable "ct2_1_0_1": SPAD(26) <- r1b3 +F0, 0, bexit # id: (0, 116); terminating bundle 0 +F0, 0, nop, 0 # id: (0, 117) +F0, 0, nop, 0 # id: (0, 118) +F0, 0, nop, 0 # id: (0, 119) +F0, 0, nop, 0 # id: (0, 120) +F0, 0, nop, 0 # id: (0, 121) +F0, 0, nop, 0 # id: (0, 122) +F0, 0, nop, 0 # id: (0, 123) +F0, 0, nop, 0 # id: (0, 124) +F0, 0, nop, 0 # id: (0, 125) +F0, 0, nop, 0 # id: (0, 126) +F0, 0, nop, 0 # id: (0, 127) +F0, 0, nop, 0 # id: (0, 128) +F0, 0, nop, 0 # id: (0, 129) +F0, 0, nop, 0 # id: (0, 130) +F0, 0, nop, 0 # id: (0, 131) +F0, 0, nop, 0 # id: (0, 132) +F0, 0, nop, 0 # id: (0, 133) +F0, 0, nop, 0 # id: (0, 134) +F0, 0, nop, 0 # id: (0, 135) +F0, 0, nop, 0 # id: (0, 136) +F0, 0, nop, 0 # id: (0, 137) +F0, 0, nop, 0 # id: (0, 138) +F0, 0, nop, 0 # id: (0, 139) +F0, 0, nop, 0 # id: (0, 140) +F0, 0, nop, 0 # id: (0, 141) +F0, 0, nop, 0 # id: (0, 142) +F0, 0, nop, 0 # id: (0, 143) +F0, 0, nop, 0 # id: (0, 144) +F0, 0, nop, 0 # id: (0, 145) +F0, 0, nop, 0 # id: (0, 146) +F0, 0, nop, 0 # id: (0, 147) +F0, 0, nop, 0 # id: (0, 148) +F0, 0, nop, 0 # id: (0, 149) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..f73a024d --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst @@ -0,0 +1,125 @@ +0, csyncm, 4 # id: (0, 361) +1, bload, 0, 4, 0 # id: (0, 362); loading twid metadata for residuals [0, 64) +2, bload, 1, 4, 1 # id: (0, 363); loading twid metadata for residuals [0, 64) +3, bload, 2, 4, 2 # id: (0, 364); loading twid metadata for residuals [0, 64) +4, bload, 3, 4, 3 # id: (0, 365); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 366) +6, bload, 4, 5, 0 # id: (0, 367); loading twid metadata for residuals [0, 64) +7, bload, 5, 5, 1 # id: (0, 368); loading twid metadata for residuals [0, 64) +8, bload, 6, 5, 2 # id: (0, 369); loading twid metadata for residuals [0, 64) +9, bload, 7, 5, 3 # id: (0, 370); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 371) +11, bload, 8, 6, 0 # id: (0, 372); loading twid metadata for residuals [0, 64) +12, bload, 9, 6, 1 # id: (0, 373); loading twid metadata for residuals [0, 64) +13, bload, 10, 6, 2 # id: (0, 374); loading twid metadata for residuals [0, 64) +14, bload, 11, 6, 3 # id: (0, 375); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 376) +16, bload, 12, 7, 0 # id: (0, 377); loading twid metadata for residuals [0, 64) +17, bload, 13, 7, 1 # id: (0, 378); loading twid metadata for residuals [0, 64) +18, bload, 14, 7, 2 # id: (0, 379); loading twid metadata for residuals [0, 64) +19, bload, 15, 7, 3 # id: (0, 380); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 381) +21, bload, 16, 8, 0 # id: (0, 382); loading twid metadata for residuals [0, 64) +22, bload, 17, 8, 1 # id: (0, 383); loading twid metadata for residuals [0, 64) +23, bload, 18, 8, 2 # id: (0, 384); loading twid metadata for residuals [0, 64) +24, bload, 19, 8, 3 # id: (0, 385); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 386) +26, bload, 20, 9, 0 # id: (0, 387); loading twid metadata for residuals [0, 64) +27, bload, 21, 9, 1 # id: (0, 388); loading twid metadata for residuals [0, 64) +28, bload, 22, 9, 2 # id: (0, 389); loading twid metadata for residuals [0, 64) +29, bload, 23, 9, 3 # id: (0, 390); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 391) +31, bload, 24, 10, 0 # id: (0, 392); loading twid metadata for residuals [0, 64) +32, bload, 25, 10, 1 # id: (0, 393); loading twid metadata for residuals [0, 64) +33, bload, 26, 10, 2 # id: (0, 394); loading twid metadata for residuals [0, 64) +34, bload, 27, 10, 3 # id: (0, 395); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 396) +36, bload, 28, 11, 0 # id: (0, 397); loading twid metadata for residuals [0, 64) +37, bload, 29, 11, 1 # id: (0, 398); loading twid metadata for residuals [0, 64) +38, bload, 30, 11, 2 # id: (0, 399); loading twid metadata for residuals [0, 64) +39, bload, 31, 11, 3 # id: (0, 400); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 402) +41, bones, 12, 0 # id: (0, 403); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 406) +43, cload, r0b0, 13 # id: (1, 407); dep id: (1, 0); ct0_2_0_0 +44, csyncm, 14 # id: (1, 410) +45, cload, r1b0, 14 # id: (1, 411); dep id: (1, 0); ct0_2_0_1 +46, csyncm, 2 # id: (0, 439) +47, nload, 0, 2 # loading routing table for `intt` +48, csyncm, 3 # id: (0, 441) +49, nload, 1, 3 # loading routing table for `intt` +50, ifetch, 0 # id: (408, 438) +51, csyncm, 15 # id: (42, 446) +52, cload, r2b0, 15 # id: (42, 447); dep id: (42, 41); ipsi_0_0 +53, csyncm, 16 # id: (43, 450) +54, cload, r3b0, 16 # id: (43, 451); dep id: (43, 42); ipsi_0_1 +55, csyncm, 17 # id: (50, 458) +56, cload, r4b0, 17 # id: (50, 459); dep id: (50, 49); psi_0_0 +57, csyncm, 18 # id: (51, 462) +58, cload, r5b0, 18 # id: (51, 463); dep id: (51, 50); psi_0_1 +59, cnop, 364 # id: (1, 504) +60, ifetch, 1 # id: (37, 503) +61, cnop, 82 # id: (2, 532) +62, csyncm, 0 # id: (0, 533) +63, nload, 0, 0 # loading routing table for `ntt` +64, csyncm, 1 # id: (0, 535) +65, nload, 1, 1 # loading routing table for `ntt` +66, ifetch, 2 # id: (52, 531) +67, csyncm, 19 # id: (93, 538) +68, cload, r0b0, 19 # id: (93, 539); dep id: (93, 92); rlk_0_0_0_0 +69, csyncm, 20 # id: (95, 542) +70, cload, r1b0, 20 # id: (95, 543); dep id: (95, 94); rlk_1_0_0_0 +71, csyncm, 21 # id: (94, 547) +72, cload, r2b0, 21 # id: (94, 548); dep id: (94, 93); rlk_0_0_0_1 +73, csyncm, 22 # id: (96, 551) +74, cload, r3b0, 22 # id: (96, 552); dep id: (96, 95); rlk_1_0_0_1 +75, csyncm, 23 # id: (99, 557) +76, cload, r4b0, 23 # id: (99, 558); dep id: (99, 98); psi_1_0 +77, csyncm, 24 # id: (100, 562) +78, cload, r5b0, 24 # id: (100, 563); dep id: (100, 99); psi_1_1 +79, cnop, 368 # id: (3, 585) +80, ifetch, 3 # id: (91, 584) +81, csyncm, 25 # id: (142, 597) +82, cload, r6b0, 25 # id: (142, 598); dep id: (142, 141); rlk_0_0_1_0 +83, csyncm, 26 # id: (144, 601) +84, cload, r7b0, 26 # id: (144, 602); dep id: (144, 143); rlk_1_0_1_0 +85, csyncm, 27 # id: (143, 606) +86, cload, r8b0, 27 # id: (143, 607); dep id: (143, 142); rlk_0_0_1_1 +87, csyncm, 28 # id: (145, 610) +88, cload, r9b0, 28 # id: (145, 611); dep id: (145, 144); rlk_1_0_1_1 +89, cnop, 291 # id: (4, 644) +90, ifetch, 4 # id: (125, 643) +91, cnop, 193 # id: (5, 672) +92, nload, 0, 2 # loading routing table for `intt` +93, nload, 1, 3 # loading routing table for `intt` +94, ifetch, 5 # id: (145, 671) +95, csyncm, 29 # id: (188, 678) +96, cload, r0b0, 29 # id: (188, 679); dep id: (188, 187); ipsi_1_1 +97, csyncm, 30 # id: (187, 682) +98, cload, r1b0, 30 # id: (187, 683); dep id: (187, 186); ipsi_1_0 +99, cnop, 367 # id: (6, 705) +100, ifetch, 6 # id: (182, 704) +101, cnop, 265 # id: (7, 746) +102, ifetch, 7 # id: (271, 745) +103, cnop, 205 # id: (8, 774) +104, nload, 0, 0 # loading routing table for `ntt` +105, nload, 1, 1 # loading routing table for `ntt` +106, ifetch, 8 # id: (199, 773) +107, csyncm, 31 # id: (246, 781) +108, cload, r0b0, 31 # id: (246, 782); dep id: (246, 245); ct0_0_0_0 +109, csyncm, 32 # id: (247, 785) +110, cload, r1b0, 32 # id: (247, 786); dep id: (247, 246); ct0_0_0_1 +111, cnop, 388 # id: (9, 813) +112, ifetch, 9 # id: (238, 812) +113, cstore, 33 # id: (246, 792); id: (246, 789); flushing output; variable "ct1_0_0_0": SPAD(33) <- r17b1; ct1_0_0_0 +114, cstore, 34 # id: (247, 795); id: (247, 790); flushing output; variable "ct1_0_0_1": SPAD(34) <- r19b1; ct1_0_0_1 +115, csyncm, 37 # id: (348, 833) +116, cload, r2b0, 33 # id: (348, 834); dep id: (348, 347); ct0_1_0_0 +117, csyncm, 38 # id: (349, 837) +118, cload, r3b0, 34 # id: (349, 838); dep id: (349, 348); ct0_1_0_1 +119, cnop, 230 # id: (10, 866) +120, ifetch, 10 # id: (324, 865) +121, cstore, 35 # id: (348, 844); id: (348, 841); flushing output; variable "ct1_1_0_0": SPAD(35) <- r17b1; ct1_1_0_0 +122, cstore, 36 # id: (349, 846); id: (349, 842); flushing output; variable "ct1_1_0_1": SPAD(36) <- r20b1; ct1_1_0_1 +123, csyncm, 42 # id: (349, 871) +124, cexit # id: (124, 872) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..fb7b3912 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.mem @@ -0,0 +1,39 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_2_0_0 +dload, poly, 14, ct0_2_0_1 +dload, poly, 15, ipsi_0_0 +dload, poly, 16, ipsi_0_1 +dload, poly, 17, psi_0_0 +dload, poly, 18, psi_0_1 +dload, poly, 19, rlk_0_0_0_0 +dload, poly, 20, rlk_0_0_0_1 +dload, poly, 21, rlk_1_0_0_0 +dload, poly, 22, rlk_1_0_0_1 +dload, poly, 23, psi_1_0 +dload, poly, 24, psi_1_1 +dload, poly, 25, rlk_0_0_1_0 +dload, poly, 26, rlk_0_0_1_1 +dload, poly, 27, rlk_1_0_1_0 +dload, poly, 28, rlk_1_0_1_1 +dload, poly, 29, ipsi_1_0 +dload, poly, 30, ipsi_1_1 +dload, poly, 31, ct0_0_0_0 +dload, poly, 32, ct0_0_0_1 +dload, poly, 33, ct0_1_0_0 +dload, poly, 34, ct0_1_0_1 +dstore, ct1_0_0_0, 35 +dstore, ct1_0_0_1, 36 +dstore, ct1_1_0_0, 37 +dstore, ct1_1_0_1, 38 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..88830cf7 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.minst @@ -0,0 +1,44 @@ +0, mload, 0, ntt_auxiliary_table_0 # id: (0, 349) +1, mload, 1, ntt_routing_table_1 # id: (0, 350) +2, mload, 2, intt_auxiliary_table_2 # id: (0, 351) +3, mload, 3, intt_routing_table_3 # id: (0, 352) +4, mload, 4, twid_4 # id: (0, 353); loading twid metadata for residuals [0, 64) +5, mload, 5, twid_5 # id: (0, 354); loading twid metadata for residuals [0, 64) +6, mload, 6, twid_6 # id: (0, 355); loading twid metadata for residuals [0, 64) +7, mload, 7, twid_7 # id: (0, 356); loading twid metadata for residuals [0, 64) +8, mload, 8, twid_8 # id: (0, 357); loading twid metadata for residuals [0, 64) +9, mload, 9, twid_9 # id: (0, 358); loading twid metadata for residuals [0, 64) +10, mload, 10, twid_10 # id: (0, 359); loading twid metadata for residuals [0, 64) +11, mload, 11, twid_11 # id: (0, 360); loading twid metadata for residuals [0, 64) +12, mload, 12, ones_12 # id: (0, 401); loading ones metadata for residuals [0, 64) +13, mload, 13, ct0_2_0_0 # id: (1, 405); dep id: (1, 0) +14, mload, 14, ct0_2_0_1 # id: (1, 409); dep id: (1, 0) +15, mload, 15, ipsi_0_0 # id: (42, 445); dep id: (42, 41) +16, mload, 16, ipsi_0_1 # id: (43, 449); dep id: (43, 42) +17, mload, 17, psi_0_0 # id: (50, 457); dep id: (50, 49) +18, mload, 18, psi_0_1 # id: (51, 461); dep id: (51, 50) +19, mload, 19, rlk_0_0_0_0 # id: (93, 537); dep id: (93, 92) +20, mload, 20, rlk_1_0_0_0 # id: (95, 541); dep id: (95, 94) +21, mload, 21, rlk_0_0_0_1 # id: (94, 546); dep id: (94, 93) +22, mload, 22, rlk_1_0_0_1 # id: (96, 550); dep id: (96, 95) +23, mload, 23, psi_1_0 # id: (99, 556); dep id: (99, 98) +24, mload, 24, psi_1_1 # id: (100, 561); dep id: (100, 99) +25, mload, 25, rlk_0_0_1_0 # id: (142, 596); dep id: (142, 141) +26, mload, 26, rlk_1_0_1_0 # id: (144, 600); dep id: (144, 143) +27, mload, 27, rlk_0_0_1_1 # id: (143, 605); dep id: (143, 142) +28, mload, 28, rlk_1_0_1_1 # id: (145, 609); dep id: (145, 144) +29, mload, 29, ipsi_1_1 # id: (188, 677); dep id: (188, 187) +30, mload, 30, ipsi_1_0 # id: (187, 681); dep id: (187, 186) +31, mload, 31, ct0_0_0_0 # id: (246, 780); dep id: (246, 245) +32, mload, 32, ct0_0_0_1 # id: (247, 784); dep id: (247, 246) +33, msyncc, 113 # id: (246, 814) +34, mstore, ct1_0_0_0, 33 # id: (246, 815); id: (246, 792) - flushing; variable "ct1_0_0_0" <- SPAD(33) +35, msyncc, 114 # id: (247, 816) +36, mstore, ct1_0_0_1, 34 # id: (247, 817); id: (247, 795) - flushing; variable "ct1_0_0_1" <- SPAD(34) +37, mload, 33, ct0_1_0_0 # id: (348, 832); dep id: (348, 347) +38, mload, 34, ct0_1_0_1 # id: (349, 836); dep id: (349, 348) +39, msyncc, 121 # id: (348, 867) +40, mstore, ct1_1_0_0, 35 # id: (348, 868); id: (348, 844) - flushing; variable "ct1_1_0_0" <- SPAD(35) +41, msyncc, 122 # id: (349, 869) +42, mstore, ct1_1_0_1, 36 # id: (349, 870); id: (349, 846) - flushing; variable "ct1_1_0_1" <- SPAD(36) +43, msyncc, 125 # id: (124, 873); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..3c500692 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst @@ -0,0 +1,704 @@ +F0, 1, move, r0b2, r0b0 # id: (1, 408); variable "ct0_2_0_0" +F0, 1, move, r0b3, r1b0 # id: (1, 412); variable "ct0_2_0_1" +F0, 1, nop, 4 # id: (1, 413); nop for not ready instr (1, 0) +F0, 1, rshuffle, r0b2, r0b3, r0b2, r0b3, 0, intt # id: (1, 0); id: (1, 1); 0 0 1 12 w_0_0_0 +F0, 2, nop, 21 # id: (2, 414); nop for not ready instr (2, 1) +F0, 2, intt, r1b2, r1b3, r0b2, r0b3, r0b1, 0, 0 # id: (2, 1); id: (1, 2); 0 0 1 12 w_0_0_0 +F0, 3, twintt, r0b1, r0b1, 28, 0, 0, 14, 0 # id: (3, 2); id: (1, 0); 0 0 1 12 w_0_0_0 +F0, 4, nop, 3 # id: (4, 415); nop for not ready instr (4, 3) +F0, 4, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (4, 3); id: (2, 4); 0 0 1 11 w_0_1_0 +F0, 5, nop, 21 # id: (5, 416); nop for not ready instr (5, 4) +F0, 5, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 1, 0 # id: (5, 4); id: (2, 5); 0 0 1 11 w_0_1_0 +F0, 6, twintt, r0b1, r0b1, 27, 1, 0, 14, 0 # id: (6, 5); id: (2, 3); 0 0 1 11 w_0_1_0 +F0, 7, nop, 3 # id: (7, 417); nop for not ready instr (7, 6) +F0, 7, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (7, 6); id: (3, 7); 0 0 1 10 w_0_2_0 +F0, 8, nop, 21 # id: (8, 418); nop for not ready instr (8, 7) +F0, 8, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 2, 0 # id: (8, 7); id: (3, 8); 0 0 1 10 w_0_2_0 +F0, 9, twintt, r0b1, r0b1, 26, 2, 0, 14, 0 # id: (9, 8); id: (3, 6); 0 0 1 10 w_0_2_0 +F0, 10, nop, 3 # id: (10, 419); nop for not ready instr (10, 9) +F0, 10, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (10, 9); id: (4, 10); 0 0 1 9 w_0_3_0 +F0, 11, nop, 21 # id: (11, 420); nop for not ready instr (11, 10) +F0, 11, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 3, 0 # id: (11, 10); id: (4, 11); 0 0 1 9 w_0_3_0 +F0, 12, twintt, r0b1, r0b1, 25, 3, 0, 14, 0 # id: (12, 11); id: (4, 9); 0 0 1 9 w_0_3_0 +F0, 13, nop, 3 # id: (13, 421); nop for not ready instr (13, 12) +F0, 13, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (13, 12); id: (5, 13); 0 0 1 8 w_0_4_0 +F0, 14, nop, 21 # id: (14, 422); nop for not ready instr (14, 13) +F0, 14, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 4, 0 # id: (14, 13); id: (5, 14); 0 0 1 8 w_0_4_0 +F0, 15, twintt, r0b1, r0b1, 24, 4, 0, 14, 0 # id: (15, 14); id: (5, 12); 0 0 1 8 w_0_4_0 +F0, 16, nop, 3 # id: (16, 423); nop for not ready instr (16, 15) +F0, 16, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (16, 15); id: (6, 16); 0 0 1 7 w_0_5_0 +F0, 17, nop, 21 # id: (17, 424); nop for not ready instr (17, 16) +F0, 17, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 5, 0 # id: (17, 16); id: (6, 17); 0 0 1 7 w_0_5_0 +F0, 18, twintt, r0b1, r0b1, 23, 5, 0, 14, 0 # id: (18, 17); id: (6, 15); 0 0 1 7 w_0_5_0 +F0, 19, nop, 3 # id: (19, 425); nop for not ready instr (19, 18) +F0, 19, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (19, 18); id: (7, 19); 0 0 1 6 w_0_6_0 +F0, 20, nop, 21 # id: (20, 426); nop for not ready instr (20, 19) +F0, 20, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 6, 0 # id: (20, 19); id: (7, 20); 0 0 1 6 w_0_6_0 +F0, 21, twintt, r0b1, r0b1, 22, 6, 0, 14, 0 # id: (21, 20); id: (7, 18); 0 0 1 6 w_0_6_0 +F0, 22, nop, 3 # id: (22, 427); nop for not ready instr (22, 21) +F0, 22, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (22, 21); id: (8, 22); 0 0 1 5 w_0_7_0 +F0, 23, nop, 21 # id: (23, 428); nop for not ready instr (23, 22) +F0, 23, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 7, 0 # id: (23, 22); id: (8, 23); 0 0 1 5 w_0_7_0 +F0, 24, twintt, r0b1, r0b1, 21, 7, 0, 14, 0 # id: (24, 23); id: (8, 21); 0 0 1 5 w_0_7_0 +F0, 25, nop, 3 # id: (25, 429); nop for not ready instr (25, 24) +F0, 25, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (25, 24); id: (9, 25); 0 0 1 4 w_0_8_0 +F0, 26, nop, 21 # id: (26, 430); nop for not ready instr (26, 25) +F0, 26, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 8, 0 # id: (26, 25); id: (9, 26); 0 0 1 4 w_0_8_0 +F0, 27, twintt, r0b1, r0b1, 20, 8, 0, 14, 0 # id: (27, 26); id: (9, 24); 0 0 1 4 w_0_8_0 +F0, 28, nop, 3 # id: (28, 431); nop for not ready instr (28, 27) +F0, 28, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (28, 27); id: (10, 28); 0 0 1 3 w_0_9_0 +F0, 29, nop, 21 # id: (29, 432); nop for not ready instr (29, 28) +F0, 29, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 9, 0 # id: (29, 28); id: (10, 29); 0 0 1 3 w_0_9_0 +F0, 30, twintt, r0b1, r0b1, 19, 9, 0, 14, 0 # id: (30, 29); id: (10, 27); 0 0 1 3 w_0_9_0 +F0, 31, nop, 3 # id: (31, 433); nop for not ready instr (31, 30) +F0, 31, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (31, 30); id: (11, 31); 0 0 1 2 w_0_10_0 +F0, 32, nop, 21 # id: (32, 434); nop for not ready instr (32, 31) +F0, 32, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 10, 0 # id: (32, 31); id: (11, 32); 0 0 1 2 w_0_10_0 +F0, 33, twintt, r0b1, r0b1, 18, 10, 0, 14, 0 # id: (33, 32); id: (11, 30); 0 0 1 2 w_0_10_0 +F0, 34, nop, 3 # id: (34, 435); nop for not ready instr (34, 33) +F0, 34, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (34, 33); id: (12, 34); 0 0 1 1 w_0_11_0 +F0, 35, nop, 21 # id: (35, 436); nop for not ready instr (35, 34) +F0, 35, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 11, 0 # id: (35, 34); id: (12, 35); 0 0 1 1 w_0_11_0 +F0, 36, twintt, r0b1, r0b1, 17, 11, 0, 14, 0 # id: (36, 35); id: (12, 33); 0 0 1 1 w_0_11_0 +F0, 37, nop, 3 # id: (37, 437); nop for not ready instr (37, 36) +F0, 37, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (37, 36); id: (13, 37); 0 0 1 0 w_0_12_0 +F1, 38, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 12, 0 # id: (38, 37); id: (13, 38); 0 0 1 0 w_0_12_0 +F1, 39, twintt, r0b1, r0b1, 16, 12, 0, 14, 0 # id: (39, 38); id: (13, 36); 0 0 1 0 w_0_12_0 +F1, 40, nop, 3 # id: (40, 443); nop for not ready instr (40, 39) +F1, 40, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (40, 39); id: (14, 39); 0 0 1 -1 w_0_13_0 +F1, 41, nop, 21 # id: (41, 444); nop for not ready instr (41, 40) +F1, 41, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 13, 0 # id: (41, 40); id: (14, 40); 0 0 1 -1 w_0_13_0 +F1, 42, move, r1b1, r2b0 # id: (42, 448); variable "ipsi_0_0" +F1, 43, move, r2b1, r3b0 # id: (43, 452); variable "ipsi_0_1" +F1, 42, nop, 3 # id: (42, 453); nop for not ready instr (42, 41) +F1, 42, mul, r2b2, r2b2, r1b1, 0 # id: (42, 41); id: (15, 41) +F1, 43, mul, r2b3, r2b3, r2b1, 0 # id: (43, 42); id: (16, 42) +F1, 44, nop, 3 # id: (44, 454); nop for not ready instr (44, 43) +F1, 44, muli, r2b2, r2b2, iN, 0 # id: (44, 43); id: (17, 43) +F1, 45, muli, r2b3, r2b3, iN, 0 # id: (45, 44); id: (18, 44) +F1, 46, nop, 3 # id: (46, 455); nop for not ready instr (46, 45) +F1, 46, muli, r2b2, r2b2, one, 0 # id: (46, 45); id: (19, 45) +F1, 47, muli, r2b3, r2b3, one, 0 # id: (47, 46); id: (20, 46) +F1, 48, nop, 3 # id: (48, 456); nop for not ready instr (48, 47) +F1, 48, muli, r3b1, r2b2, R2_0, 0 # id: (48, 47); id: (21, 47) +F1, 49, muli, r3b2, r2b3, R2_0, 0 # id: (49, 48); id: (22, 48) +F1, 50, move, r4b2, r4b0 # id: (50, 460); variable "psi_0_0" +F1, 51, move, r4b1, r5b0 # id: (51, 464); variable "psi_0_1" +F1, 50, nop, 3 # id: (50, 465); nop for not ready instr (50, 49) +F1, 50, mul, r3b1, r3b1, r4b2, 0 # id: (50, 49); id: (23, 49) +F1, 51, mul, r3b2, r3b2, r4b1, 0 # id: (51, 50); id: (24, 50) +F1, 52, nop, 4 # id: (52, 466); nop for not ready instr (52, 51) +F1, 52, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 0, 0 # id: (52, 51); id: (25, 53); 0 0 0 12 w_0_0_0 +F1, 54, twntt, r3b3, r3b3, 12, 0, 0, 14, 0 # id: (54, 53); id: (25, 51); 0 0 0 12 w_0_0_0 +F1, 1, bexit # id: (1, 467); terminating bundle 1 +F1, 1, nop, 0 # id: (1, 468) +F1, 1, nop, 0 # id: (1, 469) +F1, 1, nop, 0 # id: (1, 470) +F1, 1, nop, 0 # id: (1, 471) +F1, 1, nop, 0 # id: (1, 472) +F1, 1, nop, 0 # id: (1, 473) +F1, 1, nop, 0 # id: (1, 474) +F1, 1, nop, 0 # id: (1, 475) +F1, 1, nop, 0 # id: (1, 476) +F1, 1, nop, 0 # id: (1, 477) +F1, 1, nop, 0 # id: (1, 478) +F1, 1, nop, 0 # id: (1, 479) +F1, 1, nop, 0 # id: (1, 480) +F1, 1, nop, 0 # id: (1, 481) +F1, 1, nop, 0 # id: (1, 482) +F1, 1, nop, 0 # id: (1, 483) +F1, 1, nop, 0 # id: (1, 484) +F1, 1, nop, 0 # id: (1, 485) +F1, 1, nop, 0 # id: (1, 486) +F1, 1, nop, 0 # id: (1, 487) +F1, 1, nop, 0 # id: (1, 488) +F1, 1, nop, 0 # id: (1, 489) +F1, 1, nop, 0 # id: (1, 490) +F1, 1, nop, 0 # id: (1, 491) +F1, 1, nop, 0 # id: (1, 492) +F1, 1, nop, 0 # id: (1, 493) +F1, 1, nop, 0 # id: (1, 494) +F1, 1, nop, 0 # id: (1, 495) +F1, 1, nop, 0 # id: (1, 496) +F1, 1, nop, 0 # id: (1, 497) +F1, 1, nop, 0 # id: (1, 498) +F1, 1, nop, 0 # id: (1, 499) +F1, 1, nop, 0 # id: (1, 500) +F1, 1, nop, 0 # id: (1, 501) +F1, 1, nop, 0 # id: (1, 502) +F2, 53, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (53, 52); id: (25, 52); 0 0 0 12 w_0_0_0 +F2, 55, nop, 21 # id: (55, 505); nop for not ready instr (55, 54) +F2, 55, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 1, 0 # id: (55, 54); id: (26, 56); 0 0 0 11 w_0_1_0 +F2, 57, twntt, r3b3, r3b3, 11, 1, 0, 14, 0 # id: (57, 56); id: (26, 54); 0 0 0 11 w_0_1_0 +F2, 56, nop, 3 # id: (56, 506); nop for not ready instr (56, 55) +F2, 56, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (56, 55); id: (26, 55); 0 0 0 11 w_0_1_0 +F2, 58, nop, 21 # id: (58, 507); nop for not ready instr (58, 57) +F2, 58, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 2, 0 # id: (58, 57); id: (27, 59); 0 0 0 10 w_0_2_0 +F2, 60, twntt, r3b3, r3b3, 10, 2, 0, 14, 0 # id: (60, 59); id: (27, 57); 0 0 0 10 w_0_2_0 +F2, 59, nop, 3 # id: (59, 508); nop for not ready instr (59, 58) +F2, 59, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (59, 58); id: (27, 58); 0 0 0 10 w_0_2_0 +F2, 61, nop, 21 # id: (61, 509); nop for not ready instr (61, 60) +F2, 61, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 3, 0 # id: (61, 60); id: (28, 62); 0 0 0 9 w_0_3_0 +F2, 63, twntt, r3b3, r3b3, 9, 3, 0, 14, 0 # id: (63, 62); id: (28, 60); 0 0 0 9 w_0_3_0 +F2, 62, nop, 3 # id: (62, 510); nop for not ready instr (62, 61) +F2, 62, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (62, 61); id: (28, 61); 0 0 0 9 w_0_3_0 +F2, 64, nop, 21 # id: (64, 511); nop for not ready instr (64, 63) +F2, 64, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 4, 0 # id: (64, 63); id: (29, 65); 0 0 0 8 w_0_4_0 +F2, 66, twntt, r3b3, r3b3, 8, 4, 0, 14, 0 # id: (66, 65); id: (29, 63); 0 0 0 8 w_0_4_0 +F2, 65, nop, 3 # id: (65, 512); nop for not ready instr (65, 64) +F2, 65, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (65, 64); id: (29, 64); 0 0 0 8 w_0_4_0 +F2, 67, nop, 21 # id: (67, 513); nop for not ready instr (67, 66) +F2, 67, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 5, 0 # id: (67, 66); id: (30, 68); 0 0 0 7 w_0_5_0 +F2, 69, twntt, r3b3, r3b3, 7, 5, 0, 14, 0 # id: (69, 68); id: (30, 66); 0 0 0 7 w_0_5_0 +F2, 68, nop, 3 # id: (68, 514); nop for not ready instr (68, 67) +F2, 68, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (68, 67); id: (30, 67); 0 0 0 7 w_0_5_0 +F2, 70, nop, 21 # id: (70, 515); nop for not ready instr (70, 69) +F2, 70, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 6, 0 # id: (70, 69); id: (31, 71); 0 0 0 6 w_0_6_0 +F2, 72, twntt, r3b3, r3b3, 6, 6, 0, 14, 0 # id: (72, 71); id: (31, 69); 0 0 0 6 w_0_6_0 +F2, 71, nop, 3 # id: (71, 516); nop for not ready instr (71, 70) +F2, 71, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (71, 70); id: (31, 70); 0 0 0 6 w_0_6_0 +F2, 73, nop, 21 # id: (73, 517); nop for not ready instr (73, 72) +F2, 73, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 7, 0 # id: (73, 72); id: (32, 74); 0 0 0 5 w_0_7_0 +F2, 75, twntt, r3b3, r3b3, 5, 7, 0, 14, 0 # id: (75, 74); id: (32, 72); 0 0 0 5 w_0_7_0 +F2, 74, nop, 3 # id: (74, 518); nop for not ready instr (74, 73) +F2, 74, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (74, 73); id: (32, 73); 0 0 0 5 w_0_7_0 +F2, 76, nop, 21 # id: (76, 519); nop for not ready instr (76, 75) +F2, 76, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 8, 0 # id: (76, 75); id: (33, 77); 0 0 0 4 w_0_8_0 +F2, 78, twntt, r3b3, r3b3, 4, 8, 0, 14, 0 # id: (78, 77); id: (33, 75); 0 0 0 4 w_0_8_0 +F2, 77, nop, 3 # id: (77, 520); nop for not ready instr (77, 76) +F2, 77, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (77, 76); id: (33, 76); 0 0 0 4 w_0_8_0 +F2, 79, nop, 21 # id: (79, 521); nop for not ready instr (79, 78) +F2, 79, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 9, 0 # id: (79, 78); id: (34, 80); 0 0 0 3 w_0_9_0 +F2, 81, twntt, r3b3, r3b3, 3, 9, 0, 14, 0 # id: (81, 80); id: (34, 78); 0 0 0 3 w_0_9_0 +F2, 80, nop, 3 # id: (80, 522); nop for not ready instr (80, 79) +F2, 80, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (80, 79); id: (34, 79); 0 0 0 3 w_0_9_0 +F2, 82, nop, 21 # id: (82, 523); nop for not ready instr (82, 81) +F2, 82, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 10, 0 # id: (82, 81); id: (35, 83); 0 0 0 2 w_0_10_0 +F2, 84, twntt, r3b3, r3b3, 2, 10, 0, 14, 0 # id: (84, 83); id: (35, 81); 0 0 0 2 w_0_10_0 +F2, 83, nop, 3 # id: (83, 524); nop for not ready instr (83, 82) +F2, 83, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (83, 82); id: (35, 82); 0 0 0 2 w_0_10_0 +F2, 85, nop, 21 # id: (85, 525); nop for not ready instr (85, 84) +F2, 85, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 11, 0 # id: (85, 84); id: (36, 86); 0 0 0 1 w_0_11_0 +F2, 87, twntt, r3b3, r3b3, 1, 11, 0, 14, 0 # id: (87, 86); id: (36, 84); 0 0 0 1 w_0_11_0 +F2, 86, nop, 3 # id: (86, 526); nop for not ready instr (86, 85) +F2, 86, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (86, 85); id: (36, 85); 0 0 0 1 w_0_11_0 +F2, 88, nop, 21 # id: (88, 527); nop for not ready instr (88, 87) +F2, 88, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 12, 0 # id: (88, 87); id: (37, 89); 0 0 0 0 w_0_12_0 +F2, 90, twntt, r3b3, r3b3, 0, 12, 0, 14, 0 # id: (90, 89); id: (37, 87); 0 0 0 0 w_0_12_0 +F2, 89, nop, 3 # id: (89, 528); nop for not ready instr (89, 88) +F2, 89, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (89, 88); id: (37, 88); 0 0 0 0 w_0_12_0 +F2, 91, nop, 21 # id: (91, 529); nop for not ready instr (91, 90) +F2, 91, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 13, 0 # id: (91, 90); id: (38, 91); 0 0 0 -1 w_0_13_0 +F2, 2, bexit # id: (2, 530); terminating bundle 2 +F3, 92, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (92, 91); id: (38, 90); 0 0 0 -1 w_0_13_0 +F3, 93, move, r6b2, r0b0 # id: (93, 540); variable "rlk_0_0_0_0" +F3, 95, move, r8b2, r1b0 # id: (95, 544); variable "rlk_1_0_0_0" +F3, 93, nop, 19 # id: (93, 545); nop for not ready instr (93, 92) +F3, 93, mul, r7b2, r3b1, r6b2, 0 # id: (93, 92); id: (39, 92) +F3, 94, move, r6b1, r2b0 # id: (94, 549); variable "rlk_0_0_0_1" +F3, 95, mul, r9b2, r3b1, r8b2, 0 # id: (95, 94); id: (41, 94) +F3, 96, move, r8b1, r3b0 # id: (96, 553); variable "rlk_1_0_0_1" +F3, 97, muli, r3b1, r2b2, R2_1, 1 # id: (97, 96); id: (43, 96) +F3, 94, nop, 1 # id: (94, 554); nop for not ready instr (94, 93) +F3, 94, mul, r7b1, r3b2, r6b1, 0 # id: (94, 93); id: (40, 93) +F3, 96, nop, 0 # id: (96, 555); nop for not ready instr (96, 95) +F3, 96, mul, r9b1, r3b2, r8b1, 0 # id: (96, 95); id: (42, 95) +F3, 99, move, r10b2, r4b0 # id: (99, 559); variable "psi_1_0" +F3, 98, muli, r3b2, r2b3, R2_1, 1 # id: (98, 97); id: (44, 97) +F3, 99, nop, 3 # id: (99, 560); nop for not ready instr (99, 98) +F3, 99, mul, r3b1, r3b1, r10b2, 1 # id: (99, 98); id: (45, 98) +F3, 100, move, r10b1, r5b0 # id: (100, 564); variable "psi_1_1" +F3, 100, nop, 4 # id: (100, 565); nop for not ready instr (100, 99) +F3, 100, mul, r3b2, r3b2, r10b1, 1 # id: (100, 99); id: (46, 99) +F3, 101, nop, 4 # id: (101, 566); nop for not ready instr (101, 100) +F3, 101, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 0, 1 # id: (101, 100); id: (47, 102); 0 1 0 12 w_1_0_0 +F3, 103, twntt, r4b3, r4b3, 44, 0, 0, 14, 1 # id: (103, 102); id: (47, 100); 0 1 0 12 w_1_0_0 +F3, 102, nop, 3 # id: (102, 567); nop for not ready instr (102, 101) +F3, 102, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (102, 101); id: (47, 101); 0 1 0 12 w_1_0_0 +F3, 104, nop, 21 # id: (104, 568); nop for not ready instr (104, 103) +F3, 104, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 1, 1 # id: (104, 103); id: (48, 105); 0 1 0 11 w_1_1_0 +F3, 106, twntt, r4b3, r4b3, 43, 1, 0, 14, 1 # id: (106, 105); id: (48, 103); 0 1 0 11 w_1_1_0 +F3, 105, nop, 3 # id: (105, 569); nop for not ready instr (105, 104) +F3, 105, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (105, 104); id: (48, 104); 0 1 0 11 w_1_1_0 +F3, 107, nop, 21 # id: (107, 570); nop for not ready instr (107, 106) +F3, 107, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 2, 1 # id: (107, 106); id: (49, 108); 0 1 0 10 w_1_2_0 +F3, 109, twntt, r4b3, r4b3, 42, 2, 0, 14, 1 # id: (109, 108); id: (49, 106); 0 1 0 10 w_1_2_0 +F3, 108, nop, 3 # id: (108, 571); nop for not ready instr (108, 107) +F3, 108, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (108, 107); id: (49, 107); 0 1 0 10 w_1_2_0 +F3, 110, nop, 21 # id: (110, 572); nop for not ready instr (110, 109) +F3, 110, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 3, 1 # id: (110, 109); id: (50, 111); 0 1 0 9 w_1_3_0 +F3, 112, twntt, r4b3, r4b3, 41, 3, 0, 14, 1 # id: (112, 111); id: (50, 109); 0 1 0 9 w_1_3_0 +F3, 111, nop, 3 # id: (111, 573); nop for not ready instr (111, 110) +F3, 111, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (111, 110); id: (50, 110); 0 1 0 9 w_1_3_0 +F3, 113, nop, 21 # id: (113, 574); nop for not ready instr (113, 112) +F3, 113, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 4, 1 # id: (113, 112); id: (51, 114); 0 1 0 8 w_1_4_0 +F3, 115, twntt, r4b3, r4b3, 40, 4, 0, 14, 1 # id: (115, 114); id: (51, 112); 0 1 0 8 w_1_4_0 +F3, 114, nop, 3 # id: (114, 575); nop for not ready instr (114, 113) +F3, 114, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (114, 113); id: (51, 113); 0 1 0 8 w_1_4_0 +F3, 116, nop, 21 # id: (116, 576); nop for not ready instr (116, 115) +F3, 116, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 5, 1 # id: (116, 115); id: (52, 117); 0 1 0 7 w_1_5_0 +F3, 118, twntt, r4b3, r4b3, 39, 5, 0, 14, 1 # id: (118, 117); id: (52, 115); 0 1 0 7 w_1_5_0 +F3, 117, nop, 3 # id: (117, 577); nop for not ready instr (117, 116) +F3, 117, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (117, 116); id: (52, 116); 0 1 0 7 w_1_5_0 +F3, 119, nop, 21 # id: (119, 578); nop for not ready instr (119, 118) +F3, 119, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 6, 1 # id: (119, 118); id: (53, 120); 0 1 0 6 w_1_6_0 +F3, 121, twntt, r4b3, r4b3, 38, 6, 0, 14, 1 # id: (121, 120); id: (53, 118); 0 1 0 6 w_1_6_0 +F3, 120, nop, 3 # id: (120, 579); nop for not ready instr (120, 119) +F3, 120, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (120, 119); id: (53, 119); 0 1 0 6 w_1_6_0 +F3, 122, nop, 21 # id: (122, 580); nop for not ready instr (122, 121) +F3, 122, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 7, 1 # id: (122, 121); id: (54, 123); 0 1 0 5 w_1_7_0 +F3, 124, twntt, r4b3, r4b3, 37, 7, 0, 14, 1 # id: (124, 123); id: (54, 121); 0 1 0 5 w_1_7_0 +F3, 123, nop, 3 # id: (123, 581); nop for not ready instr (123, 122) +F3, 123, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (123, 122); id: (54, 122); 0 1 0 5 w_1_7_0 +F3, 125, nop, 21 # id: (125, 582); nop for not ready instr (125, 124) +F3, 125, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 8, 1 # id: (125, 124); id: (55, 126); 0 1 0 4 w_1_8_0 +F3, 127, twntt, r4b3, r4b3, 36, 8, 0, 14, 1 # id: (127, 126); id: (55, 124); 0 1 0 4 w_1_8_0 +F3, 3, bexit # id: (3, 583); terminating bundle 3 +F4, 126, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (126, 125); id: (55, 125); 0 1 0 4 w_1_8_0 +F4, 128, nop, 21 # id: (128, 586); nop for not ready instr (128, 127) +F4, 128, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 9, 1 # id: (128, 127); id: (56, 129); 0 1 0 3 w_1_9_0 +F4, 130, twntt, r4b3, r4b3, 35, 9, 0, 14, 1 # id: (130, 129); id: (56, 127); 0 1 0 3 w_1_9_0 +F4, 129, nop, 3 # id: (129, 587); nop for not ready instr (129, 128) +F4, 129, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (129, 128); id: (56, 128); 0 1 0 3 w_1_9_0 +F4, 131, nop, 21 # id: (131, 588); nop for not ready instr (131, 130) +F4, 131, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 10, 1 # id: (131, 130); id: (57, 132); 0 1 0 2 w_1_10_0 +F4, 133, twntt, r4b3, r4b3, 34, 10, 0, 14, 1 # id: (133, 132); id: (57, 130); 0 1 0 2 w_1_10_0 +F4, 132, nop, 3 # id: (132, 589); nop for not ready instr (132, 131) +F4, 132, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (132, 131); id: (57, 131); 0 1 0 2 w_1_10_0 +F4, 134, nop, 21 # id: (134, 590); nop for not ready instr (134, 133) +F4, 134, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 11, 1 # id: (134, 133); id: (58, 135); 0 1 0 1 w_1_11_0 +F4, 136, twntt, r4b3, r4b3, 33, 11, 0, 14, 1 # id: (136, 135); id: (58, 133); 0 1 0 1 w_1_11_0 +F4, 135, nop, 3 # id: (135, 591); nop for not ready instr (135, 134) +F4, 135, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (135, 134); id: (58, 134); 0 1 0 1 w_1_11_0 +F4, 137, nop, 21 # id: (137, 592); nop for not ready instr (137, 136) +F4, 137, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 12, 1 # id: (137, 136); id: (59, 138); 0 1 0 0 w_1_12_0 +F4, 139, twntt, r4b3, r4b3, 32, 12, 0, 14, 1 # id: (139, 138); id: (59, 136); 0 1 0 0 w_1_12_0 +F4, 138, nop, 3 # id: (138, 593); nop for not ready instr (138, 137) +F4, 138, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (138, 137); id: (59, 137); 0 1 0 0 w_1_12_0 +F4, 140, nop, 21 # id: (140, 594); nop for not ready instr (140, 139) +F4, 140, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 13, 1 # id: (140, 139); id: (60, 140); 0 1 0 -1 w_1_13_0 +F4, 141, nop, 4 # id: (141, 595); nop for not ready instr (141, 140) +F4, 141, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (141, 140); id: (60, 139); 0 1 0 -1 w_1_13_0 +F4, 142, move, r11b2, r6b0 # id: (142, 599); variable "rlk_0_0_1_0" +F4, 144, move, r13b2, r7b0 # id: (144, 603); variable "rlk_1_0_1_0" +F4, 142, nop, 19 # id: (142, 604); nop for not ready instr (142, 141) +F4, 142, mul, r12b2, r3b1, r11b2, 1 # id: (142, 141); id: (61, 141) +F4, 143, move, r11b1, r8b0 # id: (143, 608); variable "rlk_0_0_1_1" +F4, 144, mul, r14b2, r3b1, r13b2, 1 # id: (144, 143); id: (63, 143) +F4, 145, move, r12b1, r9b0 # id: (145, 612); variable "rlk_1_0_1_1" +F4, 143, nop, 2 # id: (143, 613); nop for not ready instr (143, 142) +F4, 143, mul, r5b3, r3b2, r11b1, 1 # id: (143, 142); id: (62, 142) +F4, 145, nop, 0 # id: (145, 614); nop for not ready instr (145, 144) +F4, 145, mul, r6b3, r3b2, r12b1, 1 # id: (145, 144); id: (64, 144) +F4, 4, bexit # id: (4, 615); terminating bundle 4 +F4, 4, nop, 0 # id: (4, 616) +F4, 4, nop, 0 # id: (4, 617) +F4, 4, nop, 0 # id: (4, 618) +F4, 4, nop, 0 # id: (4, 619) +F4, 4, nop, 0 # id: (4, 620) +F4, 4, nop, 0 # id: (4, 621) +F4, 4, nop, 0 # id: (4, 622) +F4, 4, nop, 0 # id: (4, 623) +F4, 4, nop, 0 # id: (4, 624) +F4, 4, nop, 0 # id: (4, 625) +F4, 4, nop, 0 # id: (4, 626) +F4, 4, nop, 0 # id: (4, 627) +F4, 4, nop, 0 # id: (4, 628) +F4, 4, nop, 0 # id: (4, 629) +F4, 4, nop, 0 # id: (4, 630) +F4, 4, nop, 0 # id: (4, 631) +F4, 4, nop, 0 # id: (4, 632) +F4, 4, nop, 0 # id: (4, 633) +F4, 4, nop, 0 # id: (4, 634) +F4, 4, nop, 0 # id: (4, 635) +F4, 4, nop, 0 # id: (4, 636) +F4, 4, nop, 0 # id: (4, 637) +F4, 4, nop, 0 # id: (4, 638) +F4, 4, nop, 0 # id: (4, 639) +F4, 4, nop, 0 # id: (4, 640) +F4, 4, nop, 0 # id: (4, 641) +F4, 4, nop, 0 # id: (4, 642) +F5, 146, rshuffle, r12b2, r5b3, r12b2, r5b3, 0, intt # id: (146, 145); id: (65, 146); 0 1 1 12 w_1_0_0 +F5, 248, nop, 3 # id: (248, 645); nop for not ready instr (248, 247) +F5, 248, rshuffle, r14b2, r6b3, r14b2, r6b3, 0, intt # id: (248, 247); id: (113, 248); 0 1 1 12 w_1_0_0 +F5, 147, nop, 16 # id: (147, 646); nop for not ready instr (147, 146) +F5, 147, intt, r15b2, r7b3, r12b2, r5b3, r13b1, 0, 1 # id: (147, 146); id: (65, 147); 0 1 1 12 w_1_0_0 +F5, 148, twintt, r13b1, r13b1, 60, 0, 0, 14, 1 # id: (148, 147); id: (65, 145); 0 1 1 12 w_1_0_0 +F5, 149, nop, 3 # id: (149, 647); nop for not ready instr (149, 148) +F5, 149, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (149, 148); id: (66, 149); 0 1 1 11 w_1_1_0 +F5, 150, nop, 21 # id: (150, 648); nop for not ready instr (150, 149) +F5, 150, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 1, 1 # id: (150, 149); id: (66, 150); 0 1 1 11 w_1_1_0 +F5, 151, twintt, r13b1, r13b1, 59, 1, 0, 14, 1 # id: (151, 150); id: (66, 148); 0 1 1 11 w_1_1_0 +F5, 152, nop, 3 # id: (152, 649); nop for not ready instr (152, 151) +F5, 152, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (152, 151); id: (67, 152); 0 1 1 10 w_1_2_0 +F5, 153, nop, 21 # id: (153, 650); nop for not ready instr (153, 152) +F5, 153, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 2, 1 # id: (153, 152); id: (67, 153); 0 1 1 10 w_1_2_0 +F5, 154, twintt, r13b1, r13b1, 58, 2, 0, 14, 1 # id: (154, 153); id: (67, 151); 0 1 1 10 w_1_2_0 +F5, 155, nop, 3 # id: (155, 651); nop for not ready instr (155, 154) +F5, 155, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (155, 154); id: (68, 155); 0 1 1 9 w_1_3_0 +F5, 156, nop, 21 # id: (156, 652); nop for not ready instr (156, 155) +F5, 156, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 3, 1 # id: (156, 155); id: (68, 156); 0 1 1 9 w_1_3_0 +F5, 157, twintt, r13b1, r13b1, 57, 3, 0, 14, 1 # id: (157, 156); id: (68, 154); 0 1 1 9 w_1_3_0 +F5, 158, nop, 3 # id: (158, 653); nop for not ready instr (158, 157) +F5, 158, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (158, 157); id: (69, 158); 0 1 1 8 w_1_4_0 +F5, 159, nop, 21 # id: (159, 654); nop for not ready instr (159, 158) +F5, 159, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 4, 1 # id: (159, 158); id: (69, 159); 0 1 1 8 w_1_4_0 +F5, 160, twintt, r13b1, r13b1, 56, 4, 0, 14, 1 # id: (160, 159); id: (69, 157); 0 1 1 8 w_1_4_0 +F5, 161, nop, 3 # id: (161, 655); nop for not ready instr (161, 160) +F5, 161, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (161, 160); id: (70, 161); 0 1 1 7 w_1_5_0 +F5, 162, nop, 21 # id: (162, 656); nop for not ready instr (162, 161) +F5, 162, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 5, 1 # id: (162, 161); id: (70, 162); 0 1 1 7 w_1_5_0 +F5, 163, twintt, r13b1, r13b1, 55, 5, 0, 14, 1 # id: (163, 162); id: (70, 160); 0 1 1 7 w_1_5_0 +F5, 164, nop, 3 # id: (164, 657); nop for not ready instr (164, 163) +F5, 164, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (164, 163); id: (71, 164); 0 1 1 6 w_1_6_0 +F5, 165, nop, 21 # id: (165, 658); nop for not ready instr (165, 164) +F5, 165, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 6, 1 # id: (165, 164); id: (71, 165); 0 1 1 6 w_1_6_0 +F5, 166, twintt, r13b1, r13b1, 54, 6, 0, 14, 1 # id: (166, 165); id: (71, 163); 0 1 1 6 w_1_6_0 +F5, 167, nop, 3 # id: (167, 659); nop for not ready instr (167, 166) +F5, 167, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (167, 166); id: (72, 167); 0 1 1 5 w_1_7_0 +F5, 168, nop, 21 # id: (168, 660); nop for not ready instr (168, 167) +F5, 168, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 7, 1 # id: (168, 167); id: (72, 168); 0 1 1 5 w_1_7_0 +F5, 169, twintt, r13b1, r13b1, 53, 7, 0, 14, 1 # id: (169, 168); id: (72, 166); 0 1 1 5 w_1_7_0 +F5, 170, nop, 3 # id: (170, 661); nop for not ready instr (170, 169) +F5, 170, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (170, 169); id: (73, 170); 0 1 1 4 w_1_8_0 +F5, 171, nop, 21 # id: (171, 662); nop for not ready instr (171, 170) +F5, 171, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 8, 1 # id: (171, 170); id: (73, 171); 0 1 1 4 w_1_8_0 +F5, 172, twintt, r13b1, r13b1, 52, 8, 0, 14, 1 # id: (172, 171); id: (73, 169); 0 1 1 4 w_1_8_0 +F5, 173, nop, 3 # id: (173, 663); nop for not ready instr (173, 172) +F5, 173, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (173, 172); id: (74, 173); 0 1 1 3 w_1_9_0 +F5, 174, nop, 21 # id: (174, 664); nop for not ready instr (174, 173) +F5, 174, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 9, 1 # id: (174, 173); id: (74, 174); 0 1 1 3 w_1_9_0 +F5, 175, twintt, r13b1, r13b1, 51, 9, 0, 14, 1 # id: (175, 174); id: (74, 172); 0 1 1 3 w_1_9_0 +F5, 176, nop, 3 # id: (176, 665); nop for not ready instr (176, 175) +F5, 176, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (176, 175); id: (75, 176); 0 1 1 2 w_1_10_0 +F5, 177, nop, 21 # id: (177, 666); nop for not ready instr (177, 176) +F5, 177, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 10, 1 # id: (177, 176); id: (75, 177); 0 1 1 2 w_1_10_0 +F5, 178, twintt, r13b1, r13b1, 50, 10, 0, 14, 1 # id: (178, 177); id: (75, 175); 0 1 1 2 w_1_10_0 +F5, 179, nop, 3 # id: (179, 667); nop for not ready instr (179, 178) +F5, 179, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (179, 178); id: (76, 179); 0 1 1 1 w_1_11_0 +F5, 180, nop, 21 # id: (180, 668); nop for not ready instr (180, 179) +F5, 180, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 11, 1 # id: (180, 179); id: (76, 180); 0 1 1 1 w_1_11_0 +F5, 181, twintt, r13b1, r13b1, 49, 11, 0, 14, 1 # id: (181, 180); id: (76, 178); 0 1 1 1 w_1_11_0 +F5, 182, nop, 3 # id: (182, 669); nop for not ready instr (182, 181) +F5, 182, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (182, 181); id: (77, 182); 0 1 1 0 w_1_12_0 +F5, 5, bexit # id: (5, 670); terminating bundle 5 +F6, 183, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 12, 1 # id: (183, 182); id: (77, 183); 0 1 1 0 w_1_12_0 +F6, 184, twintt, r13b1, r13b1, 48, 12, 0, 14, 1 # id: (184, 183); id: (77, 181); 0 1 1 0 w_1_12_0 +F6, 185, nop, 3 # id: (185, 675); nop for not ready instr (185, 184) +F6, 185, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (185, 184); id: (78, 184); 0 1 1 -1 w_1_13_0 +F6, 186, nop, 21 # id: (186, 676); nop for not ready instr (186, 185) +F6, 186, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 13, 1 # id: (186, 185); id: (78, 185); 0 1 1 -1 w_1_13_0 +F6, 249, intt, r15b2, r7b3, r14b2, r6b3, r14b1, 0, 1 # id: (249, 248); id: (113, 249); 0 1 1 12 w_1_0_0 +F6, 250, twintt, r14b1, r14b1, 60, 0, 0, 14, 1 # id: (250, 249); id: (113, 247); 0 1 1 12 w_1_0_0 +F6, 188, move, r15b1, r0b0 # id: (188, 680); variable "ipsi_1_1" +F6, 187, move, r16b1, r1b0 # id: (187, 684); variable "ipsi_1_0" +F6, 251, nop, 1 # id: (251, 685); nop for not ready instr (251, 250) +F6, 251, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (251, 250); id: (114, 251); 0 1 1 11 w_1_1_0 +F6, 188, nop, 0 # id: (188, 686); nop for not ready instr (188, 187) +F6, 188, mul, r8b3, r8b3, r15b1, 1 # id: (188, 187); id: (80, 187) +F6, 187, mul, r16b2, r16b2, r16b1, 1 # id: (187, 186); id: (79, 186) +F6, 190, nop, 3 # id: (190, 687); nop for not ready instr (190, 189) +F6, 190, muli, r8b3, r8b3, iN, 1 # id: (190, 189); id: (82, 189) +F6, 189, muli, r16b2, r16b2, iN, 1 # id: (189, 188); id: (81, 188) +F6, 192, nop, 3 # id: (192, 688); nop for not ready instr (192, 191) +F6, 192, muli, r8b3, r8b3, t_inverse_mod_p_0, 1 # id: (192, 191); id: (84, 191) +F6, 191, muli, r16b2, r16b2, t_inverse_mod_p_0, 1 # id: (191, 190); id: (83, 190) +F6, 194, nop, 3 # id: (194, 689); nop for not ready instr (194, 193) +F6, 194, muli, r8b3, r8b3, one, 1 # id: (194, 193); id: (86, 193) +F6, 193, muli, r16b2, r16b2, one, 1 # id: (193, 192); id: (85, 192) +F6, 196, nop, 3 # id: (196, 690); nop for not ready instr (196, 195) +F6, 196, muli, r3b2, r8b3, R2_0, 0 # id: (196, 195); id: (88, 195) +F6, 195, muli, r3b1, r16b2, R2_0, 0 # id: (195, 194); id: (87, 194) +F6, 252, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 1, 1 # id: (252, 251); id: (114, 252); 0 1 1 11 w_1_1_0 +F6, 253, twintt, r14b1, r14b1, 59, 1, 0, 14, 1 # id: (253, 252); id: (114, 250); 0 1 1 11 w_1_1_0 +F6, 198, nop, 1 # id: (198, 691); nop for not ready instr (198, 197) +F6, 198, mul, r3b2, r3b2, r4b1, 0 # id: (198, 197); id: (90, 197) +F6, 197, mul, r3b1, r3b1, r4b2, 0 # id: (197, 196); id: (89, 196) +F6, 254, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (254, 253); id: (115, 254); 0 1 1 10 w_1_2_0 +F6, 199, nop, 3 # id: (199, 692); nop for not ready instr (199, 198) +F6, 199, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 0, 0 # id: (199, 198); id: (91, 200); 0 0 0 12 w_0_0_0 +F6, 201, twntt, r9b3, r9b3, 12, 0, 0, 14, 0 # id: (201, 200); id: (91, 198); 0 0 0 12 w_0_0_0 +F6, 255, nop, 15 # id: (255, 693); nop for not ready instr (255, 254) +F6, 255, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 2, 1 # id: (255, 254); id: (115, 255); 0 1 1 10 w_1_2_0 +F6, 256, twintt, r14b1, r14b1, 58, 2, 0, 14, 1 # id: (256, 255); id: (115, 253); 0 1 1 10 w_1_2_0 +F6, 257, nop, 3 # id: (257, 694); nop for not ready instr (257, 256) +F6, 257, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (257, 256); id: (116, 257); 0 1 1 9 w_1_3_0 +F6, 258, nop, 21 # id: (258, 695); nop for not ready instr (258, 257) +F6, 258, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 3, 1 # id: (258, 257); id: (116, 258); 0 1 1 9 w_1_3_0 +F6, 259, twintt, r14b1, r14b1, 57, 3, 0, 14, 1 # id: (259, 258); id: (116, 256); 0 1 1 9 w_1_3_0 +F6, 260, nop, 3 # id: (260, 696); nop for not ready instr (260, 259) +F6, 260, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (260, 259); id: (117, 260); 0 1 1 8 w_1_4_0 +F6, 261, nop, 21 # id: (261, 697); nop for not ready instr (261, 260) +F6, 261, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 4, 1 # id: (261, 260); id: (117, 261); 0 1 1 8 w_1_4_0 +F6, 262, twintt, r14b1, r14b1, 56, 4, 0, 14, 1 # id: (262, 261); id: (117, 259); 0 1 1 8 w_1_4_0 +F6, 263, nop, 3 # id: (263, 698); nop for not ready instr (263, 262) +F6, 263, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (263, 262); id: (118, 263); 0 1 1 7 w_1_5_0 +F6, 264, nop, 21 # id: (264, 699); nop for not ready instr (264, 263) +F6, 264, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 5, 1 # id: (264, 263); id: (118, 264); 0 1 1 7 w_1_5_0 +F6, 265, twintt, r14b1, r14b1, 55, 5, 0, 14, 1 # id: (265, 264); id: (118, 262); 0 1 1 7 w_1_5_0 +F6, 266, nop, 3 # id: (266, 700); nop for not ready instr (266, 265) +F6, 266, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (266, 265); id: (119, 266); 0 1 1 6 w_1_6_0 +F6, 267, nop, 21 # id: (267, 701); nop for not ready instr (267, 266) +F6, 267, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 6, 1 # id: (267, 266); id: (119, 267); 0 1 1 6 w_1_6_0 +F6, 268, twintt, r14b1, r14b1, 54, 6, 0, 14, 1 # id: (268, 267); id: (119, 265); 0 1 1 6 w_1_6_0 +F6, 269, nop, 3 # id: (269, 702); nop for not ready instr (269, 268) +F6, 269, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (269, 268); id: (120, 269); 0 1 1 5 w_1_7_0 +F6, 270, nop, 21 # id: (270, 703); nop for not ready instr (270, 269) +F6, 270, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 7, 1 # id: (270, 269); id: (120, 270); 0 1 1 5 w_1_7_0 +F6, 271, twintt, r14b1, r14b1, 53, 7, 0, 14, 1 # id: (271, 270); id: (120, 268); 0 1 1 5 w_1_7_0 +F7, 272, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (272, 271); id: (121, 272); 0 1 1 4 w_1_8_0 +F7, 273, nop, 21 # id: (273, 706); nop for not ready instr (273, 272) +F7, 273, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 8, 1 # id: (273, 272); id: (121, 273); 0 1 1 4 w_1_8_0 +F7, 274, twintt, r14b1, r14b1, 52, 8, 0, 14, 1 # id: (274, 273); id: (121, 271); 0 1 1 4 w_1_8_0 +F7, 275, nop, 3 # id: (275, 707); nop for not ready instr (275, 274) +F7, 275, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (275, 274); id: (122, 275); 0 1 1 3 w_1_9_0 +F7, 276, nop, 21 # id: (276, 708); nop for not ready instr (276, 275) +F7, 276, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 9, 1 # id: (276, 275); id: (122, 276); 0 1 1 3 w_1_9_0 +F7, 277, twintt, r14b1, r14b1, 51, 9, 0, 14, 1 # id: (277, 276); id: (122, 274); 0 1 1 3 w_1_9_0 +F7, 278, nop, 3 # id: (278, 709); nop for not ready instr (278, 277) +F7, 278, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (278, 277); id: (123, 278); 0 1 1 2 w_1_10_0 +F7, 279, nop, 21 # id: (279, 710); nop for not ready instr (279, 278) +F7, 279, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 10, 1 # id: (279, 278); id: (123, 279); 0 1 1 2 w_1_10_0 +F7, 280, twintt, r14b1, r14b1, 50, 10, 0, 14, 1 # id: (280, 279); id: (123, 277); 0 1 1 2 w_1_10_0 +F7, 281, nop, 3 # id: (281, 711); nop for not ready instr (281, 280) +F7, 281, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (281, 280); id: (124, 281); 0 1 1 1 w_1_11_0 +F7, 282, nop, 21 # id: (282, 712); nop for not ready instr (282, 281) +F7, 282, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 11, 1 # id: (282, 281); id: (124, 282); 0 1 1 1 w_1_11_0 +F7, 283, twintt, r14b1, r14b1, 49, 11, 0, 14, 1 # id: (283, 282); id: (124, 280); 0 1 1 1 w_1_11_0 +F7, 284, nop, 3 # id: (284, 713); nop for not ready instr (284, 283) +F7, 284, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (284, 283); id: (125, 284); 0 1 1 0 w_1_12_0 +F7, 285, nop, 21 # id: (285, 714); nop for not ready instr (285, 284) +F7, 285, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 12, 1 # id: (285, 284); id: (125, 285); 0 1 1 0 w_1_12_0 +F7, 286, twintt, r14b1, r14b1, 48, 12, 0, 14, 1 # id: (286, 285); id: (125, 283); 0 1 1 0 w_1_12_0 +F7, 287, nop, 3 # id: (287, 715); nop for not ready instr (287, 286) +F7, 287, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (287, 286); id: (126, 286); 0 1 1 -1 w_1_13_0 +F7, 288, nop, 21 # id: (288, 716); nop for not ready instr (288, 287) +F7, 288, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 13, 1 # id: (288, 287); id: (126, 287); 0 1 1 -1 w_1_13_0 +F7, 289, nop, 4 # id: (289, 717); nop for not ready instr (289, 288) +F7, 289, mul, r16b2, r16b2, r16b1, 1 # id: (289, 288); id: (127, 288) +F7, 290, mul, r8b3, r8b3, r15b1, 1 # id: (290, 289); id: (128, 289) +F7, 291, nop, 3 # id: (291, 718); nop for not ready instr (291, 290) +F7, 291, muli, r16b2, r16b2, iN, 1 # id: (291, 290); id: (129, 290) +F7, 292, muli, r8b3, r8b3, iN, 1 # id: (292, 291); id: (130, 291) +F7, 293, nop, 3 # id: (293, 719); nop for not ready instr (293, 292) +F7, 293, muli, r16b2, r16b2, t_inverse_mod_p_0, 1 # id: (293, 292); id: (131, 292) +F7, 294, muli, r8b3, r8b3, t_inverse_mod_p_0, 1 # id: (294, 293); id: (132, 293) +F7, 295, nop, 3 # id: (295, 720); nop for not ready instr (295, 294) +F7, 295, muli, r16b2, r16b2, one, 1 # id: (295, 294); id: (133, 294) +F7, 296, muli, r8b3, r8b3, one, 1 # id: (296, 295); id: (134, 295) +F7, 7, bexit # id: (7, 721); terminating bundle 7 +F7, 7, nop, 0 # id: (7, 722) +F7, 7, nop, 0 # id: (7, 723) +F7, 7, nop, 0 # id: (7, 724) +F7, 7, nop, 0 # id: (7, 725) +F7, 7, nop, 0 # id: (7, 726) +F7, 7, nop, 0 # id: (7, 727) +F7, 7, nop, 0 # id: (7, 728) +F7, 7, nop, 0 # id: (7, 729) +F7, 7, nop, 0 # id: (7, 730) +F7, 7, nop, 0 # id: (7, 731) +F7, 7, nop, 0 # id: (7, 732) +F7, 7, nop, 0 # id: (7, 733) +F7, 7, nop, 0 # id: (7, 734) +F7, 7, nop, 0 # id: (7, 735) +F7, 7, nop, 0 # id: (7, 736) +F7, 7, nop, 0 # id: (7, 737) +F7, 7, nop, 0 # id: (7, 738) +F7, 7, nop, 0 # id: (7, 739) +F7, 7, nop, 0 # id: (7, 740) +F7, 7, nop, 0 # id: (7, 741) +F7, 7, nop, 0 # id: (7, 742) +F7, 7, nop, 0 # id: (7, 743) +F7, 7, nop, 0 # id: (7, 744) +F8, 200, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (200, 199); id: (91, 199); 0 0 0 12 w_0_0_0 +F8, 202, nop, 21 # id: (202, 747); nop for not ready instr (202, 201) +F8, 202, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 1, 0 # id: (202, 201); id: (92, 203); 0 0 0 11 w_0_1_0 +F8, 204, twntt, r9b3, r9b3, 11, 1, 0, 14, 0 # id: (204, 203); id: (92, 201); 0 0 0 11 w_0_1_0 +F8, 203, nop, 3 # id: (203, 748); nop for not ready instr (203, 202) +F8, 203, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (203, 202); id: (92, 202); 0 0 0 11 w_0_1_0 +F8, 205, nop, 21 # id: (205, 749); nop for not ready instr (205, 204) +F8, 205, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 2, 0 # id: (205, 204); id: (93, 206); 0 0 0 10 w_0_2_0 +F8, 207, twntt, r9b3, r9b3, 10, 2, 0, 14, 0 # id: (207, 206); id: (93, 204); 0 0 0 10 w_0_2_0 +F8, 206, nop, 3 # id: (206, 750); nop for not ready instr (206, 205) +F8, 206, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (206, 205); id: (93, 205); 0 0 0 10 w_0_2_0 +F8, 208, nop, 21 # id: (208, 751); nop for not ready instr (208, 207) +F8, 208, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 3, 0 # id: (208, 207); id: (94, 209); 0 0 0 9 w_0_3_0 +F8, 210, twntt, r9b3, r9b3, 9, 3, 0, 14, 0 # id: (210, 209); id: (94, 207); 0 0 0 9 w_0_3_0 +F8, 209, nop, 3 # id: (209, 752); nop for not ready instr (209, 208) +F8, 209, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (209, 208); id: (94, 208); 0 0 0 9 w_0_3_0 +F8, 211, nop, 21 # id: (211, 753); nop for not ready instr (211, 210) +F8, 211, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 4, 0 # id: (211, 210); id: (95, 212); 0 0 0 8 w_0_4_0 +F8, 213, twntt, r9b3, r9b3, 8, 4, 0, 14, 0 # id: (213, 212); id: (95, 210); 0 0 0 8 w_0_4_0 +F8, 212, nop, 3 # id: (212, 754); nop for not ready instr (212, 211) +F8, 212, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (212, 211); id: (95, 211); 0 0 0 8 w_0_4_0 +F8, 214, nop, 21 # id: (214, 755); nop for not ready instr (214, 213) +F8, 214, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 5, 0 # id: (214, 213); id: (96, 215); 0 0 0 7 w_0_5_0 +F8, 216, twntt, r9b3, r9b3, 7, 5, 0, 14, 0 # id: (216, 215); id: (96, 213); 0 0 0 7 w_0_5_0 +F8, 215, nop, 3 # id: (215, 756); nop for not ready instr (215, 214) +F8, 215, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (215, 214); id: (96, 214); 0 0 0 7 w_0_5_0 +F8, 217, nop, 21 # id: (217, 757); nop for not ready instr (217, 216) +F8, 217, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 6, 0 # id: (217, 216); id: (97, 218); 0 0 0 6 w_0_6_0 +F8, 219, twntt, r9b3, r9b3, 6, 6, 0, 14, 0 # id: (219, 218); id: (97, 216); 0 0 0 6 w_0_6_0 +F8, 218, nop, 3 # id: (218, 758); nop for not ready instr (218, 217) +F8, 218, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (218, 217); id: (97, 217); 0 0 0 6 w_0_6_0 +F8, 220, nop, 21 # id: (220, 759); nop for not ready instr (220, 219) +F8, 220, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 7, 0 # id: (220, 219); id: (98, 221); 0 0 0 5 w_0_7_0 +F8, 222, twntt, r9b3, r9b3, 5, 7, 0, 14, 0 # id: (222, 221); id: (98, 219); 0 0 0 5 w_0_7_0 +F8, 221, nop, 3 # id: (221, 760); nop for not ready instr (221, 220) +F8, 221, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (221, 220); id: (98, 220); 0 0 0 5 w_0_7_0 +F8, 223, nop, 21 # id: (223, 761); nop for not ready instr (223, 222) +F8, 223, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 8, 0 # id: (223, 222); id: (99, 224); 0 0 0 4 w_0_8_0 +F8, 225, twntt, r9b3, r9b3, 4, 8, 0, 14, 0 # id: (225, 224); id: (99, 222); 0 0 0 4 w_0_8_0 +F8, 224, nop, 3 # id: (224, 762); nop for not ready instr (224, 223) +F8, 224, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (224, 223); id: (99, 223); 0 0 0 4 w_0_8_0 +F8, 226, nop, 21 # id: (226, 763); nop for not ready instr (226, 225) +F8, 226, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 9, 0 # id: (226, 225); id: (100, 227); 0 0 0 3 w_0_9_0 +F8, 228, twntt, r9b3, r9b3, 3, 9, 0, 14, 0 # id: (228, 227); id: (100, 225); 0 0 0 3 w_0_9_0 +F8, 227, nop, 3 # id: (227, 764); nop for not ready instr (227, 226) +F8, 227, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (227, 226); id: (100, 226); 0 0 0 3 w_0_9_0 +F8, 229, nop, 21 # id: (229, 765); nop for not ready instr (229, 228) +F8, 229, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 10, 0 # id: (229, 228); id: (101, 230); 0 0 0 2 w_0_10_0 +F8, 231, twntt, r9b3, r9b3, 2, 10, 0, 14, 0 # id: (231, 230); id: (101, 228); 0 0 0 2 w_0_10_0 +F8, 230, nop, 3 # id: (230, 766); nop for not ready instr (230, 229) +F8, 230, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (230, 229); id: (101, 229); 0 0 0 2 w_0_10_0 +F8, 232, nop, 21 # id: (232, 767); nop for not ready instr (232, 231) +F8, 232, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 11, 0 # id: (232, 231); id: (102, 233); 0 0 0 1 w_0_11_0 +F8, 234, twntt, r9b3, r9b3, 1, 11, 0, 14, 0 # id: (234, 233); id: (102, 231); 0 0 0 1 w_0_11_0 +F8, 233, nop, 3 # id: (233, 768); nop for not ready instr (233, 232) +F8, 233, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (233, 232); id: (102, 232); 0 0 0 1 w_0_11_0 +F8, 235, nop, 21 # id: (235, 769); nop for not ready instr (235, 234) +F8, 235, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 12, 0 # id: (235, 234); id: (103, 236); 0 0 0 0 w_0_12_0 +F8, 237, twntt, r9b3, r9b3, 0, 12, 0, 14, 0 # id: (237, 236); id: (103, 234); 0 0 0 0 w_0_12_0 +F8, 236, nop, 3 # id: (236, 770); nop for not ready instr (236, 235) +F8, 236, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (236, 235); id: (103, 235); 0 0 0 0 w_0_12_0 +F8, 238, nop, 21 # id: (238, 771); nop for not ready instr (238, 237) +F8, 238, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 13, 0 # id: (238, 237); id: (104, 238); 0 0 0 -1 w_0_13_0 +F8, 8, bexit # id: (8, 772); terminating bundle 8 +F9, 239, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (239, 238); id: (104, 237); 0 0 0 -1 w_0_13_0 +F9, 240, nop, 21 # id: (240, 777); nop for not ready instr (240, 239) +F9, 240, muli, r3b1, r3b1, t_0, 0 # id: (240, 239); id: (105, 239) +F9, 241, muli, r3b2, r3b2, t_0, 0 # id: (241, 240); id: (106, 240) +F9, 242, nop, 3 # id: (242, 778); nop for not ready instr (242, 241) +F9, 242, add, r3b1, r3b1, r7b2, 0 # id: (242, 241); id: (107, 241) +F9, 243, add, r3b2, r3b2, r7b1, 0 # id: (243, 242); id: (108, 242) +F9, 244, nop, 3 # id: (244, 779); nop for not ready instr (244, 243) +F9, 244, muli, r3b1, r3b1, pinv_q_0, 0 # id: (244, 243); id: (109, 243) +F9, 245, muli, r3b2, r3b2, pinv_q_0, 0 # id: (245, 244); id: (110, 244) +F9, 246, move, r17b2, r0b0 # id: (246, 783); variable "ct0_0_0_0" +F9, 247, move, r18b1, r1b0 # id: (247, 787); variable "ct0_0_0_1" +F9, 246, nop, 3 # id: (246, 788); nop for not ready instr (246, 245) +F9, 246, add, r17b1, r3b1, r17b2, 0 # id: (246, 245); id: (111, 245) +F9, 247, add, r19b1, r3b2, r18b1, 0 # id: (247, 246); id: (112, 246) +F9, 297, muli, r3b1, r16b2, R2_0, 0 # id: (297, 296); id: (135, 296) +F9, 298, muli, r3b2, r8b3, R2_0, 0 # id: (298, 297); id: (136, 297) +F9, 246, nop, 1 # id: (246, 791); nop for not ready instr (246, 789) +F9, 246, xstore, r17b1 # id: (246, 789); flushing output; variable "ct1_0_0_0": SPAD(33) <- r17b1 +F9, 299, nop, 0 # id: (299, 793); nop for not ready instr (299, 298) +F9, 299, mul, r3b1, r3b1, r4b2, 0 # id: (299, 298); id: (137, 298) +F9, 300, mul, r3b2, r3b2, r4b1, 0 # id: (300, 299); id: (138, 299) +F9, 247, nop, 1 # id: (247, 794); nop for not ready instr (247, 790) +F9, 247, xstore, r19b1 # id: (247, 790); flushing output; variable "ct1_0_0_1": SPAD(34) <- r19b1 +F9, 301, nop, 1 # id: (301, 796); nop for not ready instr (301, 300) +F9, 301, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 0, 0 # id: (301, 300); id: (139, 302); 0 0 0 12 w_0_0_0 +F9, 303, twntt, r10b3, r10b3, 12, 0, 0, 14, 0 # id: (303, 302); id: (139, 300); 0 0 0 12 w_0_0_0 +F9, 302, nop, 3 # id: (302, 797); nop for not ready instr (302, 301) +F9, 302, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (302, 301); id: (139, 301); 0 0 0 12 w_0_0_0 +F9, 304, nop, 21 # id: (304, 798); nop for not ready instr (304, 303) +F9, 304, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 1, 0 # id: (304, 303); id: (140, 305); 0 0 0 11 w_0_1_0 +F9, 306, twntt, r10b3, r10b3, 11, 1, 0, 14, 0 # id: (306, 305); id: (140, 303); 0 0 0 11 w_0_1_0 +F9, 305, nop, 3 # id: (305, 799); nop for not ready instr (305, 304) +F9, 305, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (305, 304); id: (140, 304); 0 0 0 11 w_0_1_0 +F9, 307, nop, 21 # id: (307, 800); nop for not ready instr (307, 306) +F9, 307, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 2, 0 # id: (307, 306); id: (141, 308); 0 0 0 10 w_0_2_0 +F9, 309, twntt, r10b3, r10b3, 10, 2, 0, 14, 0 # id: (309, 308); id: (141, 306); 0 0 0 10 w_0_2_0 +F9, 308, nop, 3 # id: (308, 801); nop for not ready instr (308, 307) +F9, 308, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (308, 307); id: (141, 307); 0 0 0 10 w_0_2_0 +F9, 310, nop, 21 # id: (310, 802); nop for not ready instr (310, 309) +F9, 310, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 3, 0 # id: (310, 309); id: (142, 311); 0 0 0 9 w_0_3_0 +F9, 312, twntt, r10b3, r10b3, 9, 3, 0, 14, 0 # id: (312, 311); id: (142, 309); 0 0 0 9 w_0_3_0 +F9, 311, nop, 3 # id: (311, 803); nop for not ready instr (311, 310) +F9, 311, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (311, 310); id: (142, 310); 0 0 0 9 w_0_3_0 +F9, 313, nop, 21 # id: (313, 804); nop for not ready instr (313, 312) +F9, 313, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 4, 0 # id: (313, 312); id: (143, 314); 0 0 0 8 w_0_4_0 +F9, 315, twntt, r10b3, r10b3, 8, 4, 0, 14, 0 # id: (315, 314); id: (143, 312); 0 0 0 8 w_0_4_0 +F9, 314, nop, 3 # id: (314, 805); nop for not ready instr (314, 313) +F9, 314, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (314, 313); id: (143, 313); 0 0 0 8 w_0_4_0 +F9, 316, nop, 21 # id: (316, 806); nop for not ready instr (316, 315) +F9, 316, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 5, 0 # id: (316, 315); id: (144, 317); 0 0 0 7 w_0_5_0 +F9, 318, twntt, r10b3, r10b3, 7, 5, 0, 14, 0 # id: (318, 317); id: (144, 315); 0 0 0 7 w_0_5_0 +F9, 317, nop, 3 # id: (317, 807); nop for not ready instr (317, 316) +F9, 317, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (317, 316); id: (144, 316); 0 0 0 7 w_0_5_0 +F9, 319, nop, 21 # id: (319, 808); nop for not ready instr (319, 318) +F9, 319, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 6, 0 # id: (319, 318); id: (145, 320); 0 0 0 6 w_0_6_0 +F9, 321, twntt, r10b3, r10b3, 6, 6, 0, 14, 0 # id: (321, 320); id: (145, 318); 0 0 0 6 w_0_6_0 +F9, 320, nop, 3 # id: (320, 809); nop for not ready instr (320, 319) +F9, 320, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (320, 319); id: (145, 319); 0 0 0 6 w_0_6_0 +F9, 322, nop, 21 # id: (322, 810); nop for not ready instr (322, 321) +F9, 322, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 7, 0 # id: (322, 321); id: (146, 323); 0 0 0 5 w_0_7_0 +F9, 324, twntt, r10b3, r10b3, 5, 7, 0, 14, 0 # id: (324, 323); id: (146, 321); 0 0 0 5 w_0_7_0 +F9, 323, nop, 3 # id: (323, 811); nop for not ready instr (323, 322) +F9, 323, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (323, 322); id: (146, 322); 0 0 0 5 w_0_7_0 +F10, 325, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 8, 0 # id: (325, 324); id: (147, 326); 0 0 0 4 w_0_8_0 +F10, 327, twntt, r10b3, r10b3, 4, 8, 0, 14, 0 # id: (327, 326); id: (147, 324); 0 0 0 4 w_0_8_0 +F10, 326, nop, 3 # id: (326, 818); nop for not ready instr (326, 325) +F10, 326, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (326, 325); id: (147, 325); 0 0 0 4 w_0_8_0 +F10, 328, nop, 21 # id: (328, 819); nop for not ready instr (328, 327) +F10, 328, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 9, 0 # id: (328, 327); id: (148, 329); 0 0 0 3 w_0_9_0 +F10, 330, twntt, r10b3, r10b3, 3, 9, 0, 14, 0 # id: (330, 329); id: (148, 327); 0 0 0 3 w_0_9_0 +F10, 329, nop, 3 # id: (329, 820); nop for not ready instr (329, 328) +F10, 329, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (329, 328); id: (148, 328); 0 0 0 3 w_0_9_0 +F10, 331, nop, 21 # id: (331, 821); nop for not ready instr (331, 330) +F10, 331, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 10, 0 # id: (331, 330); id: (149, 332); 0 0 0 2 w_0_10_0 +F10, 333, twntt, r10b3, r10b3, 2, 10, 0, 14, 0 # id: (333, 332); id: (149, 330); 0 0 0 2 w_0_10_0 +F10, 332, nop, 3 # id: (332, 822); nop for not ready instr (332, 331) +F10, 332, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (332, 331); id: (149, 331); 0 0 0 2 w_0_10_0 +F10, 334, nop, 21 # id: (334, 823); nop for not ready instr (334, 333) +F10, 334, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 11, 0 # id: (334, 333); id: (150, 335); 0 0 0 1 w_0_11_0 +F10, 336, twntt, r10b3, r10b3, 1, 11, 0, 14, 0 # id: (336, 335); id: (150, 333); 0 0 0 1 w_0_11_0 +F10, 335, nop, 3 # id: (335, 824); nop for not ready instr (335, 334) +F10, 335, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (335, 334); id: (150, 334); 0 0 0 1 w_0_11_0 +F10, 337, nop, 21 # id: (337, 825); nop for not ready instr (337, 336) +F10, 337, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 12, 0 # id: (337, 336); id: (151, 338); 0 0 0 0 w_0_12_0 +F10, 339, twntt, r10b3, r10b3, 0, 12, 0, 14, 0 # id: (339, 338); id: (151, 336); 0 0 0 0 w_0_12_0 +F10, 338, nop, 3 # id: (338, 826); nop for not ready instr (338, 337) +F10, 338, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (338, 337); id: (151, 337); 0 0 0 0 w_0_12_0 +F10, 340, nop, 21 # id: (340, 827); nop for not ready instr (340, 339) +F10, 340, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 13, 0 # id: (340, 339); id: (152, 340); 0 0 0 -1 w_0_13_0 +F10, 341, nop, 4 # id: (341, 828); nop for not ready instr (341, 340) +F10, 341, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (341, 340); id: (152, 339); 0 0 0 -1 w_0_13_0 +F10, 342, nop, 21 # id: (342, 829); nop for not ready instr (342, 341) +F10, 342, muli, r3b1, r3b1, t_0, 0 # id: (342, 341); id: (153, 341) +F10, 343, muli, r3b2, r3b2, t_0, 0 # id: (343, 342); id: (154, 342) +F10, 344, nop, 3 # id: (344, 830); nop for not ready instr (344, 343) +F10, 344, add, r3b1, r3b1, r9b2, 0 # id: (344, 343); id: (155, 343) +F10, 345, add, r3b2, r3b2, r9b1, 0 # id: (345, 344); id: (156, 344) +F10, 346, nop, 3 # id: (346, 831); nop for not ready instr (346, 345) +F10, 346, muli, r3b1, r3b1, pinv_q_0, 0 # id: (346, 345); id: (157, 345) +F10, 347, muli, r3b2, r3b2, pinv_q_0, 0 # id: (347, 346); id: (158, 346) +F10, 348, move, r18b2, r2b0 # id: (348, 835); variable "ct0_1_0_0" +F10, 349, move, r19b1, r3b0 # id: (349, 839); variable "ct0_1_0_1" +F10, 348, nop, 3 # id: (348, 840); nop for not ready instr (348, 347) +F10, 348, add, r17b1, r3b1, r18b2, 0 # id: (348, 347); id: (159, 347) +F10, 349, add, r20b1, r3b2, r19b1, 0 # id: (349, 348); id: (160, 348) +F10, 348, nop, 3 # id: (348, 843); nop for not ready instr (348, 841) +F10, 348, xstore, r17b1 # id: (348, 841); flushing output; variable "ct1_1_0_0": SPAD(35) <- r17b1 +F10, 349, nop, 4 # id: (349, 845); nop for not ready instr (349, 842) +F10, 349, xstore, r20b1 # id: (349, 842); flushing output; variable "ct1_1_0_1": SPAD(36) <- r20b1 +F10, 10, bexit # id: (10, 847); terminating bundle 10 +F10, 10, nop, 0 # id: (10, 848) +F10, 10, nop, 0 # id: (10, 849) +F10, 10, nop, 0 # id: (10, 850) +F10, 10, nop, 0 # id: (10, 851) +F10, 10, nop, 0 # id: (10, 852) +F10, 10, nop, 0 # id: (10, 853) +F10, 10, nop, 0 # id: (10, 854) +F10, 10, nop, 0 # id: (10, 855) +F10, 10, nop, 0 # id: (10, 856) +F10, 10, nop, 0 # id: (10, 857) +F10, 10, nop, 0 # id: (10, 858) +F10, 10, nop, 0 # id: (10, 859) +F10, 10, nop, 0 # id: (10, 860) +F10, 10, nop, 0 # id: (10, 861) +F10, 10, nop, 0 # id: (10, 862) +F10, 10, nop, 0 # id: (10, 863) +F10, 10, nop, 0 # id: (10, 864) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..84c10cc3 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.cinst @@ -0,0 +1,67 @@ +0, csyncm, 4 # id: (0, 20) +1, bload, 0, twid_4, 0 # id: (0, 21); loading twid metadata for residuals [0, 64) +2, bload, 1, twid_4, 1 # id: (0, 22); loading twid metadata for residuals [0, 64) +3, bload, 2, twid_4, 2 # id: (0, 23); loading twid metadata for residuals [0, 64) +4, bload, 3, twid_4, 3 # id: (0, 24); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 25) +6, bload, 4, twid_5, 0 # id: (0, 26); loading twid metadata for residuals [0, 64) +7, bload, 5, twid_5, 1 # id: (0, 27); loading twid metadata for residuals [0, 64) +8, bload, 6, twid_5, 2 # id: (0, 28); loading twid metadata for residuals [0, 64) +9, bload, 7, twid_5, 3 # id: (0, 29); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 30) +11, bload, 8, twid_6, 0 # id: (0, 31); loading twid metadata for residuals [0, 64) +12, bload, 9, twid_6, 1 # id: (0, 32); loading twid metadata for residuals [0, 64) +13, bload, 10, twid_6, 2 # id: (0, 33); loading twid metadata for residuals [0, 64) +14, bload, 11, twid_6, 3 # id: (0, 34); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 35) +16, bload, 12, twid_7, 0 # id: (0, 36); loading twid metadata for residuals [0, 64) +17, bload, 13, twid_7, 1 # id: (0, 37); loading twid metadata for residuals [0, 64) +18, bload, 14, twid_7, 2 # id: (0, 38); loading twid metadata for residuals [0, 64) +19, bload, 15, twid_7, 3 # id: (0, 39); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 40) +21, bload, 16, twid_8, 0 # id: (0, 41); loading twid metadata for residuals [0, 64) +22, bload, 17, twid_8, 1 # id: (0, 42); loading twid metadata for residuals [0, 64) +23, bload, 18, twid_8, 2 # id: (0, 43); loading twid metadata for residuals [0, 64) +24, bload, 19, twid_8, 3 # id: (0, 44); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 45) +26, bload, 20, twid_9, 0 # id: (0, 46); loading twid metadata for residuals [0, 64) +27, bload, 21, twid_9, 1 # id: (0, 47); loading twid metadata for residuals [0, 64) +28, bload, 22, twid_9, 2 # id: (0, 48); loading twid metadata for residuals [0, 64) +29, bload, 23, twid_9, 3 # id: (0, 49); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 50) +31, bload, 24, twid_10, 0 # id: (0, 51); loading twid metadata for residuals [0, 64) +32, bload, 25, twid_10, 1 # id: (0, 52); loading twid metadata for residuals [0, 64) +33, bload, 26, twid_10, 2 # id: (0, 53); loading twid metadata for residuals [0, 64) +34, bload, 27, twid_10, 3 # id: (0, 54); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 55) +36, bload, 28, twid_11, 0 # id: (0, 56); loading twid metadata for residuals [0, 64) +37, bload, 29, twid_11, 1 # id: (0, 57); loading twid metadata for residuals [0, 64) +38, bload, 30, twid_11, 2 # id: (0, 58); loading twid metadata for residuals [0, 64) +39, bload, 31, twid_11, 3 # id: (0, 59); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 61) +41, bones, ones_12, 0 # id: (0, 62); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 65) +43, cload, r0b0, ct0_0_0_0 # id: (1, 66); dep id: (1, 0); ct0_0_0_0 +44, csyncm, 14 # id: (1, 69) +45, cload, r1b0, ct1_1_0_0 # id: (1, 70); dep id: (1, 0); ct1_1_0_0 +46, csyncm, 15 # id: (2, 73) +47, cload, r2b0, ct0_0_0_1 # id: (2, 74); dep id: (2, 1); ct0_0_0_1 +48, csyncm, 16 # id: (2, 77) +49, cload, r3b0, ct1_1_0_1 # id: (2, 78); dep id: (2, 1); ct1_1_0_1 +50, csyncm, 17 # id: (3, 81) +51, cload, r4b0, ct1_0_0_0 # id: (3, 82); dep id: (3, 2); ct1_0_0_0 +52, csyncm, 18 # id: (4, 86) +53, cload, r5b0, ct1_0_0_1 # id: (4, 87); dep id: (4, 3); ct1_0_0_1 +54, csyncm, 19 # id: (5, 91) +55, cload, r6b0, ct0_1_0_0 # id: (5, 92); dep id: (5, 4); ct0_1_0_0 +56, csyncm, 20 # id: (6, 95) +57, cload, r7b0, ct0_1_0_1 # id: (6, 96); dep id: (6, 5); ct0_1_0_1 +58, ifetch, 0 # id: (67, 150) +59, cstore, ct2_0_0_0 # id: (3, 101); id: (3, 89); flushing output; variable "ct2_0_0_0": SPAD(19) <- r3b1; ct2_0_0_0 +60, cstore, ct2_0_0_1 # id: (4, 107); id: (4, 99); flushing output; variable "ct2_0_0_1": SPAD(22) <- r7b1; ct2_0_0_1 +61, cstore, ct2_2_0_0 # id: (5, 109); id: (5, 102); flushing output; variable "ct2_2_0_0": SPAD(23) <- r5b1; ct2_2_0_0 +62, cstore, ct2_2_0_1 # id: (6, 111); id: (6, 103); flushing output; variable "ct2_2_0_1": SPAD(24) <- r6b1; ct2_2_0_1 +63, cstore, ct2_1_0_0 # id: (7, 113); id: (7, 104); flushing output; variable "ct2_1_0_0": SPAD(25) <- r0b3; ct2_1_0_0 +64, cstore, ct2_1_0_1 # id: (8, 115); id: (8, 105); flushing output; variable "ct2_1_0_1": SPAD(26) <- r1b3; ct2_1_0_1 +65, csyncm, 32 # id: (8, 163) +66, cexit # id: (66, 164) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..f6625deb --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.mem @@ -0,0 +1,27 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_0_0_0 +dload, poly, 14, ct1_1_0_0 +dload, poly, 15, ct0_0_0_1 +dload, poly, 16, ct1_1_0_1 +dload, poly, 17, ct1_0_0_0 +dload, poly, 18, ct1_0_0_1 +dload, poly, 19, ct0_1_0_0 +dload, poly, 20, ct0_1_0_1 +dstore, ct2_0_0_0, 21 +dstore, ct2_0_0_1, 22 +dstore, ct2_2_0_0, 23 +dstore, ct2_2_0_1, 24 +dstore, ct2_1_0_0, 25 +dstore, ct2_1_0_1, 26 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..90833825 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.minst @@ -0,0 +1,34 @@ +0, mload, ntt_auxiliary_table_0, ntt_auxiliary_table_0 # id: (0, 8) +1, mload, ntt_routing_table_1, ntt_routing_table_1 # id: (0, 9) +2, mload, intt_auxiliary_table_2, intt_auxiliary_table_2 # id: (0, 10) +3, mload, intt_routing_table_3, intt_routing_table_3 # id: (0, 11) +4, mload, twid_4, twid_4 # id: (0, 12); loading twid metadata for residuals [0, 64) +5, mload, twid_5, twid_5 # id: (0, 13); loading twid metadata for residuals [0, 64) +6, mload, twid_6, twid_6 # id: (0, 14); loading twid metadata for residuals [0, 64) +7, mload, twid_7, twid_7 # id: (0, 15); loading twid metadata for residuals [0, 64) +8, mload, twid_8, twid_8 # id: (0, 16); loading twid metadata for residuals [0, 64) +9, mload, twid_9, twid_9 # id: (0, 17); loading twid metadata for residuals [0, 64) +10, mload, twid_10, twid_10 # id: (0, 18); loading twid metadata for residuals [0, 64) +11, mload, twid_11, twid_11 # id: (0, 19); loading twid metadata for residuals [0, 64) +12, mload, ones_12, ones_12 # id: (0, 60); loading ones metadata for residuals [0, 64) +13, mload, ct0_0_0_0, ct0_0_0_0 # id: (1, 64); dep id: (1, 0) +14, mload, ct1_1_0_0, ct1_1_0_0 # id: (1, 68); dep id: (1, 0) +15, mload, ct0_0_0_1, ct0_0_0_1 # id: (2, 72); dep id: (2, 1) +16, mload, ct1_1_0_1, ct1_1_0_1 # id: (2, 76); dep id: (2, 1) +17, mload, ct1_0_0_0, ct1_0_0_0 # id: (3, 80); dep id: (3, 2) +18, mload, ct1_0_0_1, ct1_0_0_1 # id: (4, 85); dep id: (4, 3) +19, mload, ct0_1_0_0, ct0_1_0_0 # id: (5, 90); dep id: (5, 4) +20, mload, ct0_1_0_1, ct0_1_0_1 # id: (6, 94); dep id: (6, 5) +21, msyncc, 59 # id: (3, 151) +22, mstore, ct2_0_0_0, 19 # id: (3, 152); id: (3, 101) - flushing; variable "ct2_0_0_0" <- SPAD(19) +23, msyncc, 60 # id: (4, 153) +24, mstore, ct2_0_0_1, 22 # id: (4, 154); id: (4, 107) - flushing; variable "ct2_0_0_1" <- SPAD(22) +25, msyncc, 61 # id: (5, 155) +26, mstore, ct2_2_0_0, 23 # id: (5, 156); id: (5, 109) - flushing; variable "ct2_2_0_0" <- SPAD(23) +27, msyncc, 62 # id: (6, 157) +28, mstore, ct2_2_0_1, 24 # id: (6, 158); id: (6, 111) - flushing; variable "ct2_2_0_1" <- SPAD(24) +29, msyncc, 63 # id: (7, 159) +30, mstore, ct2_1_0_0, 25 # id: (7, 160); id: (7, 113) - flushing; variable "ct2_1_0_0" <- SPAD(25) +31, msyncc, 64 # id: (8, 161) +32, mstore, ct2_1_0_1, 26 # id: (8, 162); id: (8, 115) - flushing; variable "ct2_1_0_1" <- SPAD(26) +33, msyncc, 67 # id: (66, 165); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..06f07a53 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_mul_16384_l1_m2_pisa.tw.xinst @@ -0,0 +1,64 @@ +F0, 1, move, r0b2, r0b0 # id: (1, 67); variable "ct0_0_0_0" +F0, 1, move, r0b1, r1b0 # id: (1, 71); variable "ct1_1_0_0" +F0, 2, move, r1b2, r2b0 # id: (2, 75); variable "ct0_0_0_1" +F0, 2, move, r1b1, r3b0 # id: (2, 79); variable "ct1_1_0_1" +F0, 3, move, r2b1, r4b0 # id: (3, 83); variable "ct1_0_0_0" +F0, 1, nop, 1 # id: (1, 84); nop for not ready instr (1, 0) +F0, 1, mul, r0b3, r0b2, r0b1, 0 # id: (1, 0); id: (1, 0) +F0, 4, move, r4b1, r5b0 # id: (4, 88); variable "ct1_0_0_1" +F0, 2, mul, r1b3, r1b2, r1b1, 0 # id: (2, 1); id: (2, 1) +F0, 3, mul, r3b1, r0b2, r2b1, 0 # id: (3, 2); id: (3, 2) +F0, 5, move, r2b2, r6b0 # id: (5, 93); variable "ct0_1_0_0" +F0, 6, move, r3b2, r7b0 # id: (6, 97); variable "ct0_1_0_1" +F0, 4, nop, 0 # id: (4, 98); nop for not ready instr (4, 3) +F0, 4, mul, r7b1, r1b2, r4b1, 0 # id: (4, 3); id: (4, 3) +F0, 3, nop, 0 # id: (3, 100); nop for not ready instr (3, 89) +F0, 3, xstore, r3b1 # id: (3, 89); flushing output; variable "ct2_0_0_0": SPAD(19) <- r3b1 +F0, 5, mul, r5b1, r2b2, r0b1, 0 # id: (5, 4); id: (5, 4) +F0, 6, mul, r6b1, r3b2, r1b1, 0 # id: (6, 5); id: (6, 5) +F0, 7, mac, r0b3, r0b3, r2b2, r2b1, 0 # id: (7, 6); id: (7, 6) +F0, 8, mac, r1b3, r1b3, r3b2, r4b1, 0 # id: (8, 7); id: (8, 7) +F0, 4, nop, 0 # id: (4, 106); nop for not ready instr (4, 99) +F0, 4, xstore, r7b1 # id: (4, 99); flushing output; variable "ct2_0_0_1": SPAD(22) <- r7b1 +F0, 5, nop, 4 # id: (5, 108); nop for not ready instr (5, 102) +F0, 5, xstore, r5b1 # id: (5, 102); flushing output; variable "ct2_2_0_0": SPAD(23) <- r5b1 +F0, 6, nop, 4 # id: (6, 110); nop for not ready instr (6, 103) +F0, 6, xstore, r6b1 # id: (6, 103); flushing output; variable "ct2_2_0_1": SPAD(24) <- r6b1 +F0, 7, nop, 4 # id: (7, 112); nop for not ready instr (7, 104) +F0, 7, xstore, r0b3 # id: (7, 104); flushing output; variable "ct2_1_0_0": SPAD(25) <- r0b3 +F0, 8, nop, 4 # id: (8, 114); nop for not ready instr (8, 105) +F0, 8, xstore, r1b3 # id: (8, 105); flushing output; variable "ct2_1_0_1": SPAD(26) <- r1b3 +F0, 0, bexit # id: (0, 116); terminating bundle 0 +F0, 0, nop, 0 # id: (0, 117) +F0, 0, nop, 0 # id: (0, 118) +F0, 0, nop, 0 # id: (0, 119) +F0, 0, nop, 0 # id: (0, 120) +F0, 0, nop, 0 # id: (0, 121) +F0, 0, nop, 0 # id: (0, 122) +F0, 0, nop, 0 # id: (0, 123) +F0, 0, nop, 0 # id: (0, 124) +F0, 0, nop, 0 # id: (0, 125) +F0, 0, nop, 0 # id: (0, 126) +F0, 0, nop, 0 # id: (0, 127) +F0, 0, nop, 0 # id: (0, 128) +F0, 0, nop, 0 # id: (0, 129) +F0, 0, nop, 0 # id: (0, 130) +F0, 0, nop, 0 # id: (0, 131) +F0, 0, nop, 0 # id: (0, 132) +F0, 0, nop, 0 # id: (0, 133) +F0, 0, nop, 0 # id: (0, 134) +F0, 0, nop, 0 # id: (0, 135) +F0, 0, nop, 0 # id: (0, 136) +F0, 0, nop, 0 # id: (0, 137) +F0, 0, nop, 0 # id: (0, 138) +F0, 0, nop, 0 # id: (0, 139) +F0, 0, nop, 0 # id: (0, 140) +F0, 0, nop, 0 # id: (0, 141) +F0, 0, nop, 0 # id: (0, 142) +F0, 0, nop, 0 # id: (0, 143) +F0, 0, nop, 0 # id: (0, 144) +F0, 0, nop, 0 # id: (0, 145) +F0, 0, nop, 0 # id: (0, 146) +F0, 0, nop, 0 # id: (0, 147) +F0, 0, nop, 0 # id: (0, 148) +F0, 0, nop, 0 # id: (0, 149) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst new file mode 100644 index 00000000..4e7fab63 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.cinst @@ -0,0 +1,125 @@ +0, csyncm, 4 # id: (0, 361) +1, bload, 0, twid_4, 0 # id: (0, 362); loading twid metadata for residuals [0, 64) +2, bload, 1, twid_4, 1 # id: (0, 363); loading twid metadata for residuals [0, 64) +3, bload, 2, twid_4, 2 # id: (0, 364); loading twid metadata for residuals [0, 64) +4, bload, 3, twid_4, 3 # id: (0, 365); loading twid metadata for residuals [0, 64) +5, csyncm, 5 # id: (0, 366) +6, bload, 4, twid_5, 0 # id: (0, 367); loading twid metadata for residuals [0, 64) +7, bload, 5, twid_5, 1 # id: (0, 368); loading twid metadata for residuals [0, 64) +8, bload, 6, twid_5, 2 # id: (0, 369); loading twid metadata for residuals [0, 64) +9, bload, 7, twid_5, 3 # id: (0, 370); loading twid metadata for residuals [0, 64) +10, csyncm, 6 # id: (0, 371) +11, bload, 8, twid_6, 0 # id: (0, 372); loading twid metadata for residuals [0, 64) +12, bload, 9, twid_6, 1 # id: (0, 373); loading twid metadata for residuals [0, 64) +13, bload, 10, twid_6, 2 # id: (0, 374); loading twid metadata for residuals [0, 64) +14, bload, 11, twid_6, 3 # id: (0, 375); loading twid metadata for residuals [0, 64) +15, csyncm, 7 # id: (0, 376) +16, bload, 12, twid_7, 0 # id: (0, 377); loading twid metadata for residuals [0, 64) +17, bload, 13, twid_7, 1 # id: (0, 378); loading twid metadata for residuals [0, 64) +18, bload, 14, twid_7, 2 # id: (0, 379); loading twid metadata for residuals [0, 64) +19, bload, 15, twid_7, 3 # id: (0, 380); loading twid metadata for residuals [0, 64) +20, csyncm, 8 # id: (0, 381) +21, bload, 16, twid_8, 0 # id: (0, 382); loading twid metadata for residuals [0, 64) +22, bload, 17, twid_8, 1 # id: (0, 383); loading twid metadata for residuals [0, 64) +23, bload, 18, twid_8, 2 # id: (0, 384); loading twid metadata for residuals [0, 64) +24, bload, 19, twid_8, 3 # id: (0, 385); loading twid metadata for residuals [0, 64) +25, csyncm, 9 # id: (0, 386) +26, bload, 20, twid_9, 0 # id: (0, 387); loading twid metadata for residuals [0, 64) +27, bload, 21, twid_9, 1 # id: (0, 388); loading twid metadata for residuals [0, 64) +28, bload, 22, twid_9, 2 # id: (0, 389); loading twid metadata for residuals [0, 64) +29, bload, 23, twid_9, 3 # id: (0, 390); loading twid metadata for residuals [0, 64) +30, csyncm, 10 # id: (0, 391) +31, bload, 24, twid_10, 0 # id: (0, 392); loading twid metadata for residuals [0, 64) +32, bload, 25, twid_10, 1 # id: (0, 393); loading twid metadata for residuals [0, 64) +33, bload, 26, twid_10, 2 # id: (0, 394); loading twid metadata for residuals [0, 64) +34, bload, 27, twid_10, 3 # id: (0, 395); loading twid metadata for residuals [0, 64) +35, csyncm, 11 # id: (0, 396) +36, bload, 28, twid_11, 0 # id: (0, 397); loading twid metadata for residuals [0, 64) +37, bload, 29, twid_11, 1 # id: (0, 398); loading twid metadata for residuals [0, 64) +38, bload, 30, twid_11, 2 # id: (0, 399); loading twid metadata for residuals [0, 64) +39, bload, 31, twid_11, 3 # id: (0, 400); loading twid metadata for residuals [0, 64) +40, csyncm, 12 # id: (0, 402) +41, bones, ones_12, 0 # id: (0, 403); loading ones metadata for residuals [0, 64) +42, csyncm, 13 # id: (1, 406) +43, cload, r0b0, ct0_2_0_0 # id: (1, 407); dep id: (1, 0); ct0_2_0_0 +44, csyncm, 14 # id: (1, 410) +45, cload, r1b0, ct0_2_0_1 # id: (1, 411); dep id: (1, 0); ct0_2_0_1 +46, csyncm, 2 # id: (0, 439) +47, nload, 0, intt_auxiliary_table_2 # loading routing table for `intt` +48, csyncm, 3 # id: (0, 441) +49, nload, 1, intt_routing_table_3 # loading routing table for `intt` +50, ifetch, 0 # id: (408, 438) +51, csyncm, 15 # id: (42, 446) +52, cload, r2b0, ipsi_0_0 # id: (42, 447); dep id: (42, 41); ipsi_0_0 +53, csyncm, 16 # id: (43, 450) +54, cload, r3b0, ipsi_0_1 # id: (43, 451); dep id: (43, 42); ipsi_0_1 +55, csyncm, 17 # id: (50, 458) +56, cload, r4b0, psi_0_0 # id: (50, 459); dep id: (50, 49); psi_0_0 +57, csyncm, 18 # id: (51, 462) +58, cload, r5b0, psi_0_1 # id: (51, 463); dep id: (51, 50); psi_0_1 +59, cnop, 364 # id: (1, 504) +60, ifetch, 1 # id: (37, 503) +61, cnop, 82 # id: (2, 532) +62, csyncm, 0 # id: (0, 533) +63, nload, 0, ntt_auxiliary_table_0 # loading routing table for `ntt` +64, csyncm, 1 # id: (0, 535) +65, nload, 1, ntt_routing_table_1 # loading routing table for `ntt` +66, ifetch, 2 # id: (52, 531) +67, csyncm, 19 # id: (93, 538) +68, cload, r0b0, rlk_0_0_0_0 # id: (93, 539); dep id: (93, 92); rlk_0_0_0_0 +69, csyncm, 20 # id: (95, 542) +70, cload, r1b0, rlk_1_0_0_0 # id: (95, 543); dep id: (95, 94); rlk_1_0_0_0 +71, csyncm, 21 # id: (94, 547) +72, cload, r2b0, rlk_0_0_0_1 # id: (94, 548); dep id: (94, 93); rlk_0_0_0_1 +73, csyncm, 22 # id: (96, 551) +74, cload, r3b0, rlk_1_0_0_1 # id: (96, 552); dep id: (96, 95); rlk_1_0_0_1 +75, csyncm, 23 # id: (99, 557) +76, cload, r4b0, psi_1_0 # id: (99, 558); dep id: (99, 98); psi_1_0 +77, csyncm, 24 # id: (100, 562) +78, cload, r5b0, psi_1_1 # id: (100, 563); dep id: (100, 99); psi_1_1 +79, cnop, 368 # id: (3, 585) +80, ifetch, 3 # id: (91, 584) +81, csyncm, 25 # id: (142, 597) +82, cload, r6b0, rlk_0_0_1_0 # id: (142, 598); dep id: (142, 141); rlk_0_0_1_0 +83, csyncm, 26 # id: (144, 601) +84, cload, r7b0, rlk_1_0_1_0 # id: (144, 602); dep id: (144, 143); rlk_1_0_1_0 +85, csyncm, 27 # id: (143, 606) +86, cload, r8b0, rlk_0_0_1_1 # id: (143, 607); dep id: (143, 142); rlk_0_0_1_1 +87, csyncm, 28 # id: (145, 610) +88, cload, r9b0, rlk_1_0_1_1 # id: (145, 611); dep id: (145, 144); rlk_1_0_1_1 +89, cnop, 291 # id: (4, 644) +90, ifetch, 4 # id: (125, 643) +91, cnop, 193 # id: (5, 672) +92, nload, 0, intt_auxiliary_table_2 # loading routing table for `intt` +93, nload, 1, intt_routing_table_3 # loading routing table for `intt` +94, ifetch, 5 # id: (145, 671) +95, csyncm, 29 # id: (188, 678) +96, cload, r0b0, ipsi_1_1 # id: (188, 679); dep id: (188, 187); ipsi_1_1 +97, csyncm, 30 # id: (187, 682) +98, cload, r1b0, ipsi_1_0 # id: (187, 683); dep id: (187, 186); ipsi_1_0 +99, cnop, 367 # id: (6, 705) +100, ifetch, 6 # id: (182, 704) +101, cnop, 265 # id: (7, 746) +102, ifetch, 7 # id: (271, 745) +103, cnop, 205 # id: (8, 774) +104, nload, 0, ntt_auxiliary_table_0 # loading routing table for `ntt` +105, nload, 1, ntt_routing_table_1 # loading routing table for `ntt` +106, ifetch, 8 # id: (199, 773) +107, csyncm, 31 # id: (246, 781) +108, cload, r0b0, ct0_0_0_0 # id: (246, 782); dep id: (246, 245); ct0_0_0_0 +109, csyncm, 32 # id: (247, 785) +110, cload, r1b0, ct0_0_0_1 # id: (247, 786); dep id: (247, 246); ct0_0_0_1 +111, cnop, 388 # id: (9, 813) +112, ifetch, 9 # id: (238, 812) +113, cstore, ct1_0_0_0 # id: (246, 792); id: (246, 789); flushing output; variable "ct1_0_0_0": SPAD(33) <- r17b1; ct1_0_0_0 +114, cstore, ct1_0_0_1 # id: (247, 795); id: (247, 790); flushing output; variable "ct1_0_0_1": SPAD(34) <- r19b1; ct1_0_0_1 +115, csyncm, 37 # id: (348, 833) +116, cload, r2b0, ct0_1_0_0 # id: (348, 834); dep id: (348, 347); ct0_1_0_0 +117, csyncm, 38 # id: (349, 837) +118, cload, r3b0, ct0_1_0_1 # id: (349, 838); dep id: (349, 348); ct0_1_0_1 +119, cnop, 230 # id: (10, 866) +120, ifetch, 10 # id: (324, 865) +121, cstore, ct1_1_0_0 # id: (348, 844); id: (348, 841); flushing output; variable "ct1_1_0_0": SPAD(35) <- r17b1; ct1_1_0_0 +122, cstore, ct1_1_0_1 # id: (349, 846); id: (349, 842); flushing output; variable "ct1_1_0_1": SPAD(36) <- r20b1; ct1_1_0_1 +123, csyncm, 42 # id: (349, 871) +124, cexit # id: (124, 872) diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.mem b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.mem new file mode 100644 index 00000000..fb7b3912 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.mem @@ -0,0 +1,39 @@ +dload, ntt_auxiliary_table, 0 +dload, ntt_routing_table, 1 +dload, intt_auxiliary_table, 2 +dload, intt_routing_table, 3 +dload, twid, 4 +dload, twid, 5 +dload, twid, 6 +dload, twid, 7 +dload, twid, 8 +dload, twid, 9 +dload, twid, 10 +dload, twid, 11 +dload, ones, 12 +dload, poly, 13, ct0_2_0_0 +dload, poly, 14, ct0_2_0_1 +dload, poly, 15, ipsi_0_0 +dload, poly, 16, ipsi_0_1 +dload, poly, 17, psi_0_0 +dload, poly, 18, psi_0_1 +dload, poly, 19, rlk_0_0_0_0 +dload, poly, 20, rlk_0_0_0_1 +dload, poly, 21, rlk_1_0_0_0 +dload, poly, 22, rlk_1_0_0_1 +dload, poly, 23, psi_1_0 +dload, poly, 24, psi_1_1 +dload, poly, 25, rlk_0_0_1_0 +dload, poly, 26, rlk_0_0_1_1 +dload, poly, 27, rlk_1_0_1_0 +dload, poly, 28, rlk_1_0_1_1 +dload, poly, 29, ipsi_1_0 +dload, poly, 30, ipsi_1_1 +dload, poly, 31, ct0_0_0_0 +dload, poly, 32, ct0_0_0_1 +dload, poly, 33, ct0_1_0_0 +dload, poly, 34, ct0_1_0_1 +dstore, ct1_0_0_0, 35 +dstore, ct1_0_0_1, 36 +dstore, ct1_1_0_0, 37 +dstore, ct1_1_0_1, 38 diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.minst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.minst new file mode 100644 index 00000000..7863c7a6 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.minst @@ -0,0 +1,44 @@ +0, mload, ntt_auxiliary_table_0, ntt_auxiliary_table_0 # id: (0, 349) +1, mload, ntt_routing_table_1, ntt_routing_table_1 # id: (0, 350) +2, mload, intt_auxiliary_table_2, intt_auxiliary_table_2 # id: (0, 351) +3, mload, intt_routing_table_3, intt_routing_table_3 # id: (0, 352) +4, mload, twid_4, twid_4 # id: (0, 353); loading twid metadata for residuals [0, 64) +5, mload, twid_5, twid_5 # id: (0, 354); loading twid metadata for residuals [0, 64) +6, mload, twid_6, twid_6 # id: (0, 355); loading twid metadata for residuals [0, 64) +7, mload, twid_7, twid_7 # id: (0, 356); loading twid metadata for residuals [0, 64) +8, mload, twid_8, twid_8 # id: (0, 357); loading twid metadata for residuals [0, 64) +9, mload, twid_9, twid_9 # id: (0, 358); loading twid metadata for residuals [0, 64) +10, mload, twid_10, twid_10 # id: (0, 359); loading twid metadata for residuals [0, 64) +11, mload, twid_11, twid_11 # id: (0, 360); loading twid metadata for residuals [0, 64) +12, mload, ones_12, ones_12 # id: (0, 401); loading ones metadata for residuals [0, 64) +13, mload, ct0_2_0_0, ct0_2_0_0 # id: (1, 405); dep id: (1, 0) +14, mload, ct0_2_0_1, ct0_2_0_1 # id: (1, 409); dep id: (1, 0) +15, mload, ipsi_0_0, ipsi_0_0 # id: (42, 445); dep id: (42, 41) +16, mload, ipsi_0_1, ipsi_0_1 # id: (43, 449); dep id: (43, 42) +17, mload, psi_0_0, psi_0_0 # id: (50, 457); dep id: (50, 49) +18, mload, psi_0_1, psi_0_1 # id: (51, 461); dep id: (51, 50) +19, mload, rlk_0_0_0_0, rlk_0_0_0_0 # id: (93, 537); dep id: (93, 92) +20, mload, rlk_1_0_0_0, rlk_1_0_0_0 # id: (95, 541); dep id: (95, 94) +21, mload, rlk_0_0_0_1, rlk_0_0_0_1 # id: (94, 546); dep id: (94, 93) +22, mload, rlk_1_0_0_1, rlk_1_0_0_1 # id: (96, 550); dep id: (96, 95) +23, mload, psi_1_0, psi_1_0 # id: (99, 556); dep id: (99, 98) +24, mload, psi_1_1, psi_1_1 # id: (100, 561); dep id: (100, 99) +25, mload, rlk_0_0_1_0, rlk_0_0_1_0 # id: (142, 596); dep id: (142, 141) +26, mload, rlk_1_0_1_0, rlk_1_0_1_0 # id: (144, 600); dep id: (144, 143) +27, mload, rlk_0_0_1_1, rlk_0_0_1_1 # id: (143, 605); dep id: (143, 142) +28, mload, rlk_1_0_1_1, rlk_1_0_1_1 # id: (145, 609); dep id: (145, 144) +29, mload, ipsi_1_1, ipsi_1_1 # id: (188, 677); dep id: (188, 187) +30, mload, ipsi_1_0, ipsi_1_0 # id: (187, 681); dep id: (187, 186) +31, mload, ct0_0_0_0, ct0_0_0_0 # id: (246, 780); dep id: (246, 245) +32, mload, ct0_0_0_1, ct0_0_0_1 # id: (247, 784); dep id: (247, 246) +33, msyncc, 113 # id: (246, 814) +34, mstore, ct1_0_0_0, 33 # id: (246, 815); id: (246, 792) - flushing; variable "ct1_0_0_0" <- SPAD(33) +35, msyncc, 114 # id: (247, 816) +36, mstore, ct1_0_0_1, 34 # id: (247, 817); id: (247, 795) - flushing; variable "ct1_0_0_1" <- SPAD(34) +37, mload, ct0_1_0_0, ct0_1_0_0 # id: (348, 832); dep id: (348, 347) +38, mload, ct0_1_0_1, ct0_1_0_1 # id: (349, 836); dep id: (349, 348) +39, msyncc, 121 # id: (348, 867) +40, mstore, ct1_1_0_0, 35 # id: (348, 868); id: (348, 844) - flushing; variable "ct1_1_0_0" <- SPAD(35) +41, msyncc, 122 # id: (349, 869) +42, mstore, ct1_1_0_1, 36 # id: (349, 870); id: (349, 846) - flushing; variable "ct1_1_0_1" <- SPAD(36) +43, msyncc, 125 # id: (124, 873); terminating MInstQ diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst new file mode 100644 index 00000000..3c500692 --- /dev/null +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/linking_fixtures/bgv_multi_mul_relin_16384_l1_m2/no_hbm/bgv_relin_16384_l1_m2_pisa.tw.xinst @@ -0,0 +1,704 @@ +F0, 1, move, r0b2, r0b0 # id: (1, 408); variable "ct0_2_0_0" +F0, 1, move, r0b3, r1b0 # id: (1, 412); variable "ct0_2_0_1" +F0, 1, nop, 4 # id: (1, 413); nop for not ready instr (1, 0) +F0, 1, rshuffle, r0b2, r0b3, r0b2, r0b3, 0, intt # id: (1, 0); id: (1, 1); 0 0 1 12 w_0_0_0 +F0, 2, nop, 21 # id: (2, 414); nop for not ready instr (2, 1) +F0, 2, intt, r1b2, r1b3, r0b2, r0b3, r0b1, 0, 0 # id: (2, 1); id: (1, 2); 0 0 1 12 w_0_0_0 +F0, 3, twintt, r0b1, r0b1, 28, 0, 0, 14, 0 # id: (3, 2); id: (1, 0); 0 0 1 12 w_0_0_0 +F0, 4, nop, 3 # id: (4, 415); nop for not ready instr (4, 3) +F0, 4, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (4, 3); id: (2, 4); 0 0 1 11 w_0_1_0 +F0, 5, nop, 21 # id: (5, 416); nop for not ready instr (5, 4) +F0, 5, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 1, 0 # id: (5, 4); id: (2, 5); 0 0 1 11 w_0_1_0 +F0, 6, twintt, r0b1, r0b1, 27, 1, 0, 14, 0 # id: (6, 5); id: (2, 3); 0 0 1 11 w_0_1_0 +F0, 7, nop, 3 # id: (7, 417); nop for not ready instr (7, 6) +F0, 7, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (7, 6); id: (3, 7); 0 0 1 10 w_0_2_0 +F0, 8, nop, 21 # id: (8, 418); nop for not ready instr (8, 7) +F0, 8, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 2, 0 # id: (8, 7); id: (3, 8); 0 0 1 10 w_0_2_0 +F0, 9, twintt, r0b1, r0b1, 26, 2, 0, 14, 0 # id: (9, 8); id: (3, 6); 0 0 1 10 w_0_2_0 +F0, 10, nop, 3 # id: (10, 419); nop for not ready instr (10, 9) +F0, 10, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (10, 9); id: (4, 10); 0 0 1 9 w_0_3_0 +F0, 11, nop, 21 # id: (11, 420); nop for not ready instr (11, 10) +F0, 11, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 3, 0 # id: (11, 10); id: (4, 11); 0 0 1 9 w_0_3_0 +F0, 12, twintt, r0b1, r0b1, 25, 3, 0, 14, 0 # id: (12, 11); id: (4, 9); 0 0 1 9 w_0_3_0 +F0, 13, nop, 3 # id: (13, 421); nop for not ready instr (13, 12) +F0, 13, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (13, 12); id: (5, 13); 0 0 1 8 w_0_4_0 +F0, 14, nop, 21 # id: (14, 422); nop for not ready instr (14, 13) +F0, 14, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 4, 0 # id: (14, 13); id: (5, 14); 0 0 1 8 w_0_4_0 +F0, 15, twintt, r0b1, r0b1, 24, 4, 0, 14, 0 # id: (15, 14); id: (5, 12); 0 0 1 8 w_0_4_0 +F0, 16, nop, 3 # id: (16, 423); nop for not ready instr (16, 15) +F0, 16, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (16, 15); id: (6, 16); 0 0 1 7 w_0_5_0 +F0, 17, nop, 21 # id: (17, 424); nop for not ready instr (17, 16) +F0, 17, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 5, 0 # id: (17, 16); id: (6, 17); 0 0 1 7 w_0_5_0 +F0, 18, twintt, r0b1, r0b1, 23, 5, 0, 14, 0 # id: (18, 17); id: (6, 15); 0 0 1 7 w_0_5_0 +F0, 19, nop, 3 # id: (19, 425); nop for not ready instr (19, 18) +F0, 19, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (19, 18); id: (7, 19); 0 0 1 6 w_0_6_0 +F0, 20, nop, 21 # id: (20, 426); nop for not ready instr (20, 19) +F0, 20, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 6, 0 # id: (20, 19); id: (7, 20); 0 0 1 6 w_0_6_0 +F0, 21, twintt, r0b1, r0b1, 22, 6, 0, 14, 0 # id: (21, 20); id: (7, 18); 0 0 1 6 w_0_6_0 +F0, 22, nop, 3 # id: (22, 427); nop for not ready instr (22, 21) +F0, 22, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (22, 21); id: (8, 22); 0 0 1 5 w_0_7_0 +F0, 23, nop, 21 # id: (23, 428); nop for not ready instr (23, 22) +F0, 23, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 7, 0 # id: (23, 22); id: (8, 23); 0 0 1 5 w_0_7_0 +F0, 24, twintt, r0b1, r0b1, 21, 7, 0, 14, 0 # id: (24, 23); id: (8, 21); 0 0 1 5 w_0_7_0 +F0, 25, nop, 3 # id: (25, 429); nop for not ready instr (25, 24) +F0, 25, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (25, 24); id: (9, 25); 0 0 1 4 w_0_8_0 +F0, 26, nop, 21 # id: (26, 430); nop for not ready instr (26, 25) +F0, 26, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 8, 0 # id: (26, 25); id: (9, 26); 0 0 1 4 w_0_8_0 +F0, 27, twintt, r0b1, r0b1, 20, 8, 0, 14, 0 # id: (27, 26); id: (9, 24); 0 0 1 4 w_0_8_0 +F0, 28, nop, 3 # id: (28, 431); nop for not ready instr (28, 27) +F0, 28, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (28, 27); id: (10, 28); 0 0 1 3 w_0_9_0 +F0, 29, nop, 21 # id: (29, 432); nop for not ready instr (29, 28) +F0, 29, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 9, 0 # id: (29, 28); id: (10, 29); 0 0 1 3 w_0_9_0 +F0, 30, twintt, r0b1, r0b1, 19, 9, 0, 14, 0 # id: (30, 29); id: (10, 27); 0 0 1 3 w_0_9_0 +F0, 31, nop, 3 # id: (31, 433); nop for not ready instr (31, 30) +F0, 31, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (31, 30); id: (11, 31); 0 0 1 2 w_0_10_0 +F0, 32, nop, 21 # id: (32, 434); nop for not ready instr (32, 31) +F0, 32, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 10, 0 # id: (32, 31); id: (11, 32); 0 0 1 2 w_0_10_0 +F0, 33, twintt, r0b1, r0b1, 18, 10, 0, 14, 0 # id: (33, 32); id: (11, 30); 0 0 1 2 w_0_10_0 +F0, 34, nop, 3 # id: (34, 435); nop for not ready instr (34, 33) +F0, 34, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (34, 33); id: (12, 34); 0 0 1 1 w_0_11_0 +F0, 35, nop, 21 # id: (35, 436); nop for not ready instr (35, 34) +F0, 35, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 11, 0 # id: (35, 34); id: (12, 35); 0 0 1 1 w_0_11_0 +F0, 36, twintt, r0b1, r0b1, 17, 11, 0, 14, 0 # id: (36, 35); id: (12, 33); 0 0 1 1 w_0_11_0 +F0, 37, nop, 3 # id: (37, 437); nop for not ready instr (37, 36) +F0, 37, rshuffle, r2b2, r2b3, r2b2, r2b3, 0, intt # id: (37, 36); id: (13, 37); 0 0 1 0 w_0_12_0 +F1, 38, intt, r1b2, r1b3, r2b2, r2b3, r0b1, 12, 0 # id: (38, 37); id: (13, 38); 0 0 1 0 w_0_12_0 +F1, 39, twintt, r0b1, r0b1, 16, 12, 0, 14, 0 # id: (39, 38); id: (13, 36); 0 0 1 0 w_0_12_0 +F1, 40, nop, 3 # id: (40, 443); nop for not ready instr (40, 39) +F1, 40, rshuffle, r1b2, r1b3, r1b2, r1b3, 0, intt # id: (40, 39); id: (14, 39); 0 0 1 -1 w_0_13_0 +F1, 41, nop, 21 # id: (41, 444); nop for not ready instr (41, 40) +F1, 41, intt, r2b2, r2b3, r1b2, r1b3, r0b1, 13, 0 # id: (41, 40); id: (14, 40); 0 0 1 -1 w_0_13_0 +F1, 42, move, r1b1, r2b0 # id: (42, 448); variable "ipsi_0_0" +F1, 43, move, r2b1, r3b0 # id: (43, 452); variable "ipsi_0_1" +F1, 42, nop, 3 # id: (42, 453); nop for not ready instr (42, 41) +F1, 42, mul, r2b2, r2b2, r1b1, 0 # id: (42, 41); id: (15, 41) +F1, 43, mul, r2b3, r2b3, r2b1, 0 # id: (43, 42); id: (16, 42) +F1, 44, nop, 3 # id: (44, 454); nop for not ready instr (44, 43) +F1, 44, muli, r2b2, r2b2, iN, 0 # id: (44, 43); id: (17, 43) +F1, 45, muli, r2b3, r2b3, iN, 0 # id: (45, 44); id: (18, 44) +F1, 46, nop, 3 # id: (46, 455); nop for not ready instr (46, 45) +F1, 46, muli, r2b2, r2b2, one, 0 # id: (46, 45); id: (19, 45) +F1, 47, muli, r2b3, r2b3, one, 0 # id: (47, 46); id: (20, 46) +F1, 48, nop, 3 # id: (48, 456); nop for not ready instr (48, 47) +F1, 48, muli, r3b1, r2b2, R2_0, 0 # id: (48, 47); id: (21, 47) +F1, 49, muli, r3b2, r2b3, R2_0, 0 # id: (49, 48); id: (22, 48) +F1, 50, move, r4b2, r4b0 # id: (50, 460); variable "psi_0_0" +F1, 51, move, r4b1, r5b0 # id: (51, 464); variable "psi_0_1" +F1, 50, nop, 3 # id: (50, 465); nop for not ready instr (50, 49) +F1, 50, mul, r3b1, r3b1, r4b2, 0 # id: (50, 49); id: (23, 49) +F1, 51, mul, r3b2, r3b2, r4b1, 0 # id: (51, 50); id: (24, 50) +F1, 52, nop, 4 # id: (52, 466); nop for not ready instr (52, 51) +F1, 52, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 0, 0 # id: (52, 51); id: (25, 53); 0 0 0 12 w_0_0_0 +F1, 54, twntt, r3b3, r3b3, 12, 0, 0, 14, 0 # id: (54, 53); id: (25, 51); 0 0 0 12 w_0_0_0 +F1, 1, bexit # id: (1, 467); terminating bundle 1 +F1, 1, nop, 0 # id: (1, 468) +F1, 1, nop, 0 # id: (1, 469) +F1, 1, nop, 0 # id: (1, 470) +F1, 1, nop, 0 # id: (1, 471) +F1, 1, nop, 0 # id: (1, 472) +F1, 1, nop, 0 # id: (1, 473) +F1, 1, nop, 0 # id: (1, 474) +F1, 1, nop, 0 # id: (1, 475) +F1, 1, nop, 0 # id: (1, 476) +F1, 1, nop, 0 # id: (1, 477) +F1, 1, nop, 0 # id: (1, 478) +F1, 1, nop, 0 # id: (1, 479) +F1, 1, nop, 0 # id: (1, 480) +F1, 1, nop, 0 # id: (1, 481) +F1, 1, nop, 0 # id: (1, 482) +F1, 1, nop, 0 # id: (1, 483) +F1, 1, nop, 0 # id: (1, 484) +F1, 1, nop, 0 # id: (1, 485) +F1, 1, nop, 0 # id: (1, 486) +F1, 1, nop, 0 # id: (1, 487) +F1, 1, nop, 0 # id: (1, 488) +F1, 1, nop, 0 # id: (1, 489) +F1, 1, nop, 0 # id: (1, 490) +F1, 1, nop, 0 # id: (1, 491) +F1, 1, nop, 0 # id: (1, 492) +F1, 1, nop, 0 # id: (1, 493) +F1, 1, nop, 0 # id: (1, 494) +F1, 1, nop, 0 # id: (1, 495) +F1, 1, nop, 0 # id: (1, 496) +F1, 1, nop, 0 # id: (1, 497) +F1, 1, nop, 0 # id: (1, 498) +F1, 1, nop, 0 # id: (1, 499) +F1, 1, nop, 0 # id: (1, 500) +F1, 1, nop, 0 # id: (1, 501) +F1, 1, nop, 0 # id: (1, 502) +F2, 53, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (53, 52); id: (25, 52); 0 0 0 12 w_0_0_0 +F2, 55, nop, 21 # id: (55, 505); nop for not ready instr (55, 54) +F2, 55, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 1, 0 # id: (55, 54); id: (26, 56); 0 0 0 11 w_0_1_0 +F2, 57, twntt, r3b3, r3b3, 11, 1, 0, 14, 0 # id: (57, 56); id: (26, 54); 0 0 0 11 w_0_1_0 +F2, 56, nop, 3 # id: (56, 506); nop for not ready instr (56, 55) +F2, 56, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (56, 55); id: (26, 55); 0 0 0 11 w_0_1_0 +F2, 58, nop, 21 # id: (58, 507); nop for not ready instr (58, 57) +F2, 58, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 2, 0 # id: (58, 57); id: (27, 59); 0 0 0 10 w_0_2_0 +F2, 60, twntt, r3b3, r3b3, 10, 2, 0, 14, 0 # id: (60, 59); id: (27, 57); 0 0 0 10 w_0_2_0 +F2, 59, nop, 3 # id: (59, 508); nop for not ready instr (59, 58) +F2, 59, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (59, 58); id: (27, 58); 0 0 0 10 w_0_2_0 +F2, 61, nop, 21 # id: (61, 509); nop for not ready instr (61, 60) +F2, 61, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 3, 0 # id: (61, 60); id: (28, 62); 0 0 0 9 w_0_3_0 +F2, 63, twntt, r3b3, r3b3, 9, 3, 0, 14, 0 # id: (63, 62); id: (28, 60); 0 0 0 9 w_0_3_0 +F2, 62, nop, 3 # id: (62, 510); nop for not ready instr (62, 61) +F2, 62, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (62, 61); id: (28, 61); 0 0 0 9 w_0_3_0 +F2, 64, nop, 21 # id: (64, 511); nop for not ready instr (64, 63) +F2, 64, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 4, 0 # id: (64, 63); id: (29, 65); 0 0 0 8 w_0_4_0 +F2, 66, twntt, r3b3, r3b3, 8, 4, 0, 14, 0 # id: (66, 65); id: (29, 63); 0 0 0 8 w_0_4_0 +F2, 65, nop, 3 # id: (65, 512); nop for not ready instr (65, 64) +F2, 65, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (65, 64); id: (29, 64); 0 0 0 8 w_0_4_0 +F2, 67, nop, 21 # id: (67, 513); nop for not ready instr (67, 66) +F2, 67, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 5, 0 # id: (67, 66); id: (30, 68); 0 0 0 7 w_0_5_0 +F2, 69, twntt, r3b3, r3b3, 7, 5, 0, 14, 0 # id: (69, 68); id: (30, 66); 0 0 0 7 w_0_5_0 +F2, 68, nop, 3 # id: (68, 514); nop for not ready instr (68, 67) +F2, 68, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (68, 67); id: (30, 67); 0 0 0 7 w_0_5_0 +F2, 70, nop, 21 # id: (70, 515); nop for not ready instr (70, 69) +F2, 70, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 6, 0 # id: (70, 69); id: (31, 71); 0 0 0 6 w_0_6_0 +F2, 72, twntt, r3b3, r3b3, 6, 6, 0, 14, 0 # id: (72, 71); id: (31, 69); 0 0 0 6 w_0_6_0 +F2, 71, nop, 3 # id: (71, 516); nop for not ready instr (71, 70) +F2, 71, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (71, 70); id: (31, 70); 0 0 0 6 w_0_6_0 +F2, 73, nop, 21 # id: (73, 517); nop for not ready instr (73, 72) +F2, 73, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 7, 0 # id: (73, 72); id: (32, 74); 0 0 0 5 w_0_7_0 +F2, 75, twntt, r3b3, r3b3, 5, 7, 0, 14, 0 # id: (75, 74); id: (32, 72); 0 0 0 5 w_0_7_0 +F2, 74, nop, 3 # id: (74, 518); nop for not ready instr (74, 73) +F2, 74, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (74, 73); id: (32, 73); 0 0 0 5 w_0_7_0 +F2, 76, nop, 21 # id: (76, 519); nop for not ready instr (76, 75) +F2, 76, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 8, 0 # id: (76, 75); id: (33, 77); 0 0 0 4 w_0_8_0 +F2, 78, twntt, r3b3, r3b3, 4, 8, 0, 14, 0 # id: (78, 77); id: (33, 75); 0 0 0 4 w_0_8_0 +F2, 77, nop, 3 # id: (77, 520); nop for not ready instr (77, 76) +F2, 77, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (77, 76); id: (33, 76); 0 0 0 4 w_0_8_0 +F2, 79, nop, 21 # id: (79, 521); nop for not ready instr (79, 78) +F2, 79, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 9, 0 # id: (79, 78); id: (34, 80); 0 0 0 3 w_0_9_0 +F2, 81, twntt, r3b3, r3b3, 3, 9, 0, 14, 0 # id: (81, 80); id: (34, 78); 0 0 0 3 w_0_9_0 +F2, 80, nop, 3 # id: (80, 522); nop for not ready instr (80, 79) +F2, 80, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (80, 79); id: (34, 79); 0 0 0 3 w_0_9_0 +F2, 82, nop, 21 # id: (82, 523); nop for not ready instr (82, 81) +F2, 82, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 10, 0 # id: (82, 81); id: (35, 83); 0 0 0 2 w_0_10_0 +F2, 84, twntt, r3b3, r3b3, 2, 10, 0, 14, 0 # id: (84, 83); id: (35, 81); 0 0 0 2 w_0_10_0 +F2, 83, nop, 3 # id: (83, 524); nop for not ready instr (83, 82) +F2, 83, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (83, 82); id: (35, 82); 0 0 0 2 w_0_10_0 +F2, 85, nop, 21 # id: (85, 525); nop for not ready instr (85, 84) +F2, 85, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 11, 0 # id: (85, 84); id: (36, 86); 0 0 0 1 w_0_11_0 +F2, 87, twntt, r3b3, r3b3, 1, 11, 0, 14, 0 # id: (87, 86); id: (36, 84); 0 0 0 1 w_0_11_0 +F2, 86, nop, 3 # id: (86, 526); nop for not ready instr (86, 85) +F2, 86, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (86, 85); id: (36, 85); 0 0 0 1 w_0_11_0 +F2, 88, nop, 21 # id: (88, 527); nop for not ready instr (88, 87) +F2, 88, ntt, r5b1, r5b2, r3b1, r3b2, r3b3, 12, 0 # id: (88, 87); id: (37, 89); 0 0 0 0 w_0_12_0 +F2, 90, twntt, r3b3, r3b3, 0, 12, 0, 14, 0 # id: (90, 89); id: (37, 87); 0 0 0 0 w_0_12_0 +F2, 89, nop, 3 # id: (89, 528); nop for not ready instr (89, 88) +F2, 89, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (89, 88); id: (37, 88); 0 0 0 0 w_0_12_0 +F2, 91, nop, 21 # id: (91, 529); nop for not ready instr (91, 90) +F2, 91, ntt, r3b1, r3b2, r5b1, r5b2, r3b3, 13, 0 # id: (91, 90); id: (38, 91); 0 0 0 -1 w_0_13_0 +F2, 2, bexit # id: (2, 530); terminating bundle 2 +F3, 92, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (92, 91); id: (38, 90); 0 0 0 -1 w_0_13_0 +F3, 93, move, r6b2, r0b0 # id: (93, 540); variable "rlk_0_0_0_0" +F3, 95, move, r8b2, r1b0 # id: (95, 544); variable "rlk_1_0_0_0" +F3, 93, nop, 19 # id: (93, 545); nop for not ready instr (93, 92) +F3, 93, mul, r7b2, r3b1, r6b2, 0 # id: (93, 92); id: (39, 92) +F3, 94, move, r6b1, r2b0 # id: (94, 549); variable "rlk_0_0_0_1" +F3, 95, mul, r9b2, r3b1, r8b2, 0 # id: (95, 94); id: (41, 94) +F3, 96, move, r8b1, r3b0 # id: (96, 553); variable "rlk_1_0_0_1" +F3, 97, muli, r3b1, r2b2, R2_1, 1 # id: (97, 96); id: (43, 96) +F3, 94, nop, 1 # id: (94, 554); nop for not ready instr (94, 93) +F3, 94, mul, r7b1, r3b2, r6b1, 0 # id: (94, 93); id: (40, 93) +F3, 96, nop, 0 # id: (96, 555); nop for not ready instr (96, 95) +F3, 96, mul, r9b1, r3b2, r8b1, 0 # id: (96, 95); id: (42, 95) +F3, 99, move, r10b2, r4b0 # id: (99, 559); variable "psi_1_0" +F3, 98, muli, r3b2, r2b3, R2_1, 1 # id: (98, 97); id: (44, 97) +F3, 99, nop, 3 # id: (99, 560); nop for not ready instr (99, 98) +F3, 99, mul, r3b1, r3b1, r10b2, 1 # id: (99, 98); id: (45, 98) +F3, 100, move, r10b1, r5b0 # id: (100, 564); variable "psi_1_1" +F3, 100, nop, 4 # id: (100, 565); nop for not ready instr (100, 99) +F3, 100, mul, r3b2, r3b2, r10b1, 1 # id: (100, 99); id: (46, 99) +F3, 101, nop, 4 # id: (101, 566); nop for not ready instr (101, 100) +F3, 101, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 0, 1 # id: (101, 100); id: (47, 102); 0 1 0 12 w_1_0_0 +F3, 103, twntt, r4b3, r4b3, 44, 0, 0, 14, 1 # id: (103, 102); id: (47, 100); 0 1 0 12 w_1_0_0 +F3, 102, nop, 3 # id: (102, 567); nop for not ready instr (102, 101) +F3, 102, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (102, 101); id: (47, 101); 0 1 0 12 w_1_0_0 +F3, 104, nop, 21 # id: (104, 568); nop for not ready instr (104, 103) +F3, 104, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 1, 1 # id: (104, 103); id: (48, 105); 0 1 0 11 w_1_1_0 +F3, 106, twntt, r4b3, r4b3, 43, 1, 0, 14, 1 # id: (106, 105); id: (48, 103); 0 1 0 11 w_1_1_0 +F3, 105, nop, 3 # id: (105, 569); nop for not ready instr (105, 104) +F3, 105, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (105, 104); id: (48, 104); 0 1 0 11 w_1_1_0 +F3, 107, nop, 21 # id: (107, 570); nop for not ready instr (107, 106) +F3, 107, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 2, 1 # id: (107, 106); id: (49, 108); 0 1 0 10 w_1_2_0 +F3, 109, twntt, r4b3, r4b3, 42, 2, 0, 14, 1 # id: (109, 108); id: (49, 106); 0 1 0 10 w_1_2_0 +F3, 108, nop, 3 # id: (108, 571); nop for not ready instr (108, 107) +F3, 108, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (108, 107); id: (49, 107); 0 1 0 10 w_1_2_0 +F3, 110, nop, 21 # id: (110, 572); nop for not ready instr (110, 109) +F3, 110, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 3, 1 # id: (110, 109); id: (50, 111); 0 1 0 9 w_1_3_0 +F3, 112, twntt, r4b3, r4b3, 41, 3, 0, 14, 1 # id: (112, 111); id: (50, 109); 0 1 0 9 w_1_3_0 +F3, 111, nop, 3 # id: (111, 573); nop for not ready instr (111, 110) +F3, 111, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (111, 110); id: (50, 110); 0 1 0 9 w_1_3_0 +F3, 113, nop, 21 # id: (113, 574); nop for not ready instr (113, 112) +F3, 113, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 4, 1 # id: (113, 112); id: (51, 114); 0 1 0 8 w_1_4_0 +F3, 115, twntt, r4b3, r4b3, 40, 4, 0, 14, 1 # id: (115, 114); id: (51, 112); 0 1 0 8 w_1_4_0 +F3, 114, nop, 3 # id: (114, 575); nop for not ready instr (114, 113) +F3, 114, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (114, 113); id: (51, 113); 0 1 0 8 w_1_4_0 +F3, 116, nop, 21 # id: (116, 576); nop for not ready instr (116, 115) +F3, 116, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 5, 1 # id: (116, 115); id: (52, 117); 0 1 0 7 w_1_5_0 +F3, 118, twntt, r4b3, r4b3, 39, 5, 0, 14, 1 # id: (118, 117); id: (52, 115); 0 1 0 7 w_1_5_0 +F3, 117, nop, 3 # id: (117, 577); nop for not ready instr (117, 116) +F3, 117, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (117, 116); id: (52, 116); 0 1 0 7 w_1_5_0 +F3, 119, nop, 21 # id: (119, 578); nop for not ready instr (119, 118) +F3, 119, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 6, 1 # id: (119, 118); id: (53, 120); 0 1 0 6 w_1_6_0 +F3, 121, twntt, r4b3, r4b3, 38, 6, 0, 14, 1 # id: (121, 120); id: (53, 118); 0 1 0 6 w_1_6_0 +F3, 120, nop, 3 # id: (120, 579); nop for not ready instr (120, 119) +F3, 120, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (120, 119); id: (53, 119); 0 1 0 6 w_1_6_0 +F3, 122, nop, 21 # id: (122, 580); nop for not ready instr (122, 121) +F3, 122, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 7, 1 # id: (122, 121); id: (54, 123); 0 1 0 5 w_1_7_0 +F3, 124, twntt, r4b3, r4b3, 37, 7, 0, 14, 1 # id: (124, 123); id: (54, 121); 0 1 0 5 w_1_7_0 +F3, 123, nop, 3 # id: (123, 581); nop for not ready instr (123, 122) +F3, 123, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (123, 122); id: (54, 122); 0 1 0 5 w_1_7_0 +F3, 125, nop, 21 # id: (125, 582); nop for not ready instr (125, 124) +F3, 125, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 8, 1 # id: (125, 124); id: (55, 126); 0 1 0 4 w_1_8_0 +F3, 127, twntt, r4b3, r4b3, 36, 8, 0, 14, 1 # id: (127, 126); id: (55, 124); 0 1 0 4 w_1_8_0 +F3, 3, bexit # id: (3, 583); terminating bundle 3 +F4, 126, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (126, 125); id: (55, 125); 0 1 0 4 w_1_8_0 +F4, 128, nop, 21 # id: (128, 586); nop for not ready instr (128, 127) +F4, 128, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 9, 1 # id: (128, 127); id: (56, 129); 0 1 0 3 w_1_9_0 +F4, 130, twntt, r4b3, r4b3, 35, 9, 0, 14, 1 # id: (130, 129); id: (56, 127); 0 1 0 3 w_1_9_0 +F4, 129, nop, 3 # id: (129, 587); nop for not ready instr (129, 128) +F4, 129, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (129, 128); id: (56, 128); 0 1 0 3 w_1_9_0 +F4, 131, nop, 21 # id: (131, 588); nop for not ready instr (131, 130) +F4, 131, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 10, 1 # id: (131, 130); id: (57, 132); 0 1 0 2 w_1_10_0 +F4, 133, twntt, r4b3, r4b3, 34, 10, 0, 14, 1 # id: (133, 132); id: (57, 130); 0 1 0 2 w_1_10_0 +F4, 132, nop, 3 # id: (132, 589); nop for not ready instr (132, 131) +F4, 132, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (132, 131); id: (57, 131); 0 1 0 2 w_1_10_0 +F4, 134, nop, 21 # id: (134, 590); nop for not ready instr (134, 133) +F4, 134, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 11, 1 # id: (134, 133); id: (58, 135); 0 1 0 1 w_1_11_0 +F4, 136, twntt, r4b3, r4b3, 33, 11, 0, 14, 1 # id: (136, 135); id: (58, 133); 0 1 0 1 w_1_11_0 +F4, 135, nop, 3 # id: (135, 591); nop for not ready instr (135, 134) +F4, 135, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (135, 134); id: (58, 134); 0 1 0 1 w_1_11_0 +F4, 137, nop, 21 # id: (137, 592); nop for not ready instr (137, 136) +F4, 137, ntt, r5b1, r5b2, r3b1, r3b2, r4b3, 12, 1 # id: (137, 136); id: (59, 138); 0 1 0 0 w_1_12_0 +F4, 139, twntt, r4b3, r4b3, 32, 12, 0, 14, 1 # id: (139, 138); id: (59, 136); 0 1 0 0 w_1_12_0 +F4, 138, nop, 3 # id: (138, 593); nop for not ready instr (138, 137) +F4, 138, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (138, 137); id: (59, 137); 0 1 0 0 w_1_12_0 +F4, 140, nop, 21 # id: (140, 594); nop for not ready instr (140, 139) +F4, 140, ntt, r3b1, r3b2, r5b1, r5b2, r4b3, 13, 1 # id: (140, 139); id: (60, 140); 0 1 0 -1 w_1_13_0 +F4, 141, nop, 4 # id: (141, 595); nop for not ready instr (141, 140) +F4, 141, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (141, 140); id: (60, 139); 0 1 0 -1 w_1_13_0 +F4, 142, move, r11b2, r6b0 # id: (142, 599); variable "rlk_0_0_1_0" +F4, 144, move, r13b2, r7b0 # id: (144, 603); variable "rlk_1_0_1_0" +F4, 142, nop, 19 # id: (142, 604); nop for not ready instr (142, 141) +F4, 142, mul, r12b2, r3b1, r11b2, 1 # id: (142, 141); id: (61, 141) +F4, 143, move, r11b1, r8b0 # id: (143, 608); variable "rlk_0_0_1_1" +F4, 144, mul, r14b2, r3b1, r13b2, 1 # id: (144, 143); id: (63, 143) +F4, 145, move, r12b1, r9b0 # id: (145, 612); variable "rlk_1_0_1_1" +F4, 143, nop, 2 # id: (143, 613); nop for not ready instr (143, 142) +F4, 143, mul, r5b3, r3b2, r11b1, 1 # id: (143, 142); id: (62, 142) +F4, 145, nop, 0 # id: (145, 614); nop for not ready instr (145, 144) +F4, 145, mul, r6b3, r3b2, r12b1, 1 # id: (145, 144); id: (64, 144) +F4, 4, bexit # id: (4, 615); terminating bundle 4 +F4, 4, nop, 0 # id: (4, 616) +F4, 4, nop, 0 # id: (4, 617) +F4, 4, nop, 0 # id: (4, 618) +F4, 4, nop, 0 # id: (4, 619) +F4, 4, nop, 0 # id: (4, 620) +F4, 4, nop, 0 # id: (4, 621) +F4, 4, nop, 0 # id: (4, 622) +F4, 4, nop, 0 # id: (4, 623) +F4, 4, nop, 0 # id: (4, 624) +F4, 4, nop, 0 # id: (4, 625) +F4, 4, nop, 0 # id: (4, 626) +F4, 4, nop, 0 # id: (4, 627) +F4, 4, nop, 0 # id: (4, 628) +F4, 4, nop, 0 # id: (4, 629) +F4, 4, nop, 0 # id: (4, 630) +F4, 4, nop, 0 # id: (4, 631) +F4, 4, nop, 0 # id: (4, 632) +F4, 4, nop, 0 # id: (4, 633) +F4, 4, nop, 0 # id: (4, 634) +F4, 4, nop, 0 # id: (4, 635) +F4, 4, nop, 0 # id: (4, 636) +F4, 4, nop, 0 # id: (4, 637) +F4, 4, nop, 0 # id: (4, 638) +F4, 4, nop, 0 # id: (4, 639) +F4, 4, nop, 0 # id: (4, 640) +F4, 4, nop, 0 # id: (4, 641) +F4, 4, nop, 0 # id: (4, 642) +F5, 146, rshuffle, r12b2, r5b3, r12b2, r5b3, 0, intt # id: (146, 145); id: (65, 146); 0 1 1 12 w_1_0_0 +F5, 248, nop, 3 # id: (248, 645); nop for not ready instr (248, 247) +F5, 248, rshuffle, r14b2, r6b3, r14b2, r6b3, 0, intt # id: (248, 247); id: (113, 248); 0 1 1 12 w_1_0_0 +F5, 147, nop, 16 # id: (147, 646); nop for not ready instr (147, 146) +F5, 147, intt, r15b2, r7b3, r12b2, r5b3, r13b1, 0, 1 # id: (147, 146); id: (65, 147); 0 1 1 12 w_1_0_0 +F5, 148, twintt, r13b1, r13b1, 60, 0, 0, 14, 1 # id: (148, 147); id: (65, 145); 0 1 1 12 w_1_0_0 +F5, 149, nop, 3 # id: (149, 647); nop for not ready instr (149, 148) +F5, 149, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (149, 148); id: (66, 149); 0 1 1 11 w_1_1_0 +F5, 150, nop, 21 # id: (150, 648); nop for not ready instr (150, 149) +F5, 150, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 1, 1 # id: (150, 149); id: (66, 150); 0 1 1 11 w_1_1_0 +F5, 151, twintt, r13b1, r13b1, 59, 1, 0, 14, 1 # id: (151, 150); id: (66, 148); 0 1 1 11 w_1_1_0 +F5, 152, nop, 3 # id: (152, 649); nop for not ready instr (152, 151) +F5, 152, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (152, 151); id: (67, 152); 0 1 1 10 w_1_2_0 +F5, 153, nop, 21 # id: (153, 650); nop for not ready instr (153, 152) +F5, 153, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 2, 1 # id: (153, 152); id: (67, 153); 0 1 1 10 w_1_2_0 +F5, 154, twintt, r13b1, r13b1, 58, 2, 0, 14, 1 # id: (154, 153); id: (67, 151); 0 1 1 10 w_1_2_0 +F5, 155, nop, 3 # id: (155, 651); nop for not ready instr (155, 154) +F5, 155, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (155, 154); id: (68, 155); 0 1 1 9 w_1_3_0 +F5, 156, nop, 21 # id: (156, 652); nop for not ready instr (156, 155) +F5, 156, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 3, 1 # id: (156, 155); id: (68, 156); 0 1 1 9 w_1_3_0 +F5, 157, twintt, r13b1, r13b1, 57, 3, 0, 14, 1 # id: (157, 156); id: (68, 154); 0 1 1 9 w_1_3_0 +F5, 158, nop, 3 # id: (158, 653); nop for not ready instr (158, 157) +F5, 158, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (158, 157); id: (69, 158); 0 1 1 8 w_1_4_0 +F5, 159, nop, 21 # id: (159, 654); nop for not ready instr (159, 158) +F5, 159, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 4, 1 # id: (159, 158); id: (69, 159); 0 1 1 8 w_1_4_0 +F5, 160, twintt, r13b1, r13b1, 56, 4, 0, 14, 1 # id: (160, 159); id: (69, 157); 0 1 1 8 w_1_4_0 +F5, 161, nop, 3 # id: (161, 655); nop for not ready instr (161, 160) +F5, 161, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (161, 160); id: (70, 161); 0 1 1 7 w_1_5_0 +F5, 162, nop, 21 # id: (162, 656); nop for not ready instr (162, 161) +F5, 162, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 5, 1 # id: (162, 161); id: (70, 162); 0 1 1 7 w_1_5_0 +F5, 163, twintt, r13b1, r13b1, 55, 5, 0, 14, 1 # id: (163, 162); id: (70, 160); 0 1 1 7 w_1_5_0 +F5, 164, nop, 3 # id: (164, 657); nop for not ready instr (164, 163) +F5, 164, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (164, 163); id: (71, 164); 0 1 1 6 w_1_6_0 +F5, 165, nop, 21 # id: (165, 658); nop for not ready instr (165, 164) +F5, 165, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 6, 1 # id: (165, 164); id: (71, 165); 0 1 1 6 w_1_6_0 +F5, 166, twintt, r13b1, r13b1, 54, 6, 0, 14, 1 # id: (166, 165); id: (71, 163); 0 1 1 6 w_1_6_0 +F5, 167, nop, 3 # id: (167, 659); nop for not ready instr (167, 166) +F5, 167, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (167, 166); id: (72, 167); 0 1 1 5 w_1_7_0 +F5, 168, nop, 21 # id: (168, 660); nop for not ready instr (168, 167) +F5, 168, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 7, 1 # id: (168, 167); id: (72, 168); 0 1 1 5 w_1_7_0 +F5, 169, twintt, r13b1, r13b1, 53, 7, 0, 14, 1 # id: (169, 168); id: (72, 166); 0 1 1 5 w_1_7_0 +F5, 170, nop, 3 # id: (170, 661); nop for not ready instr (170, 169) +F5, 170, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (170, 169); id: (73, 170); 0 1 1 4 w_1_8_0 +F5, 171, nop, 21 # id: (171, 662); nop for not ready instr (171, 170) +F5, 171, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 8, 1 # id: (171, 170); id: (73, 171); 0 1 1 4 w_1_8_0 +F5, 172, twintt, r13b1, r13b1, 52, 8, 0, 14, 1 # id: (172, 171); id: (73, 169); 0 1 1 4 w_1_8_0 +F5, 173, nop, 3 # id: (173, 663); nop for not ready instr (173, 172) +F5, 173, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (173, 172); id: (74, 173); 0 1 1 3 w_1_9_0 +F5, 174, nop, 21 # id: (174, 664); nop for not ready instr (174, 173) +F5, 174, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 9, 1 # id: (174, 173); id: (74, 174); 0 1 1 3 w_1_9_0 +F5, 175, twintt, r13b1, r13b1, 51, 9, 0, 14, 1 # id: (175, 174); id: (74, 172); 0 1 1 3 w_1_9_0 +F5, 176, nop, 3 # id: (176, 665); nop for not ready instr (176, 175) +F5, 176, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (176, 175); id: (75, 176); 0 1 1 2 w_1_10_0 +F5, 177, nop, 21 # id: (177, 666); nop for not ready instr (177, 176) +F5, 177, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 10, 1 # id: (177, 176); id: (75, 177); 0 1 1 2 w_1_10_0 +F5, 178, twintt, r13b1, r13b1, 50, 10, 0, 14, 1 # id: (178, 177); id: (75, 175); 0 1 1 2 w_1_10_0 +F5, 179, nop, 3 # id: (179, 667); nop for not ready instr (179, 178) +F5, 179, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (179, 178); id: (76, 179); 0 1 1 1 w_1_11_0 +F5, 180, nop, 21 # id: (180, 668); nop for not ready instr (180, 179) +F5, 180, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 11, 1 # id: (180, 179); id: (76, 180); 0 1 1 1 w_1_11_0 +F5, 181, twintt, r13b1, r13b1, 49, 11, 0, 14, 1 # id: (181, 180); id: (76, 178); 0 1 1 1 w_1_11_0 +F5, 182, nop, 3 # id: (182, 669); nop for not ready instr (182, 181) +F5, 182, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (182, 181); id: (77, 182); 0 1 1 0 w_1_12_0 +F5, 5, bexit # id: (5, 670); terminating bundle 5 +F6, 183, intt, r15b2, r7b3, r16b2, r8b3, r13b1, 12, 1 # id: (183, 182); id: (77, 183); 0 1 1 0 w_1_12_0 +F6, 184, twintt, r13b1, r13b1, 48, 12, 0, 14, 1 # id: (184, 183); id: (77, 181); 0 1 1 0 w_1_12_0 +F6, 185, nop, 3 # id: (185, 675); nop for not ready instr (185, 184) +F6, 185, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (185, 184); id: (78, 184); 0 1 1 -1 w_1_13_0 +F6, 186, nop, 21 # id: (186, 676); nop for not ready instr (186, 185) +F6, 186, intt, r16b2, r8b3, r15b2, r7b3, r13b1, 13, 1 # id: (186, 185); id: (78, 185); 0 1 1 -1 w_1_13_0 +F6, 249, intt, r15b2, r7b3, r14b2, r6b3, r14b1, 0, 1 # id: (249, 248); id: (113, 249); 0 1 1 12 w_1_0_0 +F6, 250, twintt, r14b1, r14b1, 60, 0, 0, 14, 1 # id: (250, 249); id: (113, 247); 0 1 1 12 w_1_0_0 +F6, 188, move, r15b1, r0b0 # id: (188, 680); variable "ipsi_1_1" +F6, 187, move, r16b1, r1b0 # id: (187, 684); variable "ipsi_1_0" +F6, 251, nop, 1 # id: (251, 685); nop for not ready instr (251, 250) +F6, 251, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (251, 250); id: (114, 251); 0 1 1 11 w_1_1_0 +F6, 188, nop, 0 # id: (188, 686); nop for not ready instr (188, 187) +F6, 188, mul, r8b3, r8b3, r15b1, 1 # id: (188, 187); id: (80, 187) +F6, 187, mul, r16b2, r16b2, r16b1, 1 # id: (187, 186); id: (79, 186) +F6, 190, nop, 3 # id: (190, 687); nop for not ready instr (190, 189) +F6, 190, muli, r8b3, r8b3, iN, 1 # id: (190, 189); id: (82, 189) +F6, 189, muli, r16b2, r16b2, iN, 1 # id: (189, 188); id: (81, 188) +F6, 192, nop, 3 # id: (192, 688); nop for not ready instr (192, 191) +F6, 192, muli, r8b3, r8b3, t_inverse_mod_p_0, 1 # id: (192, 191); id: (84, 191) +F6, 191, muli, r16b2, r16b2, t_inverse_mod_p_0, 1 # id: (191, 190); id: (83, 190) +F6, 194, nop, 3 # id: (194, 689); nop for not ready instr (194, 193) +F6, 194, muli, r8b3, r8b3, one, 1 # id: (194, 193); id: (86, 193) +F6, 193, muli, r16b2, r16b2, one, 1 # id: (193, 192); id: (85, 192) +F6, 196, nop, 3 # id: (196, 690); nop for not ready instr (196, 195) +F6, 196, muli, r3b2, r8b3, R2_0, 0 # id: (196, 195); id: (88, 195) +F6, 195, muli, r3b1, r16b2, R2_0, 0 # id: (195, 194); id: (87, 194) +F6, 252, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 1, 1 # id: (252, 251); id: (114, 252); 0 1 1 11 w_1_1_0 +F6, 253, twintt, r14b1, r14b1, 59, 1, 0, 14, 1 # id: (253, 252); id: (114, 250); 0 1 1 11 w_1_1_0 +F6, 198, nop, 1 # id: (198, 691); nop for not ready instr (198, 197) +F6, 198, mul, r3b2, r3b2, r4b1, 0 # id: (198, 197); id: (90, 197) +F6, 197, mul, r3b1, r3b1, r4b2, 0 # id: (197, 196); id: (89, 196) +F6, 254, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (254, 253); id: (115, 254); 0 1 1 10 w_1_2_0 +F6, 199, nop, 3 # id: (199, 692); nop for not ready instr (199, 198) +F6, 199, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 0, 0 # id: (199, 198); id: (91, 200); 0 0 0 12 w_0_0_0 +F6, 201, twntt, r9b3, r9b3, 12, 0, 0, 14, 0 # id: (201, 200); id: (91, 198); 0 0 0 12 w_0_0_0 +F6, 255, nop, 15 # id: (255, 693); nop for not ready instr (255, 254) +F6, 255, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 2, 1 # id: (255, 254); id: (115, 255); 0 1 1 10 w_1_2_0 +F6, 256, twintt, r14b1, r14b1, 58, 2, 0, 14, 1 # id: (256, 255); id: (115, 253); 0 1 1 10 w_1_2_0 +F6, 257, nop, 3 # id: (257, 694); nop for not ready instr (257, 256) +F6, 257, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (257, 256); id: (116, 257); 0 1 1 9 w_1_3_0 +F6, 258, nop, 21 # id: (258, 695); nop for not ready instr (258, 257) +F6, 258, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 3, 1 # id: (258, 257); id: (116, 258); 0 1 1 9 w_1_3_0 +F6, 259, twintt, r14b1, r14b1, 57, 3, 0, 14, 1 # id: (259, 258); id: (116, 256); 0 1 1 9 w_1_3_0 +F6, 260, nop, 3 # id: (260, 696); nop for not ready instr (260, 259) +F6, 260, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (260, 259); id: (117, 260); 0 1 1 8 w_1_4_0 +F6, 261, nop, 21 # id: (261, 697); nop for not ready instr (261, 260) +F6, 261, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 4, 1 # id: (261, 260); id: (117, 261); 0 1 1 8 w_1_4_0 +F6, 262, twintt, r14b1, r14b1, 56, 4, 0, 14, 1 # id: (262, 261); id: (117, 259); 0 1 1 8 w_1_4_0 +F6, 263, nop, 3 # id: (263, 698); nop for not ready instr (263, 262) +F6, 263, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (263, 262); id: (118, 263); 0 1 1 7 w_1_5_0 +F6, 264, nop, 21 # id: (264, 699); nop for not ready instr (264, 263) +F6, 264, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 5, 1 # id: (264, 263); id: (118, 264); 0 1 1 7 w_1_5_0 +F6, 265, twintt, r14b1, r14b1, 55, 5, 0, 14, 1 # id: (265, 264); id: (118, 262); 0 1 1 7 w_1_5_0 +F6, 266, nop, 3 # id: (266, 700); nop for not ready instr (266, 265) +F6, 266, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (266, 265); id: (119, 266); 0 1 1 6 w_1_6_0 +F6, 267, nop, 21 # id: (267, 701); nop for not ready instr (267, 266) +F6, 267, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 6, 1 # id: (267, 266); id: (119, 267); 0 1 1 6 w_1_6_0 +F6, 268, twintt, r14b1, r14b1, 54, 6, 0, 14, 1 # id: (268, 267); id: (119, 265); 0 1 1 6 w_1_6_0 +F6, 269, nop, 3 # id: (269, 702); nop for not ready instr (269, 268) +F6, 269, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (269, 268); id: (120, 269); 0 1 1 5 w_1_7_0 +F6, 270, nop, 21 # id: (270, 703); nop for not ready instr (270, 269) +F6, 270, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 7, 1 # id: (270, 269); id: (120, 270); 0 1 1 5 w_1_7_0 +F6, 271, twintt, r14b1, r14b1, 53, 7, 0, 14, 1 # id: (271, 270); id: (120, 268); 0 1 1 5 w_1_7_0 +F7, 272, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (272, 271); id: (121, 272); 0 1 1 4 w_1_8_0 +F7, 273, nop, 21 # id: (273, 706); nop for not ready instr (273, 272) +F7, 273, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 8, 1 # id: (273, 272); id: (121, 273); 0 1 1 4 w_1_8_0 +F7, 274, twintt, r14b1, r14b1, 52, 8, 0, 14, 1 # id: (274, 273); id: (121, 271); 0 1 1 4 w_1_8_0 +F7, 275, nop, 3 # id: (275, 707); nop for not ready instr (275, 274) +F7, 275, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (275, 274); id: (122, 275); 0 1 1 3 w_1_9_0 +F7, 276, nop, 21 # id: (276, 708); nop for not ready instr (276, 275) +F7, 276, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 9, 1 # id: (276, 275); id: (122, 276); 0 1 1 3 w_1_9_0 +F7, 277, twintt, r14b1, r14b1, 51, 9, 0, 14, 1 # id: (277, 276); id: (122, 274); 0 1 1 3 w_1_9_0 +F7, 278, nop, 3 # id: (278, 709); nop for not ready instr (278, 277) +F7, 278, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (278, 277); id: (123, 278); 0 1 1 2 w_1_10_0 +F7, 279, nop, 21 # id: (279, 710); nop for not ready instr (279, 278) +F7, 279, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 10, 1 # id: (279, 278); id: (123, 279); 0 1 1 2 w_1_10_0 +F7, 280, twintt, r14b1, r14b1, 50, 10, 0, 14, 1 # id: (280, 279); id: (123, 277); 0 1 1 2 w_1_10_0 +F7, 281, nop, 3 # id: (281, 711); nop for not ready instr (281, 280) +F7, 281, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (281, 280); id: (124, 281); 0 1 1 1 w_1_11_0 +F7, 282, nop, 21 # id: (282, 712); nop for not ready instr (282, 281) +F7, 282, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 11, 1 # id: (282, 281); id: (124, 282); 0 1 1 1 w_1_11_0 +F7, 283, twintt, r14b1, r14b1, 49, 11, 0, 14, 1 # id: (283, 282); id: (124, 280); 0 1 1 1 w_1_11_0 +F7, 284, nop, 3 # id: (284, 713); nop for not ready instr (284, 283) +F7, 284, rshuffle, r16b2, r8b3, r16b2, r8b3, 0, intt # id: (284, 283); id: (125, 284); 0 1 1 0 w_1_12_0 +F7, 285, nop, 21 # id: (285, 714); nop for not ready instr (285, 284) +F7, 285, intt, r15b2, r7b3, r16b2, r8b3, r14b1, 12, 1 # id: (285, 284); id: (125, 285); 0 1 1 0 w_1_12_0 +F7, 286, twintt, r14b1, r14b1, 48, 12, 0, 14, 1 # id: (286, 285); id: (125, 283); 0 1 1 0 w_1_12_0 +F7, 287, nop, 3 # id: (287, 715); nop for not ready instr (287, 286) +F7, 287, rshuffle, r15b2, r7b3, r15b2, r7b3, 0, intt # id: (287, 286); id: (126, 286); 0 1 1 -1 w_1_13_0 +F7, 288, nop, 21 # id: (288, 716); nop for not ready instr (288, 287) +F7, 288, intt, r16b2, r8b3, r15b2, r7b3, r14b1, 13, 1 # id: (288, 287); id: (126, 287); 0 1 1 -1 w_1_13_0 +F7, 289, nop, 4 # id: (289, 717); nop for not ready instr (289, 288) +F7, 289, mul, r16b2, r16b2, r16b1, 1 # id: (289, 288); id: (127, 288) +F7, 290, mul, r8b3, r8b3, r15b1, 1 # id: (290, 289); id: (128, 289) +F7, 291, nop, 3 # id: (291, 718); nop for not ready instr (291, 290) +F7, 291, muli, r16b2, r16b2, iN, 1 # id: (291, 290); id: (129, 290) +F7, 292, muli, r8b3, r8b3, iN, 1 # id: (292, 291); id: (130, 291) +F7, 293, nop, 3 # id: (293, 719); nop for not ready instr (293, 292) +F7, 293, muli, r16b2, r16b2, t_inverse_mod_p_0, 1 # id: (293, 292); id: (131, 292) +F7, 294, muli, r8b3, r8b3, t_inverse_mod_p_0, 1 # id: (294, 293); id: (132, 293) +F7, 295, nop, 3 # id: (295, 720); nop for not ready instr (295, 294) +F7, 295, muli, r16b2, r16b2, one, 1 # id: (295, 294); id: (133, 294) +F7, 296, muli, r8b3, r8b3, one, 1 # id: (296, 295); id: (134, 295) +F7, 7, bexit # id: (7, 721); terminating bundle 7 +F7, 7, nop, 0 # id: (7, 722) +F7, 7, nop, 0 # id: (7, 723) +F7, 7, nop, 0 # id: (7, 724) +F7, 7, nop, 0 # id: (7, 725) +F7, 7, nop, 0 # id: (7, 726) +F7, 7, nop, 0 # id: (7, 727) +F7, 7, nop, 0 # id: (7, 728) +F7, 7, nop, 0 # id: (7, 729) +F7, 7, nop, 0 # id: (7, 730) +F7, 7, nop, 0 # id: (7, 731) +F7, 7, nop, 0 # id: (7, 732) +F7, 7, nop, 0 # id: (7, 733) +F7, 7, nop, 0 # id: (7, 734) +F7, 7, nop, 0 # id: (7, 735) +F7, 7, nop, 0 # id: (7, 736) +F7, 7, nop, 0 # id: (7, 737) +F7, 7, nop, 0 # id: (7, 738) +F7, 7, nop, 0 # id: (7, 739) +F7, 7, nop, 0 # id: (7, 740) +F7, 7, nop, 0 # id: (7, 741) +F7, 7, nop, 0 # id: (7, 742) +F7, 7, nop, 0 # id: (7, 743) +F7, 7, nop, 0 # id: (7, 744) +F8, 200, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (200, 199); id: (91, 199); 0 0 0 12 w_0_0_0 +F8, 202, nop, 21 # id: (202, 747); nop for not ready instr (202, 201) +F8, 202, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 1, 0 # id: (202, 201); id: (92, 203); 0 0 0 11 w_0_1_0 +F8, 204, twntt, r9b3, r9b3, 11, 1, 0, 14, 0 # id: (204, 203); id: (92, 201); 0 0 0 11 w_0_1_0 +F8, 203, nop, 3 # id: (203, 748); nop for not ready instr (203, 202) +F8, 203, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (203, 202); id: (92, 202); 0 0 0 11 w_0_1_0 +F8, 205, nop, 21 # id: (205, 749); nop for not ready instr (205, 204) +F8, 205, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 2, 0 # id: (205, 204); id: (93, 206); 0 0 0 10 w_0_2_0 +F8, 207, twntt, r9b3, r9b3, 10, 2, 0, 14, 0 # id: (207, 206); id: (93, 204); 0 0 0 10 w_0_2_0 +F8, 206, nop, 3 # id: (206, 750); nop for not ready instr (206, 205) +F8, 206, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (206, 205); id: (93, 205); 0 0 0 10 w_0_2_0 +F8, 208, nop, 21 # id: (208, 751); nop for not ready instr (208, 207) +F8, 208, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 3, 0 # id: (208, 207); id: (94, 209); 0 0 0 9 w_0_3_0 +F8, 210, twntt, r9b3, r9b3, 9, 3, 0, 14, 0 # id: (210, 209); id: (94, 207); 0 0 0 9 w_0_3_0 +F8, 209, nop, 3 # id: (209, 752); nop for not ready instr (209, 208) +F8, 209, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (209, 208); id: (94, 208); 0 0 0 9 w_0_3_0 +F8, 211, nop, 21 # id: (211, 753); nop for not ready instr (211, 210) +F8, 211, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 4, 0 # id: (211, 210); id: (95, 212); 0 0 0 8 w_0_4_0 +F8, 213, twntt, r9b3, r9b3, 8, 4, 0, 14, 0 # id: (213, 212); id: (95, 210); 0 0 0 8 w_0_4_0 +F8, 212, nop, 3 # id: (212, 754); nop for not ready instr (212, 211) +F8, 212, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (212, 211); id: (95, 211); 0 0 0 8 w_0_4_0 +F8, 214, nop, 21 # id: (214, 755); nop for not ready instr (214, 213) +F8, 214, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 5, 0 # id: (214, 213); id: (96, 215); 0 0 0 7 w_0_5_0 +F8, 216, twntt, r9b3, r9b3, 7, 5, 0, 14, 0 # id: (216, 215); id: (96, 213); 0 0 0 7 w_0_5_0 +F8, 215, nop, 3 # id: (215, 756); nop for not ready instr (215, 214) +F8, 215, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (215, 214); id: (96, 214); 0 0 0 7 w_0_5_0 +F8, 217, nop, 21 # id: (217, 757); nop for not ready instr (217, 216) +F8, 217, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 6, 0 # id: (217, 216); id: (97, 218); 0 0 0 6 w_0_6_0 +F8, 219, twntt, r9b3, r9b3, 6, 6, 0, 14, 0 # id: (219, 218); id: (97, 216); 0 0 0 6 w_0_6_0 +F8, 218, nop, 3 # id: (218, 758); nop for not ready instr (218, 217) +F8, 218, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (218, 217); id: (97, 217); 0 0 0 6 w_0_6_0 +F8, 220, nop, 21 # id: (220, 759); nop for not ready instr (220, 219) +F8, 220, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 7, 0 # id: (220, 219); id: (98, 221); 0 0 0 5 w_0_7_0 +F8, 222, twntt, r9b3, r9b3, 5, 7, 0, 14, 0 # id: (222, 221); id: (98, 219); 0 0 0 5 w_0_7_0 +F8, 221, nop, 3 # id: (221, 760); nop for not ready instr (221, 220) +F8, 221, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (221, 220); id: (98, 220); 0 0 0 5 w_0_7_0 +F8, 223, nop, 21 # id: (223, 761); nop for not ready instr (223, 222) +F8, 223, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 8, 0 # id: (223, 222); id: (99, 224); 0 0 0 4 w_0_8_0 +F8, 225, twntt, r9b3, r9b3, 4, 8, 0, 14, 0 # id: (225, 224); id: (99, 222); 0 0 0 4 w_0_8_0 +F8, 224, nop, 3 # id: (224, 762); nop for not ready instr (224, 223) +F8, 224, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (224, 223); id: (99, 223); 0 0 0 4 w_0_8_0 +F8, 226, nop, 21 # id: (226, 763); nop for not ready instr (226, 225) +F8, 226, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 9, 0 # id: (226, 225); id: (100, 227); 0 0 0 3 w_0_9_0 +F8, 228, twntt, r9b3, r9b3, 3, 9, 0, 14, 0 # id: (228, 227); id: (100, 225); 0 0 0 3 w_0_9_0 +F8, 227, nop, 3 # id: (227, 764); nop for not ready instr (227, 226) +F8, 227, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (227, 226); id: (100, 226); 0 0 0 3 w_0_9_0 +F8, 229, nop, 21 # id: (229, 765); nop for not ready instr (229, 228) +F8, 229, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 10, 0 # id: (229, 228); id: (101, 230); 0 0 0 2 w_0_10_0 +F8, 231, twntt, r9b3, r9b3, 2, 10, 0, 14, 0 # id: (231, 230); id: (101, 228); 0 0 0 2 w_0_10_0 +F8, 230, nop, 3 # id: (230, 766); nop for not ready instr (230, 229) +F8, 230, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (230, 229); id: (101, 229); 0 0 0 2 w_0_10_0 +F8, 232, nop, 21 # id: (232, 767); nop for not ready instr (232, 231) +F8, 232, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 11, 0 # id: (232, 231); id: (102, 233); 0 0 0 1 w_0_11_0 +F8, 234, twntt, r9b3, r9b3, 1, 11, 0, 14, 0 # id: (234, 233); id: (102, 231); 0 0 0 1 w_0_11_0 +F8, 233, nop, 3 # id: (233, 768); nop for not ready instr (233, 232) +F8, 233, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (233, 232); id: (102, 232); 0 0 0 1 w_0_11_0 +F8, 235, nop, 21 # id: (235, 769); nop for not ready instr (235, 234) +F8, 235, ntt, r5b1, r5b2, r3b1, r3b2, r9b3, 12, 0 # id: (235, 234); id: (103, 236); 0 0 0 0 w_0_12_0 +F8, 237, twntt, r9b3, r9b3, 0, 12, 0, 14, 0 # id: (237, 236); id: (103, 234); 0 0 0 0 w_0_12_0 +F8, 236, nop, 3 # id: (236, 770); nop for not ready instr (236, 235) +F8, 236, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (236, 235); id: (103, 235); 0 0 0 0 w_0_12_0 +F8, 238, nop, 21 # id: (238, 771); nop for not ready instr (238, 237) +F8, 238, ntt, r3b1, r3b2, r5b1, r5b2, r9b3, 13, 0 # id: (238, 237); id: (104, 238); 0 0 0 -1 w_0_13_0 +F8, 8, bexit # id: (8, 772); terminating bundle 8 +F9, 239, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (239, 238); id: (104, 237); 0 0 0 -1 w_0_13_0 +F9, 240, nop, 21 # id: (240, 777); nop for not ready instr (240, 239) +F9, 240, muli, r3b1, r3b1, t_0, 0 # id: (240, 239); id: (105, 239) +F9, 241, muli, r3b2, r3b2, t_0, 0 # id: (241, 240); id: (106, 240) +F9, 242, nop, 3 # id: (242, 778); nop for not ready instr (242, 241) +F9, 242, add, r3b1, r3b1, r7b2, 0 # id: (242, 241); id: (107, 241) +F9, 243, add, r3b2, r3b2, r7b1, 0 # id: (243, 242); id: (108, 242) +F9, 244, nop, 3 # id: (244, 779); nop for not ready instr (244, 243) +F9, 244, muli, r3b1, r3b1, pinv_q_0, 0 # id: (244, 243); id: (109, 243) +F9, 245, muli, r3b2, r3b2, pinv_q_0, 0 # id: (245, 244); id: (110, 244) +F9, 246, move, r17b2, r0b0 # id: (246, 783); variable "ct0_0_0_0" +F9, 247, move, r18b1, r1b0 # id: (247, 787); variable "ct0_0_0_1" +F9, 246, nop, 3 # id: (246, 788); nop for not ready instr (246, 245) +F9, 246, add, r17b1, r3b1, r17b2, 0 # id: (246, 245); id: (111, 245) +F9, 247, add, r19b1, r3b2, r18b1, 0 # id: (247, 246); id: (112, 246) +F9, 297, muli, r3b1, r16b2, R2_0, 0 # id: (297, 296); id: (135, 296) +F9, 298, muli, r3b2, r8b3, R2_0, 0 # id: (298, 297); id: (136, 297) +F9, 246, nop, 1 # id: (246, 791); nop for not ready instr (246, 789) +F9, 246, xstore, r17b1 # id: (246, 789); flushing output; variable "ct1_0_0_0": SPAD(33) <- r17b1 +F9, 299, nop, 0 # id: (299, 793); nop for not ready instr (299, 298) +F9, 299, mul, r3b1, r3b1, r4b2, 0 # id: (299, 298); id: (137, 298) +F9, 300, mul, r3b2, r3b2, r4b1, 0 # id: (300, 299); id: (138, 299) +F9, 247, nop, 1 # id: (247, 794); nop for not ready instr (247, 790) +F9, 247, xstore, r19b1 # id: (247, 790); flushing output; variable "ct1_0_0_1": SPAD(34) <- r19b1 +F9, 301, nop, 1 # id: (301, 796); nop for not ready instr (301, 300) +F9, 301, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 0, 0 # id: (301, 300); id: (139, 302); 0 0 0 12 w_0_0_0 +F9, 303, twntt, r10b3, r10b3, 12, 0, 0, 14, 0 # id: (303, 302); id: (139, 300); 0 0 0 12 w_0_0_0 +F9, 302, nop, 3 # id: (302, 797); nop for not ready instr (302, 301) +F9, 302, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (302, 301); id: (139, 301); 0 0 0 12 w_0_0_0 +F9, 304, nop, 21 # id: (304, 798); nop for not ready instr (304, 303) +F9, 304, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 1, 0 # id: (304, 303); id: (140, 305); 0 0 0 11 w_0_1_0 +F9, 306, twntt, r10b3, r10b3, 11, 1, 0, 14, 0 # id: (306, 305); id: (140, 303); 0 0 0 11 w_0_1_0 +F9, 305, nop, 3 # id: (305, 799); nop for not ready instr (305, 304) +F9, 305, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (305, 304); id: (140, 304); 0 0 0 11 w_0_1_0 +F9, 307, nop, 21 # id: (307, 800); nop for not ready instr (307, 306) +F9, 307, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 2, 0 # id: (307, 306); id: (141, 308); 0 0 0 10 w_0_2_0 +F9, 309, twntt, r10b3, r10b3, 10, 2, 0, 14, 0 # id: (309, 308); id: (141, 306); 0 0 0 10 w_0_2_0 +F9, 308, nop, 3 # id: (308, 801); nop for not ready instr (308, 307) +F9, 308, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (308, 307); id: (141, 307); 0 0 0 10 w_0_2_0 +F9, 310, nop, 21 # id: (310, 802); nop for not ready instr (310, 309) +F9, 310, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 3, 0 # id: (310, 309); id: (142, 311); 0 0 0 9 w_0_3_0 +F9, 312, twntt, r10b3, r10b3, 9, 3, 0, 14, 0 # id: (312, 311); id: (142, 309); 0 0 0 9 w_0_3_0 +F9, 311, nop, 3 # id: (311, 803); nop for not ready instr (311, 310) +F9, 311, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (311, 310); id: (142, 310); 0 0 0 9 w_0_3_0 +F9, 313, nop, 21 # id: (313, 804); nop for not ready instr (313, 312) +F9, 313, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 4, 0 # id: (313, 312); id: (143, 314); 0 0 0 8 w_0_4_0 +F9, 315, twntt, r10b3, r10b3, 8, 4, 0, 14, 0 # id: (315, 314); id: (143, 312); 0 0 0 8 w_0_4_0 +F9, 314, nop, 3 # id: (314, 805); nop for not ready instr (314, 313) +F9, 314, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (314, 313); id: (143, 313); 0 0 0 8 w_0_4_0 +F9, 316, nop, 21 # id: (316, 806); nop for not ready instr (316, 315) +F9, 316, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 5, 0 # id: (316, 315); id: (144, 317); 0 0 0 7 w_0_5_0 +F9, 318, twntt, r10b3, r10b3, 7, 5, 0, 14, 0 # id: (318, 317); id: (144, 315); 0 0 0 7 w_0_5_0 +F9, 317, nop, 3 # id: (317, 807); nop for not ready instr (317, 316) +F9, 317, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (317, 316); id: (144, 316); 0 0 0 7 w_0_5_0 +F9, 319, nop, 21 # id: (319, 808); nop for not ready instr (319, 318) +F9, 319, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 6, 0 # id: (319, 318); id: (145, 320); 0 0 0 6 w_0_6_0 +F9, 321, twntt, r10b3, r10b3, 6, 6, 0, 14, 0 # id: (321, 320); id: (145, 318); 0 0 0 6 w_0_6_0 +F9, 320, nop, 3 # id: (320, 809); nop for not ready instr (320, 319) +F9, 320, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (320, 319); id: (145, 319); 0 0 0 6 w_0_6_0 +F9, 322, nop, 21 # id: (322, 810); nop for not ready instr (322, 321) +F9, 322, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 7, 0 # id: (322, 321); id: (146, 323); 0 0 0 5 w_0_7_0 +F9, 324, twntt, r10b3, r10b3, 5, 7, 0, 14, 0 # id: (324, 323); id: (146, 321); 0 0 0 5 w_0_7_0 +F9, 323, nop, 3 # id: (323, 811); nop for not ready instr (323, 322) +F9, 323, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (323, 322); id: (146, 322); 0 0 0 5 w_0_7_0 +F10, 325, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 8, 0 # id: (325, 324); id: (147, 326); 0 0 0 4 w_0_8_0 +F10, 327, twntt, r10b3, r10b3, 4, 8, 0, 14, 0 # id: (327, 326); id: (147, 324); 0 0 0 4 w_0_8_0 +F10, 326, nop, 3 # id: (326, 818); nop for not ready instr (326, 325) +F10, 326, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (326, 325); id: (147, 325); 0 0 0 4 w_0_8_0 +F10, 328, nop, 21 # id: (328, 819); nop for not ready instr (328, 327) +F10, 328, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 9, 0 # id: (328, 327); id: (148, 329); 0 0 0 3 w_0_9_0 +F10, 330, twntt, r10b3, r10b3, 3, 9, 0, 14, 0 # id: (330, 329); id: (148, 327); 0 0 0 3 w_0_9_0 +F10, 329, nop, 3 # id: (329, 820); nop for not ready instr (329, 328) +F10, 329, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (329, 328); id: (148, 328); 0 0 0 3 w_0_9_0 +F10, 331, nop, 21 # id: (331, 821); nop for not ready instr (331, 330) +F10, 331, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 10, 0 # id: (331, 330); id: (149, 332); 0 0 0 2 w_0_10_0 +F10, 333, twntt, r10b3, r10b3, 2, 10, 0, 14, 0 # id: (333, 332); id: (149, 330); 0 0 0 2 w_0_10_0 +F10, 332, nop, 3 # id: (332, 822); nop for not ready instr (332, 331) +F10, 332, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (332, 331); id: (149, 331); 0 0 0 2 w_0_10_0 +F10, 334, nop, 21 # id: (334, 823); nop for not ready instr (334, 333) +F10, 334, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 11, 0 # id: (334, 333); id: (150, 335); 0 0 0 1 w_0_11_0 +F10, 336, twntt, r10b3, r10b3, 1, 11, 0, 14, 0 # id: (336, 335); id: (150, 333); 0 0 0 1 w_0_11_0 +F10, 335, nop, 3 # id: (335, 824); nop for not ready instr (335, 334) +F10, 335, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (335, 334); id: (150, 334); 0 0 0 1 w_0_11_0 +F10, 337, nop, 21 # id: (337, 825); nop for not ready instr (337, 336) +F10, 337, ntt, r5b1, r5b2, r3b1, r3b2, r10b3, 12, 0 # id: (337, 336); id: (151, 338); 0 0 0 0 w_0_12_0 +F10, 339, twntt, r10b3, r10b3, 0, 12, 0, 14, 0 # id: (339, 338); id: (151, 336); 0 0 0 0 w_0_12_0 +F10, 338, nop, 3 # id: (338, 826); nop for not ready instr (338, 337) +F10, 338, rshuffle, r5b1, r5b2, r5b1, r5b2, 0, ntt # id: (338, 337); id: (151, 337); 0 0 0 0 w_0_12_0 +F10, 340, nop, 21 # id: (340, 827); nop for not ready instr (340, 339) +F10, 340, ntt, r3b1, r3b2, r5b1, r5b2, r10b3, 13, 0 # id: (340, 339); id: (152, 340); 0 0 0 -1 w_0_13_0 +F10, 341, nop, 4 # id: (341, 828); nop for not ready instr (341, 340) +F10, 341, rshuffle, r3b1, r3b2, r3b1, r3b2, 0, ntt # id: (341, 340); id: (152, 339); 0 0 0 -1 w_0_13_0 +F10, 342, nop, 21 # id: (342, 829); nop for not ready instr (342, 341) +F10, 342, muli, r3b1, r3b1, t_0, 0 # id: (342, 341); id: (153, 341) +F10, 343, muli, r3b2, r3b2, t_0, 0 # id: (343, 342); id: (154, 342) +F10, 344, nop, 3 # id: (344, 830); nop for not ready instr (344, 343) +F10, 344, add, r3b1, r3b1, r9b2, 0 # id: (344, 343); id: (155, 343) +F10, 345, add, r3b2, r3b2, r9b1, 0 # id: (345, 344); id: (156, 344) +F10, 346, nop, 3 # id: (346, 831); nop for not ready instr (346, 345) +F10, 346, muli, r3b1, r3b1, pinv_q_0, 0 # id: (346, 345); id: (157, 345) +F10, 347, muli, r3b2, r3b2, pinv_q_0, 0 # id: (347, 346); id: (158, 346) +F10, 348, move, r18b2, r2b0 # id: (348, 835); variable "ct0_1_0_0" +F10, 349, move, r19b1, r3b0 # id: (349, 839); variable "ct0_1_0_1" +F10, 348, nop, 3 # id: (348, 840); nop for not ready instr (348, 347) +F10, 348, add, r17b1, r3b1, r18b2, 0 # id: (348, 347); id: (159, 347) +F10, 349, add, r20b1, r3b2, r19b1, 0 # id: (349, 348); id: (160, 348) +F10, 348, nop, 3 # id: (348, 843); nop for not ready instr (348, 841) +F10, 348, xstore, r17b1 # id: (348, 841); flushing output; variable "ct1_1_0_0": SPAD(35) <- r17b1 +F10, 349, nop, 4 # id: (349, 845); nop for not ready instr (349, 842) +F10, 349, xstore, r20b1 # id: (349, 842); flushing output; variable "ct1_1_0_1": SPAD(36) <- r20b1 +F10, 10, bexit # id: (10, 847); terminating bundle 10 +F10, 10, nop, 0 # id: (10, 848) +F10, 10, nop, 0 # id: (10, 849) +F10, 10, nop, 0 # id: (10, 850) +F10, 10, nop, 0 # id: (10, 851) +F10, 10, nop, 0 # id: (10, 852) +F10, 10, nop, 0 # id: (10, 853) +F10, 10, nop, 0 # id: (10, 854) +F10, 10, nop, 0 # id: (10, 855) +F10, 10, nop, 0 # id: (10, 856) +F10, 10, nop, 0 # id: (10, 857) +F10, 10, nop, 0 # id: (10, 858) +F10, 10, nop, 0 # id: (10, 859) +F10, 10, nop, 0 # id: (10, 860) +F10, 10, nop, 0 # id: (10, 861) +F10, 10, nop, 0 # id: (10, 862) +F10, 10, nop, 0 # id: (10, 863) +F10, 10, nop, 0 # id: (10, 864) From df2c77f66f658f65c7ec2c16a95e38b9435a0901 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Thu, 21 Aug 2025 23:24:10 +0000 Subject: [PATCH 11/12] Docstrings corrections --- .../assembler/instructions/instruction.py | 4 ---- .../hec-assembler-tools/linker/instructions/cinst/bload.py | 3 +-- .../hec-assembler-tools/linker/instructions/cinst/bones.py | 3 +-- .../hec-assembler-tools/linker/instructions/cinst/cload.py | 3 +-- .../linker/instructions/cinst/cstore.py | 2 +- .../hec-assembler-tools/linker/instructions/cinst/nload.py | 3 +-- .../hec-assembler-tools/linker/instructions/minst/mload.py | 4 ++-- .../linker/steps/program_linker_utils.py | 7 ++++--- .../tests/integration_tests/test_he_link.py | 2 +- 9 files changed, 12 insertions(+), 19 deletions(-) diff --git a/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py b/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py index e3916d95..af1c51e4 100644 --- a/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py +++ b/assembler_tools/hec-assembler-tools/assembler/instructions/instruction.py @@ -303,10 +303,6 @@ def latency(self) -> int: Returns: int: The latency. - - Note: - Accessing `latency` as a property on the class (e.g., `MyInst.latency`) returns a property object, - not an integer. Use an instance (e.g., `my_inst.latency`) or the class variable `_OP_DEFAULT_LATENCY`. """ return self.__latency diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py index d81fc9b6..3b44414b 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bload.py @@ -78,8 +78,7 @@ def var_name(self, value: str): @property def spad_address(self) -> int: """ - @brief Name of the source. - Spad address when there is HBM. + @brief Source SPAD address. """ return int(self.tokens[3]) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py index 65fd0a5f..a6c3fcc4 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/bones.py @@ -75,8 +75,7 @@ def var_name(self, value: str): @property def spad_address(self) -> int: """ - @brief Name of the source. - Spad address when there is HBM. + @brief Source SPAD address. """ return int(self.tokens[2]) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py index 74ccbb8f..17de149b 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cload.py @@ -70,8 +70,7 @@ def var_name(self, value: str): @property def spad_address(self) -> int: """ - @brief Name of the source. - SPAD address when loaded and there is HBM. + @brief Source SPAD address. """ return int(self.tokens[3]) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py index 7be339f2..ac8862f0 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/cstore.py @@ -75,7 +75,7 @@ def var_name(self, value: str): @property def spad_address(self) -> int: """ - @brief Name of the destination. + @brief SPAD address of destination. Should be set to HBM address to write back. @return The destination variable address. diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py index 596100a4..44ef21ac 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/cinst/nload.py @@ -76,8 +76,7 @@ def var_name(self, value: str): @property def spad_address(self) -> int: """ - @brief Name of the source. - SPAD address when loaded and there is HBM. + @brief Source SPAD address. """ return int(self.tokens[3]) diff --git a/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py b/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py index 592b3bb3..6b0a01a6 100644 --- a/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py +++ b/assembler_tools/hec-assembler-tools/linker/instructions/minst/mload.py @@ -75,11 +75,11 @@ def var_name(self, value: str): @property def hbm_address(self) -> int: """ - @brief Gets the name of the source. + @brief Source HBM address. Should be set to HBM address to write back. - @return The name of the source. + @return The HBM source. """ return int(self.tokens[3]) diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py index 0a80b428..88eb8c43 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker_utils.py @@ -52,11 +52,12 @@ def process_bload_instructions(kernel_cinstrs, kernel_cinstrs_map, cinst_in_var_ def remove_csyncm(kernel_cinstrs, kernel_cinstrs_map, idx): """ - @brief Remove CSyncm instruction for intermediate variables. + @brief Remove instruction at target idx if that is a CSyncm. @param kernel_cinstrs List of CInstructions. @param kernel_cinstrs_map Map of CInstructions with actions. - @param direction Direction to look for CSyncm ("next" or "prev"). + @param idx Index of the instruction to check. + @return tuple (adjust_idx, adjust_cycles) Adjustments for index and cycles. """ adjust_idx = 0 @@ -100,7 +101,7 @@ def search_minstrs_back(minstrs_map: list, idx: int, spad_address: int) -> int: def search_minstrs_forward(minstrs_map: list, idx: int, spad_address: int) -> int: """ - @brief Searches for an MStore based on its SPAD address + @brief Searches for an MStore/MLoad based on its SPAD address This method is used to find the instruction associated with a given SPAD address in the MInsts of a kernel. diff --git a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py index 886acdce..b87d5d52 100644 --- a/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py +++ b/assembler_tools/hec-assembler-tools/tests/integration_tests/test_he_link.py @@ -19,7 +19,7 @@ from linker.linker_run_config import LinkerRunConfig -class TestHeIntegration: +class TestHeLinkIntegration: """ @class TestHeIntegration @brief Integration tests for the he_link module From 857780ee5907879757794b54a3711e12f849e043 Mon Sep 17 00:00:00 2001 From: "Rojas Chaves, Jose" Date: Fri, 22 Aug 2025 20:24:47 +0000 Subject: [PATCH 12/12] Remapping vars in xinst comments --- .../linker/kern_trace/kern_remap.py | 23 ++++++++++++++++++- .../linker/steps/program_linker.py | 1 + 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py b/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py index 07fbeaba..e1b06a68 100644 --- a/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py +++ b/assembler_tools/hec-assembler-tools/linker/kern_trace/kern_remap.py @@ -8,10 +8,11 @@ import re -from linker.instructions import cinst, minst +from linker.instructions import cinst, minst, xinst from linker.instructions.cinst.cinstruction import CInstruction from linker.instructions.dinst.dinstruction import DInstruction from linker.instructions.minst.minstruction import MInstruction +from linker.instructions.xinst.xinstruction import XInstruction from linker.kern_trace.kernel_op import KernelOp @@ -97,3 +98,23 @@ def remap_m_c_instrs_vars(kernel_instrs: list, hbm_remap_dict: dict[str, str]) - else: for key, value in hbm_remap_dict.items(): instr.comment = instr.comment.replace(key, value) + + +def remap_xinstrs_vars(kernel_xinstrs: list, hbm_remap_dict: dict[str, str]) -> None: + """ + @brief Remaps variable names in X Instructions based on a provided remap dictionary. + + This function updates the variable names in each X Instruction by replacing them + with their corresponding values from the remap dictionary. + + @param kernel_xinstrs: List of X Instruction objects to process + @param hbm_remap_dict: Dictionary mapping old variable names to new variable names + """ + if hbm_remap_dict: + for instr in kernel_xinstrs: + if not isinstance(instr, XInstruction): + raise TypeError(f"Item {instr} is not a valid X Instruction.") + + if isinstance(instr, (xinst.Move, xinst.XStore)): + for key, value in hbm_remap_dict.items(): + instr.comment = instr.comment.replace(key, value) diff --git a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py index f988b52d..be262a29 100644 --- a/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py +++ b/assembler_tools/hec-assembler-tools/linker/steps/program_linker.py @@ -834,6 +834,7 @@ def link_kernels_to_files( self.prune_cinst_kernel_hbm(kernel) kernel.xinstrs = Loader.load_xinst_kernel_from_file(kernel.xinst) + kern_mapper.remap_xinstrs_vars(kernel.xinstrs, kernel.hbm_remap_dict) self.link_kernel(kernel)