From cd6a217c7b68658ce2d521d5d47ef547cfeba43b Mon Sep 17 00:00:00 2001 From: Mark Harfouche Date: Fri, 18 Jan 2019 16:40:09 -0500 Subject: [PATCH 1/2] change how clog2s is defined, remove function definition of clog2 --- fpga/riffa_hdl/functions.vh | 35 ++++------------------------------- 1 file changed, 4 insertions(+), 31 deletions(-) diff --git a/fpga/riffa_hdl/functions.vh b/fpga/riffa_hdl/functions.vh index 4a578a4..d1130d1 100644 --- a/fpga/riffa_hdl/functions.vh +++ b/fpga/riffa_hdl/functions.vh @@ -41,36 +41,9 @@ //----------------------------------------------------------------------------- `ifndef __FUNCTIONS_VH `define __FUNCTIONS_VH 1 -function integer clog2; - input [31:0] v; - reg [31:0] value; - begin - value = v; - if (value == 1) begin - clog2 = 0; - end - else begin - value = value-1; - for (clog2=0; value>0; clog2=clog2+1) - value = value>>1; - end - end -endfunction -// clog2s -- calculate the ceiling log2 value, min return is 1 (safe). -function integer clog2s; - input [31:0] v; - reg [31:0] value; - begin - value = v; - if (value == 1) begin - clog2s = 1; - end - else begin - value = value-1; - for (clog2s=0; value>0; clog2s=clog2s+1) - value = value>>1; - end - end -endfunction +// `clog2s -- calculate the ceiling log2 value, min return is 1 (safe). +// adapted from +// https://stackoverflow.com/questions/5269634/address-width-from-ram-depth +`define clog2s(x) ($clog2(x) ? $clog2(x) : 1) `endif From 1a5dcb50204fedd07612be21fb7051a8275c7679 Mon Sep 17 00:00:00 2001 From: Mark Harfouche Date: Fri, 18 Jan 2019 16:40:36 -0500 Subject: [PATCH 2/2] blanket replace clog2s by the macro. blanket replace clog2 by $clog2 --- fpga/altera/de2i/riffa_wrapper_de2i.v | 89 +++-- fpga/altera/de4/riffa_wrapper_de4.v | 89 +++-- fpga/altera/de5/riffa_wrapper_de5.v | 56 +-- fpga/riffa_hdl/async_fifo.v | 6 +- fpga/riffa_hdl/async_fifo_fwft.v | 6 +- fpga/riffa_hdl/channel.v | 2 +- fpga/riffa_hdl/channel_128.v | 2 +- fpga/riffa_hdl/channel_32.v | 2 +- fpga/riffa_hdl/channel_64.v | 2 +- fpga/riffa_hdl/counter.v | 8 +- fpga/riffa_hdl/demux.v | 2 +- fpga/riffa_hdl/engine_layer.v | 52 +-- fpga/riffa_hdl/fifo.v | 4 +- fpga/riffa_hdl/offset_flag_to_one_hot.v | 2 +- fpga/riffa_hdl/offset_to_mask.v | 4 +- fpga/riffa_hdl/ram_1clk_1w_1r.v | 6 +- fpga/riffa_hdl/ram_2clk_1w_1r.v | 6 +- fpga/riffa_hdl/registers.v | 24 +- fpga/riffa_hdl/reorder_queue.v | 14 +- fpga/riffa_hdl/reorder_queue_input.v | 8 +- fpga/riffa_hdl/reorder_queue_output.v | 4 +- fpga/riffa_hdl/reset_controller.v | 2 +- fpga/riffa_hdl/reset_extender.v | 2 +- fpga/riffa_hdl/riffa.v | 44 +-- fpga/riffa_hdl/rotate.v | 12 +- fpga/riffa_hdl/rx_engine_classic.v | 24 +- fpga/riffa_hdl/rx_engine_ultrascale.v | 16 +- fpga/riffa_hdl/rx_port_128.v | 6 +- fpga/riffa_hdl/rx_port_32.v | 6 +- fpga/riffa_hdl/rx_port_64.v | 6 +- fpga/riffa_hdl/rx_port_reader.v | 2 +- fpga/riffa_hdl/rxc_engine_128.v | 12 +- fpga/riffa_hdl/rxc_engine_classic.v | 14 +- fpga/riffa_hdl/rxc_engine_ultrascale.v | 16 +- fpga/riffa_hdl/rxr_engine_128.v | 12 +- fpga/riffa_hdl/rxr_engine_classic.v | 8 +- fpga/riffa_hdl/rxr_engine_ultrascale.v | 6 +- fpga/riffa_hdl/scsdpram.v | 4 +- fpga/riffa_hdl/sg_list_requester.v | 2 +- fpga/riffa_hdl/sync_fifo.v | 6 +- fpga/riffa_hdl/translation_altera.v | 2 +- fpga/riffa_hdl/translation_xilinx.v | 12 +- fpga/riffa_hdl/trellis.vh | 3 +- fpga/riffa_hdl/tx_alignment_pipeline.v | 24 +- fpga/riffa_hdl/tx_data_fifo.v | 14 +- fpga/riffa_hdl/tx_data_pipeline.v | 8 +- fpga/riffa_hdl/tx_data_shift.v | 51 ++- fpga/riffa_hdl/tx_engine.v | 20 +- fpga/riffa_hdl/tx_engine_classic.v | 102 +++--- fpga/riffa_hdl/tx_engine_ultrascale.v | 16 +- fpga/riffa_hdl/tx_multiplexer.v | 16 +- fpga/riffa_hdl/tx_multiplexer_128.v | 4 +- fpga/riffa_hdl/tx_multiplexer_32.v | 4 +- fpga/riffa_hdl/tx_multiplexer_64.v | 4 +- fpga/riffa_hdl/tx_port_128.v | 2 +- fpga/riffa_hdl/tx_port_32.v | 2 +- fpga/riffa_hdl/tx_port_64.v | 2 +- fpga/riffa_hdl/tx_port_buffer_128.v | 2 +- fpga/riffa_hdl/tx_port_buffer_32.v | 2 +- fpga/riffa_hdl/tx_port_buffer_64.v | 2 +- fpga/riffa_hdl/tx_port_monitor_128.v | 2 +- fpga/riffa_hdl/tx_port_monitor_32.v | 2 +- fpga/riffa_hdl/tx_port_monitor_64.v | 2 +- fpga/riffa_hdl/txc_engine_classic.v | 16 +- fpga/riffa_hdl/txc_engine_ultrascale.v | 28 +- fpga/riffa_hdl/txr_engine_classic.v | 16 +- fpga/riffa_hdl/txr_engine_ultrascale.v | 28 +- fpga/xilinx/NetFPGA/riffa_wrapper_NetFPGA.v | 48 +-- fpga/xilinx/ac701/riffa_wrapper_ac701.v | 56 +-- fpga/xilinx/adm7V3/riffa_wrapper_adm7V3.v | 48 +-- fpga/xilinx/kc705/riffa_wrapper_kc705.v | 56 +-- fpga/xilinx/vc707/riffa_wrapper_vc707.v | 56 +-- fpga/xilinx/vc709/riffa_wrapper_vc709.v | 48 +-- .../prj/ZC706_Gen2x4If128.xpr | 321 +++++++++++------- fpga/xilinx/zc706/riffa_wrapper_zc706.v | 56 +-- 75 files changed, 873 insertions(+), 790 deletions(-) diff --git a/fpga/altera/de2i/riffa_wrapper_de2i.v b/fpga/altera/de2i/riffa_wrapper_de2i.v index 9970fde..148f71a 100644 --- a/fpga/altera/de2i/riffa_wrapper_de2i.v +++ b/fpga/altera/de2i/riffa_wrapper_de2i.v @@ -1,24 +1,24 @@ // ---------------------------------------------------------------------- // Copyright (c) 2016, The Regents of the University of California All // rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: -// +// // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. -// +// // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -52,8 +52,8 @@ module riffa_wrapper_de2i parameter C_PCI_DATA_WIDTH = 64, parameter C_MAX_PAYLOAD_BYTES = 256, parameter C_LOG_NUM_TAGS = 5, - parameter C_FPGA_ID = "DE2i") - (// Interface: Altera RX + parameter C_FPGA_ID = "DE2i") + (// Interface: Altera RX input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA, input [0:0] RX_ST_EOP, input [0:0] RX_ST_SOP, @@ -77,7 +77,7 @@ module riffa_wrapper_de2i // Interface: Altera Flow Control input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER, input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA, - + // Interface: Altera Interrupt input APP_MSI_ACK, output APP_MSI_REQ, @@ -85,7 +85,7 @@ module riffa_wrapper_de2i // Interface: Altera CLK/RESET input PLD_CLK, input RESET_STATUS, - + // RIFFA Interface Signals output RST_OUT, input [C_NUM_CHNL-1:0] CHNL_RX_CLK, // Channel read clock @@ -107,7 +107,7 @@ module riffa_wrapper_de2i input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved - + localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2; localparam C_VENDOR = "ALTERA"; @@ -129,10 +129,10 @@ module riffa_wrapper_de2i wire rxc_data_valid; wire rxc_data_start_flag; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; wire [`SIG_TAG_W-1:0] rxc_meta_tag; wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; @@ -147,10 +147,10 @@ module riffa_wrapper_de2i wire rxr_data_valid; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; wire [`SIG_TC_W-1:0] rxr_meta_tc; wire [`SIG_ATTR_W-1:0] rxr_meta_attr; @@ -161,14 +161,14 @@ module riffa_wrapper_de2i wire [`SIG_REQID_W-1:0] rxr_meta_requester_id; wire [`SIG_LEN_W-1:0] rxr_meta_length; wire rxr_meta_ep; - + // interface: TXC Engine wire txc_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txc_data; wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; wire txc_data_ready; wire txc_meta_valid; @@ -190,13 +190,13 @@ module riffa_wrapper_de2i wire txr_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txr_data; wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; wire txr_data_ready; wire txr_meta_valid; - wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; + wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; wire [`SIG_LBE_W-1:0] txr_meta_ldwbe; wire [`SIG_ADDR_W-1:0] txr_meta_addr; wire [`SIG_LEN_W-1:0] txr_meta_length; @@ -217,7 +217,7 @@ module riffa_wrapper_de2i wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset; wire rx_tlp_valid; wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode; - + wire tx_tlp_ready; wire [C_PCI_DATA_WIDTH-1:0] tx_tlp; wire tx_tlp_end_flag; @@ -225,7 +225,7 @@ module riffa_wrapper_de2i wire tx_tlp_start_flag; wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset; wire tx_tlp_valid; - + // Unconnected Wires (Used in ultrascale interface) // Interface: RQ (TXC) wire s_axis_rq_tlast_nc; @@ -286,9 +286,9 @@ module riffa_wrapper_de2i .RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]), .RX_TLP_VALID (rx_tlp_valid), .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_START_OFFSET (rx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_END_OFFSET (rx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]), .TX_TLP_READY (tx_tlp_ready), .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), @@ -309,9 +309,9 @@ module riffa_wrapper_de2i .TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]), .TX_TLP_VALID (tx_tlp_valid), .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_START_OFFSET (tx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_END_OFFSET (tx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .INTR_MSI_REQUEST (intr_msi_request), /*AUTOINST*/ // Outputs @@ -352,10 +352,10 @@ module riffa_wrapper_de2i .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), @@ -369,9 +369,9 @@ module riffa_wrapper_de2i .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -411,9 +411,9 @@ module riffa_wrapper_de2i .TXC_DATA_VALID (txc_data_valid), .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -430,9 +430,9 @@ module riffa_wrapper_de2i .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -501,9 +501,9 @@ module riffa_wrapper_de2i .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_VALID (txc_data_valid), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -520,9 +520,9 @@ module riffa_wrapper_de2i .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -540,10 +540,10 @@ module riffa_wrapper_de2i .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -559,10 +559,10 @@ module riffa_wrapper_de2i .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), @@ -575,7 +575,7 @@ module riffa_wrapper_de2i .TXC_DATA_READY (txc_data_ready), .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), + .TXC_SENT (txc_sent), .TXR_DATA_READY (txr_data_ready), .TXR_META_READY (txr_meta_ready), @@ -591,7 +591,7 @@ module riffa_wrapper_de2i .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - + .INTR_MSI_RDY (intr_msi_rdy), .DONE_TXC_RST (done_txc_rst), @@ -624,4 +624,3 @@ endmodule // Local Variables: // verilog-library-directories:("../../riffa_hdl/") // End: - diff --git a/fpga/altera/de4/riffa_wrapper_de4.v b/fpga/altera/de4/riffa_wrapper_de4.v index 74f08f6..f1a06c0 100644 --- a/fpga/altera/de4/riffa_wrapper_de4.v +++ b/fpga/altera/de4/riffa_wrapper_de4.v @@ -1,24 +1,24 @@ // ---------------------------------------------------------------------- // Copyright (c) 2016, The Regents of the University of California All // rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: -// +// // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. -// +// // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -52,8 +52,8 @@ module riffa_wrapper_de4 parameter C_PCI_DATA_WIDTH = 128, parameter C_MAX_PAYLOAD_BYTES = 256, parameter C_LOG_NUM_TAGS = 5, - parameter C_FPGA_ID = "ADE4") - (// Interface: Altera RX + parameter C_FPGA_ID = "ADE4") + (// Interface: Altera RX input [C_PCI_DATA_WIDTH-1:0] RX_ST_DATA, input [0:0] RX_ST_EOP, input [0:0] RX_ST_SOP, @@ -77,7 +77,7 @@ module riffa_wrapper_de4 // Interface: Altera Flow Control input [`SIG_KO_CPLH_W-1:0] KO_CPL_SPC_HEADER, input [`SIG_KO_CPLD_W-1:0] KO_CPL_SPC_DATA, - + // Interface: Altera Interrupt input APP_MSI_ACK, output APP_MSI_REQ, @@ -85,7 +85,7 @@ module riffa_wrapper_de4 // Interface: Altera CLK/RESET input PLD_CLK, input RESET_STATUS, - + // RIFFA Interface Signals output RST_OUT, @@ -108,7 +108,7 @@ module riffa_wrapper_de4 input [(C_NUM_CHNL*C_PCI_DATA_WIDTH)-1:0] CHNL_TX_DATA, // Channel write data input [C_NUM_CHNL-1:0] CHNL_TX_DATA_VALID, // Channel write data valid output [C_NUM_CHNL-1:0] CHNL_TX_DATA_REN); // Channel write data has been recieved - + localparam C_FPGA_NAME = "REGT"; // This is not yet exposed in the driver localparam C_MAX_READ_REQ_BYTES = C_MAX_PAYLOAD_BYTES * 2; localparam C_VENDOR = "ALTERA"; @@ -131,10 +131,10 @@ module riffa_wrapper_de4 wire rxc_data_valid; wire rxc_data_start_flag; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; wire [`SIG_TAG_W-1:0] rxc_meta_tag; wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; @@ -149,10 +149,10 @@ module riffa_wrapper_de4 wire rxr_data_valid; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; wire [`SIG_TC_W-1:0] rxr_meta_tc; wire [`SIG_ATTR_W-1:0] rxr_meta_attr; @@ -163,14 +163,14 @@ module riffa_wrapper_de4 wire [`SIG_REQID_W-1:0] rxr_meta_requester_id; wire [`SIG_LEN_W-1:0] rxr_meta_length; wire rxr_meta_ep; - + // interface: TXC Engine wire txc_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txc_data; wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; wire txc_data_ready; wire txc_meta_valid; @@ -192,13 +192,13 @@ module riffa_wrapper_de4 wire txr_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txr_data; wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; wire txr_data_ready; wire txr_meta_valid; - wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; + wire [`SIG_FBE_W-1:0] txr_meta_fdwbe; wire [`SIG_LBE_W-1:0] txr_meta_ldwbe; wire [`SIG_ADDR_W-1:0] txr_meta_addr; wire [`SIG_LEN_W-1:0] txr_meta_length; @@ -219,7 +219,7 @@ module riffa_wrapper_de4 wire [`SIG_OFFSET_W-1:0] rx_tlp_start_offset; wire rx_tlp_valid; wire [`SIG_BARDECODE_W-1:0] rx_tlp_bar_decode; - + wire tx_tlp_ready; wire [C_PCI_DATA_WIDTH-1:0] tx_tlp; wire tx_tlp_end_flag; @@ -227,7 +227,7 @@ module riffa_wrapper_de4 wire tx_tlp_start_flag; wire [`SIG_OFFSET_W-1:0] tx_tlp_start_offset; wire tx_tlp_valid; - + // Unconnected Wires (Used in ultrascale interface) // Interface: RQ (TXC) wire s_axis_rq_tlast_nc; @@ -288,9 +288,9 @@ module riffa_wrapper_de4 .RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]), .RX_TLP_VALID (rx_tlp_valid), .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_START_OFFSET (rx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_END_OFFSET (rx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]), .TX_TLP_READY (tx_tlp_ready), .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), @@ -311,9 +311,9 @@ module riffa_wrapper_de4 .TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]), .TX_TLP_VALID (tx_tlp_valid), .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_START_OFFSET (tx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_END_OFFSET (tx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .INTR_MSI_REQUEST (intr_msi_request), /*AUTOINST*/ // Outputs @@ -354,10 +354,10 @@ module riffa_wrapper_de4 .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), @@ -371,9 +371,9 @@ module riffa_wrapper_de4 .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -412,9 +412,9 @@ module riffa_wrapper_de4 .TXC_DATA_VALID (txc_data_valid), .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -431,9 +431,9 @@ module riffa_wrapper_de4 .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -502,9 +502,9 @@ module riffa_wrapper_de4 .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_VALID (txc_data_valid), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -521,9 +521,9 @@ module riffa_wrapper_de4 .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -541,10 +541,10 @@ module riffa_wrapper_de4 .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -560,10 +560,10 @@ module riffa_wrapper_de4 .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), @@ -576,7 +576,7 @@ module riffa_wrapper_de4 .TXC_DATA_READY (txc_data_ready), .TXC_META_READY (txc_meta_ready), - .TXC_SENT (txc_sent), + .TXC_SENT (txc_sent), .TXR_DATA_READY (txr_data_ready), .TXR_META_READY (txr_meta_ready), @@ -592,7 +592,7 @@ module riffa_wrapper_de4 .CONFIG_CPL_BOUNDARY_SEL (config_cpl_boundary_sel), .CONFIG_MAX_CPL_DATA (config_max_cpl_data[`SIG_FC_CPLD_W-1:0]), .CONFIG_MAX_CPL_HDR (config_max_cpl_hdr[`SIG_FC_CPLH_W-1:0]), - + .INTR_MSI_RDY (intr_msi_rdy), .DONE_TXC_RST (done_txc_rst), @@ -625,4 +625,3 @@ endmodule // Local Variables: // verilog-library-directories:("../../riffa_hdl/") // End: - diff --git a/fpga/altera/de5/riffa_wrapper_de5.v b/fpga/altera/de5/riffa_wrapper_de5.v index 4949c61..94ac325 100644 --- a/fpga/altera/de5/riffa_wrapper_de5.v +++ b/fpga/altera/de5/riffa_wrapper_de5.v @@ -131,10 +131,10 @@ module riffa_wrapper_de5 wire rxc_data_valid; wire rxc_data_start_flag; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; wire [`SIG_TAG_W-1:0] rxc_meta_tag; wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; @@ -149,10 +149,10 @@ module riffa_wrapper_de5 wire rxr_data_valid; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; wire [`SIG_TC_W-1:0] rxr_meta_tc; wire [`SIG_ATTR_W-1:0] rxr_meta_attr; @@ -168,9 +168,9 @@ module riffa_wrapper_de5 wire txc_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txc_data; wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; wire txc_data_ready; wire txc_meta_valid; @@ -192,9 +192,9 @@ module riffa_wrapper_de5 wire txr_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txr_data; wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; wire txr_data_ready; wire txr_meta_valid; @@ -288,9 +288,9 @@ module riffa_wrapper_de5 .RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]), .RX_TLP_VALID (rx_tlp_valid), .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_START_OFFSET (rx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_END_OFFSET (rx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]), .TX_TLP_READY (tx_tlp_ready), .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), @@ -311,9 +311,9 @@ module riffa_wrapper_de5 .TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]), .TX_TLP_VALID (tx_tlp_valid), .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_START_OFFSET (tx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_END_OFFSET (tx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .INTR_MSI_REQUEST (intr_msi_request), /*AUTOINST*/ // Outputs @@ -354,10 +354,10 @@ module riffa_wrapper_de5 .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), @@ -371,9 +371,9 @@ module riffa_wrapper_de5 .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -412,9 +412,9 @@ module riffa_wrapper_de5 .TXC_DATA_VALID (txc_data_valid), .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -431,9 +431,9 @@ module riffa_wrapper_de5 .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -502,9 +502,9 @@ module riffa_wrapper_de5 .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_VALID (txc_data_valid), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -521,9 +521,9 @@ module riffa_wrapper_de5 .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -541,10 +541,10 @@ module riffa_wrapper_de5 .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -560,10 +560,10 @@ module riffa_wrapper_de5 .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), diff --git a/fpga/riffa_hdl/async_fifo.v b/fpga/riffa_hdl/async_fifo.v index 845dd77..e02eadf 100644 --- a/fpga/riffa_hdl/async_fifo.v +++ b/fpga/riffa_hdl/async_fifo.v @@ -52,9 +52,9 @@ module async_fifo #( parameter C_WIDTH = 32, // Data bus width parameter C_DEPTH = 1024, // Depth of the FIFO // Local parameters - parameter C_REAL_DEPTH = 2**clog2(C_DEPTH), - parameter C_DEPTH_BITS = clog2(C_REAL_DEPTH), - parameter C_DEPTH_P1_BITS = clog2(C_REAL_DEPTH+1) + parameter C_REAL_DEPTH = 2**$clog2(C_DEPTH), + parameter C_DEPTH_BITS = $clog2(C_REAL_DEPTH), + parameter C_DEPTH_P1_BITS = $clog2(C_REAL_DEPTH+1) ) ( input RD_CLK, // Read clock diff --git a/fpga/riffa_hdl/async_fifo_fwft.v b/fpga/riffa_hdl/async_fifo_fwft.v index c5d61a6..3345bfb 100644 --- a/fpga/riffa_hdl/async_fifo_fwft.v +++ b/fpga/riffa_hdl/async_fifo_fwft.v @@ -49,9 +49,9 @@ module async_fifo_fwft #( parameter C_WIDTH = 32, // Data bus width parameter C_DEPTH = 1024, // Depth of the FIFO // Local parameters - parameter C_REAL_DEPTH = 2**clog2(C_DEPTH), - parameter C_DEPTH_BITS = clog2s(C_REAL_DEPTH), - parameter C_DEPTH_P1_BITS = clog2s(C_REAL_DEPTH+1) + parameter C_REAL_DEPTH = 2**$clog2(C_DEPTH), + parameter C_DEPTH_BITS = `clog2s(C_REAL_DEPTH), + parameter C_DEPTH_P1_BITS = `clog2s(C_REAL_DEPTH+1) ) ( input RD_CLK, // Read clock diff --git a/fpga/riffa_hdl/channel.v b/fpga/riffa_hdl/channel.v index c139af2..3585217 100644 --- a/fpga/riffa_hdl/channel.v +++ b/fpga/riffa_hdl/channel.v @@ -37,7 +37,7 @@ module channel #( parameter C_DATA_WIDTH = 128, parameter C_MAX_READ_REQ = 2, // Max read: 000=128B, 001=256B, 010=512B, 011=1024B, 100=2048B, 101=4096B - parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1) + parameter C_DATA_WORD_WIDTH = $clog2((C_DATA_WIDTH/32)+1) ) ( input CLK, diff --git a/fpga/riffa_hdl/channel_128.v b/fpga/riffa_hdl/channel_128.v index 71edd14..db5302f 100644 --- a/fpga/riffa_hdl/channel_128.v +++ b/fpga/riffa_hdl/channel_128.v @@ -49,7 +49,7 @@ module channel_128 #( parameter C_RX_FIFO_DEPTH = 1024, parameter C_TX_FIFO_DEPTH = 512, parameter C_SG_FIFO_DEPTH = 1024, - parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1) + parameter C_DATA_WORD_WIDTH = $clog2((C_DATA_WIDTH/32)+1) ) ( input CLK, diff --git a/fpga/riffa_hdl/channel_32.v b/fpga/riffa_hdl/channel_32.v index 1aa6894..ddd0e9a 100644 --- a/fpga/riffa_hdl/channel_32.v +++ b/fpga/riffa_hdl/channel_32.v @@ -49,7 +49,7 @@ module channel_32 #( parameter C_RX_FIFO_DEPTH = 1024, parameter C_TX_FIFO_DEPTH = 512, parameter C_SG_FIFO_DEPTH = 1024, - parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1) + parameter C_DATA_WORD_WIDTH = $clog2((C_DATA_WIDTH/32)+1) ) ( input CLK, diff --git a/fpga/riffa_hdl/channel_64.v b/fpga/riffa_hdl/channel_64.v index a0dc7f2..e921b74 100644 --- a/fpga/riffa_hdl/channel_64.v +++ b/fpga/riffa_hdl/channel_64.v @@ -49,7 +49,7 @@ module channel_64 #( parameter C_RX_FIFO_DEPTH = 1024, parameter C_TX_FIFO_DEPTH = 512, parameter C_SG_FIFO_DEPTH = 1024, - parameter C_DATA_WORD_WIDTH = clog2((C_DATA_WIDTH/32)+1) + parameter C_DATA_WORD_WIDTH = $clog2((C_DATA_WIDTH/32)+1) ) ( input CLK, diff --git a/fpga/riffa_hdl/counter.v b/fpga/riffa_hdl/counter.v index 3b57b96..5e83c28 100644 --- a/fpga/riffa_hdl/counter.v +++ b/fpga/riffa_hdl/counter.v @@ -53,18 +53,18 @@ module counter input RST_IN, input ENABLE, - output [clog2s(C_MAX_VALUE+1)-1:0] VALUE + output [`clog2s(C_MAX_VALUE+1)-1:0] VALUE ); wire wEnable; - reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue; - reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue; + reg [`clog2s(C_MAX_VALUE+1)-1:0] wCtrValue; + reg [`clog2s(C_MAX_VALUE+1)-1:0] rCtrValue; /* verilator lint_off WIDTH */ assign wEnable = ENABLE & (C_SAT_VALUE > rCtrValue); /* verilator lint_on WIDTH */ assign VALUE = rCtrValue; always @(posedge CLK) begin if(RST_IN) begin - rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0]; + rCtrValue <= C_RST_VALUE[`clog2s(C_MAX_VALUE+1)-1:0]; end else if(wEnable) begin rCtrValue <= rCtrValue + 1; end diff --git a/fpga/riffa_hdl/demux.v b/fpga/riffa_hdl/demux.v index 6b926fc..0a51f12 100644 --- a/fpga/riffa_hdl/demux.v +++ b/fpga/riffa_hdl/demux.v @@ -48,7 +48,7 @@ module demux ) ( input [C_WIDTH-1:0] WR_DATA,// Inputs - input [clog2s(C_OUTPUTS)-1:0] WR_SEL,// Selector + input [`clog2s(C_OUTPUTS)-1:0] WR_SEL,// Selector output [C_OUTPUTS*C_WIDTH-1:0] RD_DATA// Outputs ); genvar i; diff --git a/fpga/riffa_hdl/engine_layer.v b/fpga/riffa_hdl/engine_layer.v index f7191d3..2eae9ee 100644 --- a/fpga/riffa_hdl/engine_layer.v +++ b/fpga/riffa_hdl/engine_layer.v @@ -119,9 +119,9 @@ module engine_layer output RXC_DATA_VALID, output [(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_WORD_ENABLE, output RXC_DATA_START_FLAG, - output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET, + output [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_START_OFFSET, output RXC_DATA_END_FLAG, - output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET, + output [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXC_DATA_END_OFFSET, output [`SIG_LBE_W-1:0] RXC_META_LDWBE, output [`SIG_FBE_W-1:0] RXC_META_FDWBE, @@ -138,9 +138,9 @@ module engine_layer output RXR_DATA_VALID, output [(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_WORD_ENABLE, output RXR_DATA_START_FLAG, - output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET, + output [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET, output RXR_DATA_END_FLAG, - output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET, + output [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET, output [`SIG_FBE_W-1:0] RXR_META_FDWBE, output [`SIG_LBE_W-1:0] RXR_META_LDWBE, @@ -158,9 +158,9 @@ module engine_layer input TXC_DATA_VALID, input [C_PCI_DATA_WIDTH-1:0] TXC_DATA, input TXC_DATA_START_FLAG, - input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET, + input [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET, input TXC_DATA_END_FLAG, - input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET, + input [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET, output TXC_DATA_READY, input TXC_META_VALID, @@ -182,9 +182,9 @@ module engine_layer input TXR_DATA_VALID, input [C_PCI_DATA_WIDTH-1:0] TXR_DATA, input TXR_DATA_START_FLAG, - input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET, + input [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_START_OFFSET, input TXR_DATA_END_FLAG, - input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET, + input [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXR_DATA_END_OFFSET, output TXR_DATA_READY, input TXR_META_VALID, @@ -238,9 +238,9 @@ module engine_layer .RXC_DATA_VALID (RXC_DATA_VALID), .RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_START_FLAG (RXC_DATA_START_FLAG), - .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_END_FLAG (RXC_DATA_END_FLAG), - .RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]), .RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]), .RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]), @@ -254,9 +254,9 @@ module engine_layer .RXR_DATA_VALID (RXR_DATA_VALID), .RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_START_FLAG (RXR_DATA_START_FLAG), - .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (RXR_DATA_END_FLAG), - .RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]), .RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]), @@ -296,9 +296,9 @@ module engine_layer .TX_TLP (TX_TLP[C_PCI_DATA_WIDTH-1:0]), .TX_TLP_VALID (TX_TLP_VALID), .TX_TLP_START_FLAG (TX_TLP_START_FLAG), - .TX_TLP_START_OFFSET (TX_TLP_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_START_OFFSET (TX_TLP_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_END_FLAG (TX_TLP_END_FLAG), - .TX_TLP_END_OFFSET (TX_TLP_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_END_OFFSET (TX_TLP_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_READY (TXC_DATA_READY), .TXC_META_READY (TXC_META_READY), .TXC_SENT (TXC_SENT), @@ -314,9 +314,9 @@ module engine_layer .TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_START_FLAG (TXC_DATA_START_FLAG), - .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (TXC_DATA_END_FLAG), - .TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (TXC_META_VALID), .TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]), @@ -332,9 +332,9 @@ module engine_layer .TXR_DATA_VALID (TXR_DATA_VALID), .TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (TXR_DATA_START_FLAG), - .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (TXR_DATA_END_FLAG), - .TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (TXR_META_VALID), .TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]), @@ -370,9 +370,9 @@ module engine_layer .RXC_DATA_VALID (RXC_DATA_VALID), .RXC_DATA_WORD_ENABLE (RXC_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_START_FLAG (RXC_DATA_START_FLAG), - .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (RXC_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_END_FLAG (RXC_DATA_END_FLAG), - .RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (RXC_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_LDWBE (RXC_META_LDWBE[`SIG_LBE_W-1:0]), .RXC_META_FDWBE (RXC_META_FDWBE[`SIG_FBE_W-1:0]), .RXC_META_TAG (RXC_META_TAG[`SIG_TAG_W-1:0]), @@ -386,9 +386,9 @@ module engine_layer .RXR_DATA_VALID (RXR_DATA_VALID), .RXR_DATA_WORD_ENABLE (RXR_DATA_WORD_ENABLE[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_START_FLAG (RXR_DATA_START_FLAG), - .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (RXR_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (RXR_DATA_END_FLAG), - .RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (RXR_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (RXR_META_FDWBE[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (RXR_META_LDWBE[`SIG_LBE_W-1:0]), .RXR_META_TC (RXR_META_TC[`SIG_TC_W-1:0]), @@ -452,9 +452,9 @@ module engine_layer .TXC_DATA_VALID (TXC_DATA_VALID), .TXC_DATA (TXC_DATA[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_START_FLAG (TXC_DATA_START_FLAG), - .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (TXC_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (TXC_DATA_END_FLAG), - .TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (TXC_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (TXC_META_VALID), .TXC_META_FDWBE (TXC_META_FDWBE[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (TXC_META_LDWBE[`SIG_LBE_W-1:0]), @@ -471,9 +471,9 @@ module engine_layer .TXR_DATA_VALID (TXR_DATA_VALID), .TXR_DATA (TXR_DATA[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (TXR_DATA_START_FLAG), - .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (TXR_DATA_START_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (TXR_DATA_END_FLAG), - .TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (TXR_DATA_END_OFFSET[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (TXR_META_VALID), .TXR_META_FDWBE (TXR_META_FDWBE[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (TXR_META_LDWBE[`SIG_LBE_W-1:0]), diff --git a/fpga/riffa_hdl/fifo.v b/fpga/riffa_hdl/fifo.v index 6e2ca41..68ab024 100644 --- a/fpga/riffa_hdl/fifo.v +++ b/fpga/riffa_hdl/fifo.v @@ -62,8 +62,8 @@ module fifo ); // Local parameters - localparam C_POW2_DEPTH = 2**clog2(C_DEPTH); - localparam C_DEPTH_WIDTH = clog2s(C_POW2_DEPTH); + localparam C_POW2_DEPTH = 2**$clog2(C_DEPTH); + localparam C_DEPTH_WIDTH = `clog2s(C_POW2_DEPTH); wire [C_DELAY:0] wDelayTaps; wire wDelayWrEn; diff --git a/fpga/riffa_hdl/offset_flag_to_one_hot.v b/fpga/riffa_hdl/offset_flag_to_one_hot.v index cbfec8f..403ea44 100644 --- a/fpga/riffa_hdl/offset_flag_to_one_hot.v +++ b/fpga/riffa_hdl/offset_flag_to_one_hot.v @@ -47,7 +47,7 @@ module offset_flag_to_one_hot parameter C_WIDTH = 4 ) ( - input [clog2s(C_WIDTH)-1:0] WR_OFFSET, + input [`clog2s(C_WIDTH)-1:0] WR_OFFSET, input WR_FLAG, output [C_WIDTH-1:0] RD_ONE_HOT ); diff --git a/fpga/riffa_hdl/offset_to_mask.v b/fpga/riffa_hdl/offset_to_mask.v index 92ea908..29c9206 100644 --- a/fpga/riffa_hdl/offset_to_mask.v +++ b/fpga/riffa_hdl/offset_to_mask.v @@ -38,13 +38,13 @@ module offset_to_mask parameter C_MASK_WIDTH = 4) ( input OFFSET_ENABLE, - input [clog2s(C_MASK_WIDTH)-1:0] OFFSET, + input [`clog2s(C_MASK_WIDTH)-1:0] OFFSET, output [C_MASK_WIDTH-1:0] MASK ); reg [7:0] _rMask,_rMaskSwap; wire [3:0] wSelect; - assign wSelect = {OFFSET_ENABLE,{{(3-clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}}; + assign wSelect = {OFFSET_ENABLE,{{(3-`clog2s(C_MASK_WIDTH)){1'b0}},OFFSET}}; assign MASK = (C_MASK_SWAP)? _rMaskSwap[7 -: C_MASK_WIDTH]: _rMask[C_MASK_WIDTH-1:0]; always @(*) begin _rMask = 0; diff --git a/fpga/riffa_hdl/ram_1clk_1w_1r.v b/fpga/riffa_hdl/ram_1clk_1w_1r.v index ba98634..5023792 100644 --- a/fpga/riffa_hdl/ram_1clk_1w_1r.v +++ b/fpga/riffa_hdl/ram_1clk_1w_1r.v @@ -52,13 +52,13 @@ module ram_1clk_1w_1r ) ( input CLK, - input [clog2s(C_RAM_DEPTH)-1:0] ADDRA, + input [`clog2s(C_RAM_DEPTH)-1:0] ADDRA, input WEA, - input [clog2s(C_RAM_DEPTH)-1:0] ADDRB, + input [`clog2s(C_RAM_DEPTH)-1:0] ADDRB, input [C_RAM_WIDTH-1:0] DINA, output [C_RAM_WIDTH-1:0] DOUTB ); - localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH); + localparam C_RAM_ADDR_BITS = `clog2s(C_RAM_DEPTH); reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0]; reg [C_RAM_WIDTH-1:0] rDout; assign DOUTB = rDout; diff --git a/fpga/riffa_hdl/ram_2clk_1w_1r.v b/fpga/riffa_hdl/ram_2clk_1w_1r.v index 3126060..630e3fa 100644 --- a/fpga/riffa_hdl/ram_2clk_1w_1r.v +++ b/fpga/riffa_hdl/ram_2clk_1w_1r.v @@ -54,13 +54,13 @@ module ram_2clk_1w_1r input CLKA, input CLKB, input WEA, - input [clog2s(C_RAM_DEPTH)-1:0] ADDRA, - input [clog2s(C_RAM_DEPTH)-1:0] ADDRB, + input [`clog2s(C_RAM_DEPTH)-1:0] ADDRA, + input [`clog2s(C_RAM_DEPTH)-1:0] ADDRB, input [C_RAM_WIDTH-1:0] DINA, output [C_RAM_WIDTH-1:0] DOUTB ); //Local parameters - localparam C_RAM_ADDR_BITS = clog2s(C_RAM_DEPTH); + localparam C_RAM_ADDR_BITS = `clog2s(C_RAM_DEPTH); reg [C_RAM_WIDTH-1:0] rRAM [C_RAM_DEPTH-1:0]; reg [C_RAM_WIDTH-1:0] rDout; assign DOUTB = rDout; diff --git a/fpga/riffa_hdl/registers.v b/fpga/riffa_hdl/registers.v index ffa3d00..a6fab49 100644 --- a/fpga/riffa_hdl/registers.v +++ b/fpga/riffa_hdl/registers.v @@ -55,10 +55,10 @@ module registers input [C_PCI_DATA_WIDTH-1:0] RXR_DATA, input RXR_DATA_VALID, input RXR_DATA_START_FLAG, - input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET, + input [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_START_OFFSET, input [`SIG_FBE_W-1:0] RXR_META_FDWBE, input RXR_DATA_END_FLAG, - input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET, + input [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] RXR_DATA_END_OFFSET, input [`SIG_LBE_W-1:0] RXR_META_LDWBE, input [`SIG_TC_W-1:0] RXR_META_TC, input [`SIG_ATTR_W-1:0] RXR_META_ATTR, @@ -73,9 +73,9 @@ module registers output TXC_DATA_VALID, output [C_PCI_DATA_WIDTH-1:0] TXC_DATA, output TXC_DATA_START_FLAG, - output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET, + output [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_START_OFFSET, output TXC_DATA_END_FLAG, - output [clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET, + output [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] TXC_DATA_END_OFFSET, input TXC_DATA_READY, output TXC_META_VALID, @@ -128,8 +128,8 @@ module registers localparam C_FIELDS_WIDTH = 4; localparam C_OUTPUT_STAGES = C_PIPELINE_OUTPUT > 0 ? 1:0; localparam C_INPUT_STAGES = C_PIPELINE_INPUT > 0 ? 1:0; - localparam C_TXC_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + clog2(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_LOWADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_BYTECNT_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W + 1; - localparam C_RXR_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + clog2(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_ADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W; + localparam C_TXC_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + `clog2s(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_LOWADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_BYTECNT_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W + 1; + localparam C_RXR_REGISTER_WIDTH = C_PCI_DATA_WIDTH + 2*(1 + `clog2s(C_PCI_DATA_WIDTH/32) + `SIG_FBE_W) + `SIG_ADDR_W + `SIG_TYPE_W + `SIG_LEN_W + `SIG_TAG_W + `SIG_REQID_W + `SIG_TC_W + `SIG_ATTR_W; // The Mem/IO read/write address space should be at least 8 bits wide. This // means we'll need at least 10 bits of BAR 0, at least 1024 bytes. The bottom @@ -164,10 +164,10 @@ module registers wire [C_PCI_DATA_WIDTH-1:0] wRxrData; wire wRxrDataValid; wire wRxrDataStartFlag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataStartOffset; wire [`SIG_FBE_W-1:0] wRxrMetaFdwbe; wire wRxrDataEndFlag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] wRxrDataEndOffset; wire [`SIG_LBE_W-1:0] wRxrMetaLdwbe; wire [`SIG_TC_W-1:0] wRxrMetaTc; wire [`SIG_ATTR_W-1:0] wRxrMetaAttr; @@ -180,10 +180,10 @@ module registers wire [C_PCI_DATA_WIDTH-1:0] wTxcData; wire wTxcDataValid; wire wTxcDataStartFlag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcDataStartOffset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcDataStartOffset; wire [`SIG_FBE_W-1:0] wTxcMetaFdwbe; wire wTxcDataEndFlag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcDataEndOffset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] wTxcDataEndOffset; wire [`SIG_LBE_W-1:0] wTxcMetaLdwbe; wire [`SIG_LOWADDR_W-1:0] wTxcMetaAddr; wire [`SIG_TYPE_W-1:0] wTxcMetaType; @@ -196,7 +196,7 @@ module registers wire wTxcMetaEp; wire wTxcDataReady; - wire [clog2s(C_NUM_CHNL)-1:0] wReqChnl; + wire [`clog2s(C_NUM_CHNL)-1:0] wReqChnl; wire [C_FIELDS_WIDTH-1:0] wReqField; wire [(1<= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}}; + assign _wTxMuxSelectDataReady = wReadyMux[wReadyMuxSelect] & {C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:`clog2s(C_NUM_MUXES)])}}; assign _wTxMuxSelectDataReadyAndPayload = wReadyMux[wReadyMuxSelect] & - {C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)])}} & + {C_NUM_MUXES{(wPktCtr >= _wTxHdrNonpayLen[`SIG_NONPAY_W-1:`clog2s(C_NUM_MUXES)])}} & {C_NUM_MUXES{~_wTxHdrNoPayload}} & {C_NUM_MUXES{_wTxHdrValid}}; assign _wTxMuxSelectPktStartFlag = wPktCtr == 0; - assign _wTxMuxSelectDataStartFlag = wPktCtr == _wTxHdrNonpayLen[`SIG_NONPAY_W-1:clog2s(C_NUM_MUXES)]; - assign _wTxMuxSelectDataEndFlag = ({wPktCtr,{clog2s(C_NUM_MUXES){1'b0}}} + C_NUM_MUXES) >= _wTxHdrPacketLen;// TODO: Simplify + assign _wTxMuxSelectDataStartFlag = wPktCtr == _wTxHdrNonpayLen[`SIG_NONPAY_W-1:`clog2s(C_NUM_MUXES)]; + assign _wTxMuxSelectDataEndFlag = ({wPktCtr,{`clog2s(C_NUM_MUXES){1'b0}}} + C_NUM_MUXES) >= _wTxHdrPacketLen;// TODO: Simplify // Assignments for the ready stage assign wTxHdrReady = (wTxMuxSelectDataEndFlag & wTxMuxSelectValid & wTxMuxSelectReady) | ~wTxMuxSelectValid; @@ -274,7 +274,7 @@ module tx_alignment_pipeline .MASK (__wTxHdrPacketMask), // Inputs .OFFSET_ENABLE (1), - .OFFSET (__wTxHdrPacketLenMinus1[clog2s(C_NUM_MUXES)-1:0]) + .OFFSET (__wTxHdrPacketLenMinus1[`clog2s(C_NUM_MUXES)-1:0]) /*AUTOINST*/); offset_to_mask @@ -287,7 +287,7 @@ module tx_alignment_pipeline .MASK (__wTxHdrLenMask), // Inputs .OFFSET_ENABLE (1), - .OFFSET (__wTxHdrPayloadLen[clog2s(C_NUM_MUXES)-1:0]-1) + .OFFSET (__wTxHdrPayloadLen[`clog2s(C_NUM_MUXES)-1:0]-1) /*AUTOINST*/); rotate diff --git a/fpga/riffa_hdl/tx_data_fifo.v b/fpga/riffa_hdl/tx_data_fifo.v index dfe62ae..7018675 100644 --- a/fpga/riffa_hdl/tx_data_fifo.v +++ b/fpga/riffa_hdl/tx_data_fifo.v @@ -123,12 +123,12 @@ module tx_data_fifo wire wPacketDecrement; wire wPacketIncrement; - //reg [clog2(C_DEPTH_PACKETS+1)-1:0] rPacketCounter,_rPacketCounter; - wire [clog2(C_DEPTH_PACKETS+1)-1:0] wPacketCounter; + //reg [$clog2(C_DEPTH_PACKETS+1)-1:0] rPacketCounter,_rPacketCounter; + wire [$clog2(C_DEPTH_PACKETS+1)-1:0] wPacketCounter; wire [C_NUM_FIFOS-1:0] wEFDecrement; wire [C_NUM_FIFOS-1:0] wEFIncrement; - wire [clog2(C_DEPTH_PACKETS+1)-1:0] wEFCounter [C_NUM_FIFOS-1:0]; + wire [$clog2(C_DEPTH_PACKETS+1)-1:0] wEFCounter [C_NUM_FIFOS-1:0]; wire [C_NUM_FIFOS-1:0] wEFValid; /*AUTOINPUT*/ /*AUTOWIRE*/ @@ -295,13 +295,13 @@ module counter_v2 input INC, input DEC, - output [clog2s(C_MAX_VALUE+1)-1:0] VALUE); + output [`clog2s(C_MAX_VALUE+1)-1:0] VALUE); wire wInc; wire wDec; - reg [clog2s(C_MAX_VALUE+1)-1:0] wCtrValue; - reg [clog2s(C_MAX_VALUE+1)-1:0] rCtrValue; + reg [`clog2s(C_MAX_VALUE+1)-1:0] wCtrValue; + reg [`clog2s(C_MAX_VALUE+1)-1:0] rCtrValue; /* verilator lint_off WIDTH */ assign wInc = INC & (C_SAT_VALUE > rCtrValue); assign wDec = DEC & (C_FLR_VALUE < rCtrValue); @@ -309,7 +309,7 @@ module counter_v2 assign VALUE = rCtrValue; always @(posedge CLK) begin if(RST_IN) begin - rCtrValue <= C_RST_VALUE[clog2s(C_MAX_VALUE+1)-1:0]; + rCtrValue <= C_RST_VALUE[`clog2s(C_MAX_VALUE+1)-1:0]; end else if(wInc & wDec) begin rCtrValue <= rCtrValue + 0; end else if(wInc) begin diff --git a/fpga/riffa_hdl/tx_data_pipeline.v b/fpga/riffa_hdl/tx_data_pipeline.v index cf858a7..3f6335b 100644 --- a/fpga/riffa_hdl/tx_data_pipeline.v +++ b/fpga/riffa_hdl/tx_data_pipeline.v @@ -69,9 +69,9 @@ module tx_data_pipeline input WR_TX_DATA_VALID, input [C_DATA_WIDTH-1:0] WR_TX_DATA, input WR_TX_DATA_START_FLAG, - input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET, + input [`clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET, input WR_TX_DATA_END_FLAG, - input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET, + input [`clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET, output WR_TX_DATA_READY, // Interface: TX DATA FIFOS @@ -118,9 +118,9 @@ module tx_data_pipeline .WR_TX_DATA_VALID (WR_TX_DATA_VALID), .WR_TX_DATA (WR_TX_DATA[C_DATA_WIDTH-1:0]), .WR_TX_DATA_START_FLAG (WR_TX_DATA_START_FLAG), - .WR_TX_DATA_START_OFFSET (WR_TX_DATA_START_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0]), + .WR_TX_DATA_START_OFFSET (WR_TX_DATA_START_OFFSET[`clog2s(C_DATA_WIDTH/32)-1:0]), .WR_TX_DATA_END_FLAG (WR_TX_DATA_END_FLAG), - .WR_TX_DATA_END_OFFSET (WR_TX_DATA_END_OFFSET[clog2s(C_DATA_WIDTH/32)-1:0])); + .WR_TX_DATA_END_OFFSET (WR_TX_DATA_END_OFFSET[`clog2s(C_DATA_WIDTH/32)-1:0])); // TX Data Fifo tx_data_fifo diff --git a/fpga/riffa_hdl/tx_data_shift.v b/fpga/riffa_hdl/tx_data_shift.v index d54a2cc..bab1835 100644 --- a/fpga/riffa_hdl/tx_data_shift.v +++ b/fpga/riffa_hdl/tx_data_shift.v @@ -1,24 +1,24 @@ // ---------------------------------------------------------------------- // Copyright (c) 2016, The Regents of the University of California All // rights reserved. -// +// // Redistribution and use in source and binary forms, with or without // modification, are permitted provided that the following conditions are // met: -// +// // * Redistributions of source code must retain the above copyright // notice, this list of conditions and the following disclaimer. -// +// // * Redistributions in binary form must reproduce the above // copyright notice, this list of conditions and the following // disclaimer in the documentation and/or other materials provided // with the distribution. -// +// // * Neither the name of The Regents of the University of California // nor the names of its contributors may be used to endorse or // promote products derived from this software without specific // prior written permission. -// +// // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR @@ -54,19 +54,19 @@ // value of wWrTxDataStartOffset. These registers are enabled when // wWrTxDataStartFlag is 1 and their value set based on the value of // wWrTxDataStartOffset. -// +// // Each bit in the VALID bus is determined by the result of two masks, // wRdTxEndFlagMask and wRdTxStartFlagMask, to make wRdTxDataValid. The start flag // mask is active when wWrTxDataStartFlag is 1, based on wWrTxDataStartOffset. The // end flag mask is active when wWrTxDataEndFlag is 1, based on // wWrTxDataEndOffset. -// -// TODO: +// +// TODO: // - Using WORD_VALID is a little bit confusing. I should bring back VALID as well // - WORD_VALID should be DWORD_VALID // - Use a uniform naming scheme for C_DATA_WIDTH/32 // - Is there a more efficient way to implement the wRdTxStartMaskFlag? Perhaps using the reset of a register? -// Author: Dustin Richmond (@darichmond) +// Author: Dustin Richmond (@darichmond) //----------------------------------------------------------------------------- `timescale 1ns/1ns `include "trellis.vh" @@ -88,9 +88,9 @@ module tx_data_shift input WR_TX_DATA_VALID, input [C_DATA_WIDTH-1:0] WR_TX_DATA, input WR_TX_DATA_START_FLAG, - input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET, + input [`clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_START_OFFSET, input WR_TX_DATA_END_FLAG, - input [clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET, + input [`clog2s(C_DATA_WIDTH/32)-1:0] WR_TX_DATA_END_OFFSET, output WR_TX_DATA_READY, // Interface: RD TX DATA @@ -101,20 +101,20 @@ module tx_data_shift output [(C_DATA_WIDTH/32)-1:0] RD_TX_DATA_END_FLAGS, output RD_TX_DATA_VALID ); - localparam C_ROTATE_BITS = clog2s(C_DATA_WIDTH/32); + localparam C_ROTATE_BITS = `clog2s(C_DATA_WIDTH/32); localparam C_NUM_MUXES = (C_DATA_WIDTH/32); localparam C_SELECT_WIDTH = C_DATA_WIDTH/32; localparam C_MASK_WIDTH = C_DATA_WIDTH/32; localparam C_AGGREGATE_WIDTH = C_DATA_WIDTH; - + genvar i; wire wWrTxDataValid; wire [C_DATA_WIDTH-1:0] wWrTxData; wire wWrTxDataStartFlag; - wire [clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataStartOffset; + wire [`clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataStartOffset; wire wWrTxDataEndFlag; - wire [clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataEndOffset; + wire [`clog2s(C_DATA_WIDTH/32)-1:0] wWrTxDataEndOffset; wire [(C_DATA_WIDTH/32)-1:0] wWrTxEndFlagMask; wire [(C_DATA_WIDTH/32)-1:0] wWrTxDataEndFlags; wire wWrTxDataReady; @@ -130,17 +130,17 @@ module tx_data_shift // wSelectDefault is the default select value for each mux, 1 << i where i // is the mux/dword index. - wire [C_SELECT_WIDTH-1:0] wSelectDefault[C_NUM_MUXES-1:0]; + wire [C_SELECT_WIDTH-1:0] wSelectDefault[C_NUM_MUXES-1:0]; // wSelectRotated is the value the select for each mux after the data's // start offset has been applied and until the end flag is seen. wire [C_SELECT_WIDTH-1:0] wSelectRotated[C_NUM_MUXES-1:0]; reg [C_SELECT_WIDTH-1:0] rMuxSelect[C_NUM_MUXES-1:0],_rMuxSelect[C_NUM_MUXES-1:0]; - reg [clog2s(C_DATA_WIDTH/32)-1:0] rStartOffset,_rStartOffset; + reg [`clog2s(C_DATA_WIDTH/32)-1:0] rStartOffset,_rStartOffset; assign wWrTxDataReady = wRdTxDataReady; - assign wRdTxStartFlagMask = wWrTxDataStartFlag ? + assign wRdTxStartFlagMask = wWrTxDataStartFlag ? {(C_DATA_WIDTH/32){1'b1}} >> wWrTxDataStartOffset: {(C_DATA_WIDTH/32){1'b1}}; assign wRdTxDataWordValid = wRdTxEndFlagMask & wRdTxStartFlagMask; @@ -176,10 +176,10 @@ module tx_data_shift end end endgenerate - + pipeline #(// Parameters - .C_WIDTH (C_DATA_WIDTH+2*(1+clog2s(C_DATA_WIDTH/32))), + .C_WIDTH (C_DATA_WIDTH+2*(1+`clog2s(C_DATA_WIDTH/32))), .C_USE_MEMORY (0), .C_DEPTH (C_PIPELINE_INPUT?1:0) /*AUTOINSTPARAM*/) @@ -198,7 +198,7 @@ module tx_data_shift // Inputs .CLK (CLK), .RST_IN (RST_IN)); - + // The pipeline carries the data bus and SOF/EOF. pipeline #(// Parameters @@ -249,7 +249,7 @@ module tx_data_shift .RD_DATA (wRdTxEndFlagMask), // Inputs .WR_DATA (wWrTxEndFlagMask), - .WR_SHIFTAMT (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]) + .WR_SHIFTAMT (rStartOffset[`clog2s(C_DATA_WIDTH/32)-1:0]) /*AUTOINST*/); // Determine the 1-hot dword end flag @@ -262,7 +262,7 @@ module tx_data_shift // Outputs .RD_ONE_HOT (wWrTxDataEndFlags), // Inputs - .WR_OFFSET (wWrTxDataEndOffset[clog2s(C_DATA_WIDTH/32)-1:0]), + .WR_OFFSET (wWrTxDataEndOffset[`clog2s(C_DATA_WIDTH/32)-1:0]), .WR_FLAG (wWrTxDataEndFlag) /*AUTOINST*/); @@ -278,7 +278,7 @@ module tx_data_shift .RD_DATA (wRdTxDataEndFlags), // Inputs .WR_DATA (wWrTxDataEndFlags), - .WR_SHIFTAMT (rStartOffset[clog2s(C_DATA_WIDTH/32)-1:0]) + .WR_SHIFTAMT (rStartOffset[`clog2s(C_DATA_WIDTH/32)-1:0]) /*AUTOINST*/); generate @@ -322,5 +322,4 @@ module tx_data_shift endmodule // Local Variables: // verilog-library-directories:("." "../../../common/" "../../common/") -// End: - +// End: diff --git a/fpga/riffa_hdl/tx_engine.v b/fpga/riffa_hdl/tx_engine.v index c64a281..bbe814b 100644 --- a/fpga/riffa_hdl/tx_engine.v +++ b/fpga/riffa_hdl/tx_engine.v @@ -76,24 +76,24 @@ module tx_engine input TX_DATA_VALID, input [C_DATA_WIDTH-1:0] TX_DATA, input TX_DATA_START_FLAG, - input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET, + input [`clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_START_OFFSET, input TX_DATA_END_FLAG, - input [clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET, + input [`clog2s(C_DATA_WIDTH/32)-1:0] TX_DATA_END_OFFSET, output TX_DATA_READY, // Interface: TX_PKT input TX_PKT_READY, output [C_DATA_WIDTH-1:0] TX_PKT, output TX_PKT_START_FLAG, - output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET, + output [`clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_START_OFFSET, output TX_PKT_END_FLAG, - output [clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET, + output [`clog2s(C_DATA_WIDTH/32)-1:0] TX_PKT_END_OFFSET, output TX_PKT_VALID ); localparam C_PIPELINE_HDR_FIFO_INPUT = C_PIPELINE_INPUT; localparam C_PIPELINE_HDR_FIFO_OUTPUT = C_PIPELINE_OUTPUT; localparam C_PIPELINE_HDR_INPUT = C_PIPELINE_INPUT; - localparam C_ACTUAL_HDR_FIFO_DEPTH = (1< - + - + - + - + - - + + - + - + - - + - - + - + + - + + - + + - + - + - + - + - + - - + - - + - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + - + - + - + - + - + - + - + - + - - + - + - + - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + + - + - + + - + - + - + - + - - + - + - + - + - + - + - + - + - + - + - + - + - + + - + - + - + - + - + - + - + - + - + - + - + - + - + + - + - + - + - + @@ -737,10 +764,18 @@ + + + + + @@ -769,6 +804,9 @@ + + @@ -777,21 +815,27 @@ - + + + - + - + + Vivado Synthesis Defaults + + + - + @@ -805,10 +849,14 @@ + + - + - + + Default settings for Implementation. + @@ -819,6 +867,43 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + default_dashboard + + + + + diff --git a/fpga/xilinx/zc706/riffa_wrapper_zc706.v b/fpga/xilinx/zc706/riffa_wrapper_zc706.v index 96518fe..379aae6 100644 --- a/fpga/xilinx/zc706/riffa_wrapper_zc706.v +++ b/fpga/xilinx/zc706/riffa_wrapper_zc706.v @@ -141,10 +141,10 @@ module riffa_wrapper_zc706 wire rxc_data_valid; wire rxc_data_start_flag; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_word_enable; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_start_offset; wire [`SIG_FBE_W-1:0] rxc_meta_fdwbe; wire rxc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxc_data_end_offset; wire [`SIG_LBE_W-1:0] rxc_meta_ldwbe; wire [`SIG_TAG_W-1:0] rxc_meta_tag; wire [`SIG_LOWADDR_W-1:0] rxc_meta_addr; @@ -159,10 +159,10 @@ module riffa_wrapper_zc706 wire rxr_data_valid; wire [(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_word_enable; wire rxr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_start_offset; wire [`SIG_FBE_W-1:0] rxr_meta_fdwbe; wire rxr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] rxr_data_end_offset; wire [`SIG_LBE_W-1:0] rxr_meta_ldwbe; wire [`SIG_TC_W-1:0] rxr_meta_tc; wire [`SIG_ATTR_W-1:0] rxr_meta_attr; @@ -178,9 +178,9 @@ module riffa_wrapper_zc706 wire txc_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txc_data; wire txc_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_start_offset; wire txc_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txc_data_end_offset; wire txc_data_ready; wire txc_meta_valid; @@ -202,9 +202,9 @@ module riffa_wrapper_zc706 wire txr_data_valid; wire [C_PCI_DATA_WIDTH-1:0] txr_data; wire txr_data_start_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_start_offset; wire txr_data_end_flag; - wire [clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; + wire [`clog2s(C_PCI_DATA_WIDTH/32)-1:0] txr_data_end_offset; wire txr_data_ready; wire txr_meta_valid; @@ -300,9 +300,9 @@ module riffa_wrapper_zc706 .RX_TLP (rx_tlp[C_PCI_DATA_WIDTH-1:0]), .RX_TLP_VALID (rx_tlp_valid), .RX_TLP_START_FLAG (rx_tlp_start_flag), - .RX_TLP_START_OFFSET (rx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_START_OFFSET (rx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_END_FLAG (rx_tlp_end_flag), - .RX_TLP_END_OFFSET (rx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RX_TLP_END_OFFSET (rx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RX_TLP_BAR_DECODE (rx_tlp_bar_decode[`SIG_BARDECODE_W-1:0]), .TX_TLP_READY (tx_tlp_ready), .CONFIG_COMPLETER_ID (config_completer_id[`SIG_CPLID_W-1:0]), @@ -323,9 +323,9 @@ module riffa_wrapper_zc706 .TX_TLP (tx_tlp[C_PCI_DATA_WIDTH-1:0]), .TX_TLP_VALID (tx_tlp_valid), .TX_TLP_START_FLAG (tx_tlp_start_flag), - .TX_TLP_START_OFFSET (tx_tlp_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_START_OFFSET (tx_tlp_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TX_TLP_END_FLAG (tx_tlp_end_flag), - .TX_TLP_END_OFFSET (tx_tlp_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TX_TLP_END_OFFSET (tx_tlp_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .INTR_MSI_REQUEST (intr_msi_request), /*AUTOINST*/ // Outputs @@ -375,10 +375,10 @@ module riffa_wrapper_zc706 .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]), .RXC_META_ADDR (rxc_meta_addr[`SIG_LOWADDR_W-1:0]), @@ -392,9 +392,9 @@ module riffa_wrapper_zc706 .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -433,9 +433,9 @@ module riffa_wrapper_zc706 .TXC_DATA_VALID (txc_data_valid), .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -452,9 +452,9 @@ module riffa_wrapper_zc706 .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -523,9 +523,9 @@ module riffa_wrapper_zc706 .TXC_DATA (txc_data[C_PCI_DATA_WIDTH-1:0]), .TXC_DATA_VALID (txc_data_valid), .TXC_DATA_START_FLAG (txc_data_start_flag), - .TXC_DATA_START_OFFSET (txc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_START_OFFSET (txc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_DATA_END_FLAG (txc_data_end_flag), - .TXC_DATA_END_OFFSET (txc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXC_DATA_END_OFFSET (txc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXC_META_VALID (txc_meta_valid), .TXC_META_FDWBE (txc_meta_fdwbe[`SIG_FBE_W-1:0]), .TXC_META_LDWBE (txc_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -542,9 +542,9 @@ module riffa_wrapper_zc706 .TXR_DATA_VALID (txr_data_valid), .TXR_DATA (txr_data[C_PCI_DATA_WIDTH-1:0]), .TXR_DATA_START_FLAG (txr_data_start_flag), - .TXR_DATA_START_OFFSET (txr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_START_OFFSET (txr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_DATA_END_FLAG (txr_data_end_flag), - .TXR_DATA_END_OFFSET (txr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .TXR_DATA_END_OFFSET (txr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .TXR_META_VALID (txr_meta_valid), .TXR_META_FDWBE (txr_meta_fdwbe[`SIG_FBE_W-1:0]), .TXR_META_LDWBE (txr_meta_ldwbe[`SIG_LBE_W-1:0]), @@ -562,10 +562,10 @@ module riffa_wrapper_zc706 .RXR_DATA (rxr_data[C_PCI_DATA_WIDTH-1:0]), .RXR_DATA_VALID (rxr_data_valid), .RXR_DATA_START_FLAG (rxr_data_start_flag), - .RXR_DATA_START_OFFSET (rxr_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_START_OFFSET (rxr_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_WORD_ENABLE (rxr_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_DATA_END_FLAG (rxr_data_end_flag), - .RXR_DATA_END_OFFSET (rxr_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXR_DATA_END_OFFSET (rxr_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXR_META_FDWBE (rxr_meta_fdwbe[`SIG_FBE_W-1:0]), .RXR_META_LDWBE (rxr_meta_ldwbe[`SIG_LBE_W-1:0]), .RXR_META_TC (rxr_meta_tc[`SIG_TC_W-1:0]), @@ -581,10 +581,10 @@ module riffa_wrapper_zc706 .RXC_DATA_VALID (rxc_data_valid), .RXC_DATA (rxc_data[C_PCI_DATA_WIDTH-1:0]), .RXC_DATA_START_FLAG (rxc_data_start_flag), - .RXC_DATA_START_OFFSET (rxc_data_start_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_START_OFFSET (rxc_data_start_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_WORD_ENABLE (rxc_data_word_enable[(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_DATA_END_FLAG (rxc_data_end_flag), - .RXC_DATA_END_OFFSET (rxc_data_end_offset[clog2s(C_PCI_DATA_WIDTH/32)-1:0]), + .RXC_DATA_END_OFFSET (rxc_data_end_offset[`clog2s(C_PCI_DATA_WIDTH/32)-1:0]), .RXC_META_FDWBE (rxc_meta_fdwbe[`SIG_FBE_W-1:0]), .RXC_META_LDWBE (rxc_meta_ldwbe[`SIG_LBE_W-1:0]), .RXC_META_TAG (rxc_meta_tag[`SIG_TAG_W-1:0]),