Cross-talk between channels

[andpet1324]

I'm opening this issue to document the study of potential cross-talk between channels.

As hinted at by Verena in https://github.com/LDMX-Software/pflib/wiki/Linearity-of-the-ADC-vs-input-charge, there looks to be cross-talk between channels when doing charge injections on lowrange and highrange. Is this a result of poor isolation for this type of charge injections? Are the capacitors themselves the culprit?

We would like to analyze the cross-talk for pre-CC charge injections, and compare to external charge injections. Hopefully the cross-talk is only evident in the charge injections for lowrange and highrange, or a result from charging and discharging the capacitors, and therefore shouldn't raise an issue when taking real data.

[jmmans]

Channels 0-35 share capacitors and channels 36-71 share capacitors.

[andpet1324]

From "Design and characterization of readout ASICs for SiPM
detectors in pico-second timing measurements for the
CMS HGCAL experiment" by José González Martínez:

In section 5.5.3 he is talking about cross talk and states
"From the coherent noise analysis, a minimal correlation is observed between the two inde-
pendent halves of the chip. However, independent signals arriving at one channel are expected
to affect other channels, particularly neighboring ones"

[andpet1324]

Characterizing cross-talk.

I have taken data where I do charge injections with increasing multiplicity. I start with one channel (16) and increase outwards by two in iterations (15,16,17 -> 14,15,16,17,18...). I do this link-wise. I realized that the middle channel is 18 and not 16, so I need to change that.

First I plotted the adc vs time. I get this

Here I'm showing 1 and 3 charge injections in respective figure. Here we see that the pedestal values for each pulse change with the increase of charge injections (Probably just because the voltage gets distributed). I do this again, selecting only one calib:

We can ignore the RMS plot here as I don't use it yet. We see that the initial channel (ch15 in the plot) has its pedestal value increase from about 250 to around 275. Similarly ch16 gets lowered to about 200. I think this is purely an effect of the capacitors and not cross-talk. If we include almost all channels we get this:

If this effect is a result from cross-talk (unlikely), then we have a big problem. What we have here is more of a confirmation that ASIC characterization using internal charge injections, with all channels at once, is not good practice.

I now look at max ADC vs channels:

The dashed line at 35.5 indicates the link cutoff. I limit myself to looking at one calib (2048), since it's easier to understand what's going on:

The pedestal is sampled during the first iteration when we're only doing one charge injection (I want this to be for 0 charge injections but didn't have that data at the time), and is then used for the RMS in all other iterations. I calculate the average RMS of non-activated channels (pedestals) on the activated link (link 0 in this case). I did this using the "sigma_clipped_stats" from the astropy library. This method focuses on removing outliers, which gives a better estimate of the mean, i.e. the pedestal.

Next I turned to analyzing the this value as an effect of increasing channels:

He're we're plotting the average RMS of non-activated channel for every calib that I was iterating over, and then taking a linear fit of the data. For reference, the average RMS increases with CALIB, which we can also see in this plot:

Where I plotted the slopes and intercepts as functions of CALIB.

We see that the intercept increases with larger charge injections, meaning that the overall noise on all channels is higher (cross-talk?). That the slope of the average RMS increases with larger CALIB is a pretty good indicator of cross-talk.

There doesn't seem to be any cross-talk between links.

[andpet1324]

The RMS that I looked at above is only noise. We want to look for distinguishable cross-talk, or noticeable differences in ADC on channels that aren't injected on. @verenamh had seen this before on highrange charge injection which I was able to replicate:

Here I'm showing the ADC on all channels for link 0. The injected channels are all calibrated to CALIB = 2048. We can see that the pedestal has a dip on channels that aren't being pulsed. There seems to be cross-talk between all channels simultaneously on the link. No cross talk is observed on link 1, the quiet link, except for a small increase in noise when injecting on almost all channels on link 0.

Next I looked at if I can reproduce this with external charge injections, which were done using the LED L1A trigger. We got the following plots for 400mV, 800mV and 2V on an external function generator pulsing channels 9,10,11 and 12 simultaneously:

We still see the dip, which we conclude is an expected feature of the chip. No local neighboring-channel cross talk is observed.

[andpet1324]

Next I'd like to see if this dip in the ADC has any effect on incoming pulses. For example, if we have a huge pulse in one channel, will it attenuate a smaller pulse in another channel?