how to design superscalar, out-of-order , 64-bit dual-core processor

[changeyourname]

how to design superscalar, out-of-order , 64-bit dual-core processor based mipsfpga,do yo have plan to do

[yuri-panchul]

jiangxilong :

The microarchitecture of the processor core used in MIPSfpga (MIPS microAptiv UP) is based on simple 5-stage in-order design that implements 32-bit architecture. It makes no sense to use it as a base for superscalar, out-of-order, 64-bit design. It is just a different class of processors, optimized for different design goal. It is just like starting a pickup truck from a motor bicycle.

Multi-core is somewhat different. Several professors asked me whether MIPSfpga support building multi-core systems.

The answer depends on whether you talking about multi-core systems with cache coherence or without cache coherence.

If “with cache coherence”:

MIPSfpga is not suitable for cache coherence protocols (MESI and similar). Some very advanced students or researchers can implement MESI protocol in MIPSfpga by replacing MIPSfpga modules for caches and writing their own coherence manager block. However the resulting implementation is not likely to be practical in terms of performance improvement. Multi-core with cache coherence becomes practical only for MIPS mid-range (MIPS interAptiv, MIPS I6400) or high-end (MIPS P5600, MIPS P6600) cores which are available only for commercial licensing.

If “without cache coherence”:

MIPSfpga can be used for specialized multicore systems where each core has its own mostly separate memory space and the cores exchange information with each other infrequently, via some logic (like FIFOs) connected to memory-mapped registers in uncached address space. This is an important area for academic creativity. However keep in mind that such way of using MIPSfpga is practical only for some applications like parallel internet packet processing, but is not practical for general-purpose computing.

Same thing is applicable to MIPSfpga commercial relatives – MIPS microAptiv UP and MIPS M5150.

If you don’t know the meaning of “cache coherence” and “MESI”, you can start from Wikipedia:

http://en.wikipedia.org/wiki/Cache_coherence
http://en.wikipedia.org/wiki/MESI_protocol

[IngenicC]

Are you plan to design Mesi protocolo or Cache coherence

[yuri-panchul]

I personally don't, but I know at least one university professor from Kiev, Ukraine, who wants to add MESI cache coherence to MIPSfpga (Alexander Barabanov).