cpu.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 02.04.2025 12:28:17
// Design Name: 
// Module Name: cpu
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module cpu(
    input clk, reset,
    input [7:0] instr,      // 8-bit instruction
    output [7:0] result
);
    reg [7:0] registers [3:0];  // 4 registers (R0-R3)
    reg [7:0] pc;               // Program Counter
    wire [3:0] opcode;
    wire [1:0] reg1, reg2;
    wire [7:0] mem_out;
    reg [7:0] alu_out;
    reg mem_write, mem_read, jump;
    reg [7:0] mem_addr, mem_data;

    assign opcode = instr[7:4];
    assign reg1 = instr[3:2];
    assign reg2 = instr[1:0];

    // Memory Module
    memory mem_unit (.clk(clk), .mem_write(mem_write), .mem_read(mem_read),
                     .address(mem_addr), .data_in(mem_data), .data_out(mem_out));

    // ALU & Memory Operations
    always @(*) begin
        mem_write = 0;
        mem_read = 0;
        jump = 0;
        case (opcode)
            4'b0001: alu_out = registers[reg1] + registers[reg2]; // ADD
            4'b0010: alu_out = registers[reg1] - registers[reg2]; // SUB
            4'b0100: begin  // LOAD R1, Addr
                mem_addr = registers[reg2];  
                mem_read = 1;
            end
            4'b0101: begin  // STORE R1, Addr
                mem_addr = registers[reg2];
                mem_data = registers[reg1];
                mem_write = 1;
            end
            4'b0111: pc = registers[reg1]; // JMP R1 (Jump to address in register)
            4'b1000: if (registers[reg1] == 0) pc = registers[reg2]; // BZ R, Addr
            default: alu_out = 8'b00000000;
        endcase
    end

    // Register Write & PC Update
    always @(posedge clk or posedge reset) begin
        if (reset) begin
            pc <= 0;
        end else begin
            if (opcode == 4'b0100)  // If LOAD, write memory output to register
                registers[reg1] <= mem_out;
            else if (opcode < 4'b0111)  // Don't overwrite for JUMP/BZ
                registers[reg1] <= alu_out;

            if (!jump)
                pc <= pc + 1;  // Increment PC normally if no jump
        end
    end

    assign result = alu_out;

endmodule