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Description
Currently line directive is used only by preprocessor. Preprocessor builds a large string from all the input files and this string is an input of the parser.
Problem is that the original code positions are usually lost because preprocessor does not set line directive and Verilog parser ignores it.
Solution:
- Mark all code segments with proper
linedirective https://github.com/Nic30/hdlConvertor/blob/master/src/verilogPreproc/verilogPreprocContainer.cpp#L90. - Add lexer and parser rules for
linedirectives to SystemVerilog grammar https://github.com/Nic30/hdlConvertor/blob/master/grammars/sv2017Lexer.g4 https://github.com/Nic30/hdlConvertor/blob/master/grammars/sv2017Parser.g4 - instead sharing just comment parser https://github.com/Nic30/hdlConvertor/blob/master/include/hdlConvertor/svConvertor/moduleParser.h#L16 between all parsers create a
SVParserContextwhich will contain commentParser and actual file and offset which will be used for all positions of objects and all exceptions.
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