ecdsa: Modify driver based on the review comment.

Specializing the implementation for curve type Secp384r1Curve.

Signed-off-by: Steven Lee <steven_lee@aspeedtech.com>

Author: stevenlee7189

src/ecdsa.rs

@@ -1,4 +1,4 @@
-use core::ptr::{read_volatile, write_volatile};
+use core::ptr::{NonNull, read_volatile, write_volatile};
 use ast1060_pac::Secure;
 use proposed_traits::ecdsa::{EcdsaVerify, Curve, SignatureForCurve, PubKeyForCurve, ErrorType as EcdsaErrorType, Error, ErrorKind};
 use proposed_traits::common::{FromBytes, ToBytes, Endian, ErrorKind as CommonErrorKind, ErrorType as CommonErrorType, SerdeError as CommonSerdeError};
@@ -221,41 +221,39 @@ pub struct AspeedEcdsa<'a, D: DelayNs> {
     sram_base: NonNull<u32>,
     delay: D,
 }
-    secure: &'a Secure,
-    ecdsa_base: *mut u32,
-    sram_base: *mut u32,
-    delay: D,
-}
 
 impl<D: DelayNs> EcdsaErrorType for AspeedEcdsa<'_, D> {
     type Error = AspeedEcdsaError;
 }
 
 impl<'a, D: DelayNs> AspeedEcdsa<'a, D> {
     pub fn new(secure: &'a Secure, delay: D) -> Self {
-        let ecdsa_base = ECDSA_BASE as *mut u32; // SBC base address
-        let sram_base = ECDSA_SRAM_BASE as *mut u32; // SRAM base address for ECDSA
+        let ecdsa_base = unsafe { NonNull::new_unchecked(ECDSA_BASE as *mut u32) };
+        let sram_base  = unsafe { NonNull::new_unchecked(ECDSA_SRAM_BASE as *mut u32) };
+
+        // let ecdsa_base = ECDSA_BASE as *mut u32; // SBC base address
+        // let sram_base = ECDSA_SRAM_BASE as *mut u32; // SRAM base address for ECDSA
         Self { secure, ecdsa_base, sram_base, delay }
     }
 
     #[inline(always)]
     fn sec_rd(&self, offset: usize) -> u32 {
         unsafe {
-            read_volatile(self.ecdsa_base.add(offset / 4))
+            read_volatile(self.ecdsa_base.as_ptr().add(offset / 4))
         }
     }
 
     #[inline(always)]
     fn sec_wr(&self, offset: usize, val: u32) {
         unsafe {
-            write_volatile(self.ecdsa_base.add(offset / 4), val);
+            write_volatile(self.ecdsa_base.as_ptr().add(offset / 4), val);
         }
     }
 
     #[inline(always)]
     fn sram_wr_u32(&self, offset: usize, val: u32) {
         unsafe {
-            write_volatile(self.sram_base.add(offset / 4), val);
+            write_volatile(self.sram_base.as_ptr().add(offset / 4), val);
         }
     }
 
@@ -264,7 +262,7 @@ impl<'a, D: DelayNs> AspeedEcdsa<'a, D> {
         for i in (0..Scalar48::LEN).step_by(4) {
             let val = u32::from_le_bytes([data[i], data[i + 1], data[i + 2], data[i + 3]]);
             unsafe {
-                write_volatile(self.sram_base.add((offset + i) / 4), val);
+                write_volatile(self.sram_base.as_ptr().add((offset + i) / 4), val);
             }
         }
     }
@@ -360,75 +358,3 @@ where
         }
     }
 }
-
-where
-    C: Curve<Scalar = Scalar48>,
-    C::DigestType: DigestAlgorithm,
-    <C::DigestType as DigestAlgorithm>::DigestOutput: AsRef<[u8]>,
-    D: DelayNs,
-{
-    type PublicKey = PublicKey;
-    type Signature = Signature;
-
-    fn verify(
-        &mut self,
-        public_key: &Self::PublicKey,
-        digest: <C::DigestType as DigestAlgorithm>::DigestOutput,
-        signature: &Self::Signature,
-    ) -> Result<(), Self::Error> {
-        const LEN: usize = Scalar48::LEN;
-        unsafe {
-            let digest_bytes = digest.as_ref();
-            if digest_bytes.len() != LEN {
-                return Err(AspeedEcdsaError::BadInput);
-            }
-
-            let digest_array: &[u8; LEN] = digest_bytes.try_into().map_err(|_| AspeedEcdsaError::BadInput)?;
-
-            self.sec_wr(0x7c, 0x0100f00b);
-
-            // Reset Engine
-            self.secure.secure0b4().write(|w| w.bits(0));
-            self.secure.secure0b4().write(|w| w.sec_boot_ecceng_enbl().set_bit());
-            self.delay.delay_ns(5000);
-
-            self.load_secp384r1_params();
-
-            self.sec_wr(0x7c, 0x0300f00b);
-
-            // Write qx, qy, r, s
-            self.sram_wr(SRAM_DST_QX, &public_key.qx.0);
-            self.sram_wr(SRAM_DST_QY, &public_key.qy.0);
-            self.sram_wr(SRAM_DST_R, &signature.r.0);
-            self.sram_wr(SRAM_DST_S, &signature.s.0);
-            self.sram_wr(SRAM_DST_M, digest_array);
-
-            self.sec_wr(0x7c, 0);
-
-            // Write ECDSA instruction command
-            self.sram_wr_u32(0x23c0, 1);
-
-            // Trigger ECDSA Engine
-            self.secure.secure0bc().write(|w| w.sec_boot_ecceng_trigger_reg().set_bit());
-            self.delay.delay_ns(5000);
-            self.secure.secure0bc().write(|w| w.sec_boot_ecceng_trigger_reg().clear_bit());
-
-            // Poll
-            let mut retry = 1000;
-            while retry > 0 {
-                let status = self.secure.secure014().read().bits();
-                if status & (1 << 20) != 0 {
-                    return if status & (1 << 21) != 0 {
-                        Ok(())
-                    } else {
-                        Err(AspeedEcdsaError::InvalidSignature)
-                    };
-                }
-                retry -= 1;
-                self.delay.delay_ns(5000);
-            }
-
-            Err(AspeedEcdsaError::Busy)
-        }
-    }
-}

src/main.rs

@@ -11,7 +11,7 @@ use aspeed_ddk::watchdog::WdtController;
 use fugit::MillisDurationU32 as MilliSeconds;
 use aspeed_ddk::hash::Controller;
 use aspeed_ddk::syscon::SysCon;
-use aspeed_ddk::ecdsa::{AspeedEcdsa, Secp384r1Curve};
+use aspeed_ddk::ecdsa::{AspeedEcdsa};
 
 use aspeed_ddk::tests::functional::hash_test::run_hash_tests;
 use aspeed_ddk::tests::functional::ecdsa_test::run_ecdsa_tests;

src/tests/functional/ecdsa_test.rs

@@ -1,7 +1,7 @@
 use crate::uart::UartController;
 use proposed_traits::digest::DigestAlgorithm;
 use proposed_traits::ecdsa::{Curve, EcdsaVerify};
-use crate::ecdsa::{PublicKey, Scalar48, Signature};
+use crate::ecdsa::{PublicKey, Scalar48, Signature, Secp384r1Curve};
 use embedded_io::Write;
 
 use hex_literal::hex;
@@ -103,26 +103,3 @@ pub fn run_ecdsa_tests(uart: &mut UartController, verifier: &mut impl EcdsaVerif
         };
     }
 }
-where
-    C: Curve<Scalar = Scalar48>,
-    C::DigestType: DigestAlgorithm,
-    <C::DigestType as DigestAlgorithm>::DigestOutput: Default + AsRef<[u8]> + AsMut<[u8]>,
-{
-    writeln!(uart, "\r\nRunning ECDSA test").unwrap();
-    for (i, vec) in SECP384R1_TESTVEC.iter().enumerate() {
-        let pubkey = PublicKey { qx: Scalar48(vec.qx), qy: Scalar48(vec.qy) };
-        let sig = Signature { r: Scalar48(vec.r), s: Scalar48(vec.s) };
-        let mut digest = <C::DigestType as DigestAlgorithm>::DigestOutput::default();
-        digest.as_mut().copy_from_slice(&vec.m);
-
-        let result = verifier.verify(&pubkey, digest, &sig);
-
-        writeln!(uart, "\r\nTest case {}... ", i).unwrap();
-
-        let _ = match (result.is_ok(), vec.result) {
-            (true, true) => writeln!(uart, "\rresult expected (pass), Pass"),
-            (false, false) => writeln!(uart, "\rresult expected (fail), Pass"),
-            _ => writeln!(uart, "\rresult unexpected (got {:?}), Failed", result),
-        };
-    }
-}