Skip to content

Commit 63f2a05

Browse files
committed
Figures for README are added
1 parent 8e4030f commit 63f2a05

File tree

3 files changed

+2
-2
lines changed

3 files changed

+2
-2
lines changed

README.md

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -258,7 +258,7 @@ python3 pyverilog/dataflow/graphgen.py -t top -s top.led test.v
258258

259259
Then you got a png file (out.png). The picture shows that the definition of 'led' is a part-selection of 'count' from 23-bit to 16-bit.
260260

261-
![out.png](http://cdn-ak.f.st-hatena.com/images/fotolife/s/sxhxtxa/20140101/20140101045641.png)
261+
![out.png](img/out.png)
262262

263263
Control-flow analyzer
264264
------------------------------
@@ -288,7 +288,7 @@ Loop
288288

289289
You got also a png file (top_state.png). The picture shows that the graphical structure of the state machine.
290290

291-
![top_state.png](http://cdn-ak.f.st-hatena.com/images/fotolife/s/sxhxtxa/20140101/20140101045835.png)
291+
![top_state.png](top_state.png)
292292

293293
Code generator
294294
------------------------------

img/out.png

15.8 KB
Loading

img/top_state.png

9.75 KB
Loading

0 commit comments

Comments
 (0)