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README.rst
@@ -7,7 +7,7 @@ Python-based Hardware Design Processing Toolkit for Verilog HDL
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Copyright (C) 2013, Shinya Takamaeda-Yamazaki
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-E-mail: shinya\_at\_is.naist.jp
+E-mail: takamaeda\_at\_ist.hokudai.ac.jp
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License
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=======
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