SV parse error

[sjalloq]

Hi,

I know the SV support is a work in progress but I thought this syntax was interesting to note.

module module_name import module_name_pkg::*; `MODULE_NAME_PARAM_DECL (

[shtaxxx]

SytemVerilog support is under development on feature_systemverilog branch. Stay tuned!

[ruishihan]

hi,
Is the SV feature still under development now? Is there any rough schedule for releasing this feature?

Thanks & BR