From ccc6a23a616a7b9a7c49e051f2a47b99fd168c8b Mon Sep 17 00:00:00 2001
From: Jiahui Xu <jxu@ethz.ch>
Date: Wed, 19 Mar 2025 00:14:24 +0100
Subject: [PATCH 1/3] git: ignore generated files when installed using
 --editable

---
 .gitignore | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.gitignore b/.gitignore
index 00f9cca..154a829 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,5 @@
 *.pyc
 *.out
 parsetab.py
+build/
+*.egg-info/

From 8e24d2607188a6ed3e3617eea189d8fce3354f3d Mon Sep 17 00:00:00 2001
From: Jiahui Xu <jxu@ethz.ch>
Date: Wed, 19 Mar 2025 00:16:05 +0100
Subject: [PATCH 2/3] parser: fix declassign of regs

in verilog, the statement

```
reg my_reg = 0;
```

is the same as

```
reg my_reg;
initial my_reg = 0;
```

whereas in the current HEAD, the statement above
is translated to
```
reg my_reg; assign my_reg = 0;
```

This commit fixes this bug
---
 pyverilog/vparser/parser.py | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py
index 0de0264..0c98a3e 100644
--- a/pyverilog/vparser/parser.py
+++ b/pyverilog/vparser/parser.py
@@ -628,7 +628,13 @@ def create_declassign(self, sigtypes, name, assign, width=None, lineno=0):
         if 'reg' in sigtypes:
             decls.append(Reg(name=name, width=width,
                              signed=signed, lineno=lineno))
-        decls.append(assign)
+
+        # Declassign of reg is the same as an initial block with blocking
+        # assignment (others are the same as constants).
+        if 'reg' in sigtypes:
+            decls.append(Initial(BlockingSubstitution(*(assign.children()))))
+        else:
+            decls.append(assign)
         return decls
 
     def typecheck_declassign(self, sigtypes):

From 8a4c19287e1fba20c25b6a5a2e5b61ddf41c6caf Mon Sep 17 00:00:00 2001
From: Jiahui Xu <jxu@ethz.ch>
Date: Wed, 19 Mar 2025 00:39:48 +0100
Subject: [PATCH 3/3] fix unclear comment

---
 pyverilog/vparser/parser.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pyverilog/vparser/parser.py b/pyverilog/vparser/parser.py
index 0c98a3e..7bc25f4 100644
--- a/pyverilog/vparser/parser.py
+++ b/pyverilog/vparser/parser.py
@@ -630,7 +630,7 @@ def create_declassign(self, sigtypes, name, assign, width=None, lineno=0):
                              signed=signed, lineno=lineno))
 
         # Declassign of reg is the same as an initial block with blocking
-        # assignment (others are the same as constants).
+        # assignment.
         if 'reg' in sigtypes:
             decls.append(Initial(BlockingSubstitution(*(assign.children()))))
         else: