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shtaxxxshtaxxx
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pipeline.py is updated: the stall condition bug is fixed.
1 parent 4b55024 commit 0098519

27 files changed

+1706
-422
lines changed

‎examples/pipeline_example/pipeline_example.py

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,6 +115,16 @@ def mkTest():
115115
xfsm = FSM(m, 'xfsm', clk, rst)
116116
xfsm.add(vx(0))
117117
xfsm.goto_next(cond=reset_done)
118+
for _ in range(10):
119+
xfsm.goto_next()
120+
xfsm.add(vx(1))
121+
xfsm.goto_next()
122+
xfsm.add(x.inc(), cond=rx)
123+
xfsm.add(x_count.inc(), cond=rx)
124+
xfsm.goto_next(cond=AndList(x_count==5, rx))
125+
xfsm.add(vx(0))
126+
for _ in range(10):
127+
xfsm.goto_next()
118128
xfsm.add(vx(1))
119129
xfsm.add(x.inc(), cond=rx)
120130
xfsm.add(x_count.inc(), cond=rx)
@@ -127,6 +137,7 @@ def mkTest():
127137
yfsm.add(vy(0))
128138
yfsm.goto_next(cond=reset_done)
129139
yfsm.add(vy(1))
140+
yfsm.goto_next()
130141
yfsm.add(y.add(2), cond=ry)
131142
yfsm.add(y_count.inc(), cond=ry)
132143
yfsm.goto_next(cond=AndList(y_count==10, ry))

‎examples/pipeline_example/test_pipeline_example.py

Lines changed: 149 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -4,10 +4,7 @@
44
from veriloggen import *
55

66
expected_verilog = """
7-
module test
8-
(
9-
);
10-
7+
module test;
118
reg CLK;
129
reg RST;
1310
reg [32-1:0] x;
@@ -45,13 +42,15 @@
4542
$dumpvars(0, uut);
4643
end
4744
45+
4846
initial begin
4947
CLK = 0;
5048
forever begin
51-
#5 CLK = (!CLK);
49+
#5 CLK = !CLK;
5250
end
5351
end
5452
53+
5554
initial begin
5655
RST = 0;
5756
reset_done = 0;
@@ -79,6 +78,28 @@
7978
localparam xfsm_init = 0;
8079
localparam xfsm_1 = 1;
8180
localparam xfsm_2 = 2;
81+
localparam xfsm_3 = 3;
82+
localparam xfsm_4 = 4;
83+
localparam xfsm_5 = 5;
84+
localparam xfsm_6 = 6;
85+
localparam xfsm_7 = 7;
86+
localparam xfsm_8 = 8;
87+
localparam xfsm_9 = 9;
88+
localparam xfsm_10 = 10;
89+
localparam xfsm_11 = 11;
90+
localparam xfsm_12 = 12;
91+
localparam xfsm_13 = 13;
92+
localparam xfsm_14 = 14;
93+
localparam xfsm_15 = 15;
94+
localparam xfsm_16 = 16;
95+
localparam xfsm_17 = 17;
96+
localparam xfsm_18 = 18;
97+
localparam xfsm_19 = 19;
98+
localparam xfsm_20 = 20;
99+
localparam xfsm_21 = 21;
100+
localparam xfsm_22 = 22;
101+
localparam xfsm_23 = 23;
102+
localparam xfsm_24 = 24;
82103
83104
always @(posedge CLK) begin
84105
if(RST) begin
@@ -93,18 +114,94 @@
93114
end
94115
end
95116
xfsm_1: begin
117+
xfsm <= xfsm_2;
118+
end
119+
xfsm_2: begin
120+
xfsm <= xfsm_3;
121+
end
122+
xfsm_3: begin
123+
xfsm <= xfsm_4;
124+
end
125+
xfsm_4: begin
126+
xfsm <= xfsm_5;
127+
end
128+
xfsm_5: begin
129+
xfsm <= xfsm_6;
130+
end
131+
xfsm_6: begin
132+
xfsm <= xfsm_7;
133+
end
134+
xfsm_7: begin
135+
xfsm <= xfsm_8;
136+
end
137+
xfsm_8: begin
138+
xfsm <= xfsm_9;
139+
end
140+
xfsm_9: begin
141+
xfsm <= xfsm_10;
142+
end
143+
xfsm_10: begin
144+
xfsm <= xfsm_11;
145+
end
146+
xfsm_11: begin
96147
vx <= 1;
148+
xfsm <= xfsm_12;
149+
end
150+
xfsm_12: begin
97151
if(rx) begin
98-
x <= (x + 1);
152+
x <= x + 1;
99153
end
100154
if(rx) begin
101-
_tmp_0 <= (_tmp_0 + 1);
155+
_tmp_0 <= _tmp_0 + 1;
102156
end
103-
if(((_tmp_0 == 10) && rx)) begin
104-
xfsm <= xfsm_2;
157+
if((_tmp_0 == 5) && rx) begin
158+
xfsm <= xfsm_13;
105159
end
106160
end
107-
xfsm_2: begin
161+
xfsm_13: begin
162+
vx <= 0;
163+
xfsm <= xfsm_14;
164+
end
165+
xfsm_14: begin
166+
xfsm <= xfsm_15;
167+
end
168+
xfsm_15: begin
169+
xfsm <= xfsm_16;
170+
end
171+
xfsm_16: begin
172+
xfsm <= xfsm_17;
173+
end
174+
xfsm_17: begin
175+
xfsm <= xfsm_18;
176+
end
177+
xfsm_18: begin
178+
xfsm <= xfsm_19;
179+
end
180+
xfsm_19: begin
181+
xfsm <= xfsm_20;
182+
end
183+
xfsm_20: begin
184+
xfsm <= xfsm_21;
185+
end
186+
xfsm_21: begin
187+
xfsm <= xfsm_22;
188+
end
189+
xfsm_22: begin
190+
xfsm <= xfsm_23;
191+
end
192+
xfsm_23: begin
193+
vx <= 1;
194+
if(rx) begin
195+
x <= x + 1;
196+
end
197+
if(rx) begin
198+
_tmp_0 <= _tmp_0 + 1;
199+
end
200+
if((_tmp_0 == 10) && rx) begin
201+
xfsm <= xfsm_24;
202+
end
203+
end
204+
xfsm_24: begin
108205
vx <= 0;
109206
end
110207
endcase
@@ -115,6 +212,7 @@
115212
localparam yfsm_init = 0;
116213
localparam yfsm_1 = 1;
117214
localparam yfsm_2 = 2;
215+
localparam yfsm_3 = 3;
118216
119217
always @(posedge CLK) begin
120218
if(RST) begin
@@ -130,17 +228,20 @@
130228
end
131229
yfsm_1: begin
132230
vy <= 1;
231+
yfsm <= yfsm_2;
232+
end
233+
yfsm_2: begin
133234
if(ry) begin
134-
y <= (y + 2);
235+
y <= y + 2;
135236
end
136237
if(ry) begin
137-
_tmp_1 <= (_tmp_1 + 1);
238+
_tmp_1 <= _tmp_1 + 1;
138239
end
139-
if(((_tmp_1 == 10) && ry)) begin
140-
yfsm <= yfsm_2;
240+
if((_tmp_1 == 10) && ry) begin
241+
yfsm <= yfsm_3;
141242
end
142243
end
143-
yfsm_2: begin
244+
yfsm_3: begin
144245
vy <= 0;
145246
end
146247
endcase
@@ -232,22 +333,24 @@
232333
end
233334
end
234335
336+
235337
always @(posedge CLK) begin
236338
if(reset_done) begin
237-
if((vx && rx)) begin
339+
if(vx && rx) begin
238340
$display("x=%d", x);
239341
end
240-
if((vy && ry)) begin
342+
if(vy && ry) begin
241343
$display("y=%d", y);
242344
end
243-
if((vz && rz)) begin
345+
if(vz && rz) begin
244346
$display("z=%d", z);
245347
end
246348
end
247349
end
248350
249351
endmodule
250352
353+
251354
module multadd
252355
(
253356
input CLK,
@@ -264,16 +367,16 @@
264367
input rz
265368
);
266369
267-
assign rx = (_df_ready_0 || (!_df_valid_0));
268-
assign ry = (_df_ready_1 || (!_df_valid_1));
370+
assign rx = (_df_ready_0 || !_df_valid_0) && vx;
371+
assign ry = (_df_ready_1 || !_df_valid_1) && vy;
269372
reg [32-1:0] _df_data_0;
270373
reg _df_valid_0;
271374
wire _df_ready_0;
272-
assign _df_ready_0 = (_df_ready_2 || (!_df_valid_2));
375+
assign _df_ready_0 = (_df_ready_2 || !_df_valid_2) && (_df_valid_0 && _df_valid_1);
273376
reg [32-1:0] _df_data_1;
274377
reg _df_valid_1;
275378
wire _df_ready_1;
276-
assign _df_ready_1 = (_df_ready_2 || (!_df_valid_2));
379+
assign _df_ready_1 = (_df_ready_2 || !_df_valid_2) && (_df_valid_0 && _df_valid_1);
277380
reg [32-1:0] _df_data_2;
278381
reg _df_valid_2;
279382
wire _df_ready_2;
@@ -290,36 +393,49 @@
290393
_df_data_2 <= 0;
291394
_df_valid_2 <= 0;
292395
end else begin
293-
if(((vx && rx) && (_df_ready_0 || (!_df_valid_0)))) begin
294-
_df_data_0 <= (x * c);
396+
if(vx && rx && (_df_ready_0 || !_df_valid_0)) begin
397+
_df_data_0 <= x * c;
398+
end
399+
if(_df_valid_0 && _df_ready_0) begin
400+
_df_valid_0 <= 0;
295401
end
296-
if((_df_ready_0 || (!_df_valid_0))) begin
297-
_df_valid_0 <= (vx && rx);
402+
if(rx && (_df_ready_0 || !_df_valid_0)) begin
403+
_df_valid_0 <= vx;
298404
end
299-
if(((vy && ry) && (_df_ready_1 || (!_df_valid_1)))) begin
405+
if(vy && ry && (_df_ready_1 || !_df_valid_1)) begin
300406
_df_data_1 <= y;
301407
end
302-
if((_df_ready_1 || (!_df_valid_1))) begin
303-
_df_valid_1 <= (vy && ry);
408+
if(_df_valid_1 && _df_ready_1) begin
409+
_df_valid_1 <= 0;
410+
end
411+
if(ry && (_df_ready_1 || !_df_valid_1)) begin
412+
_df_valid_1 <= vy;
304413
end
305-
if((((_df_valid_0 && _df_ready_0) && (_df_valid_1 && _df_ready_1)) && (_df_ready_2 || (!_df_valid_2)))) begin
306-
_df_data_2 <= (_df_data_0 + _df_data_1);
414+
if(_df_valid_0 && _df_valid_1 && (_df_ready_0 && _df_ready_1) && (_df_ready_2 || !_df_valid_2)) begin
415+
_df_data_2 <= _df_data_0 + _df_data_1;
307416
end
308-
if((_df_ready_2 || (!_df_valid_2))) begin
309-
_df_valid_2 <= ((_df_valid_0 && _df_ready_0) && (_df_valid_1 && _df_ready_1));
417+
if(_df_valid_2 && _df_ready_2) begin
418+
_df_valid_2 <= 0;
419+
end
420+
if(_df_ready_0 && _df_ready_1 && (_df_ready_2 || !_df_valid_2)) begin
421+
_df_valid_2 <= _df_valid_0 && _df_valid_1;
310422
end
311423
end
312424
end
313425
426+
314427
endmodule
315428
"""
316429

317430
expected_rslt = """\
318431
VCD info: dumpfile uut.vcd opened for output.
432+
y= 0
433+
x= 0
319434
x= 1
320435
y= 2
321436
x= 2
322437
y= 4
438+
z= 0
323439
x= 3
324440
y= 6
325441
z= 10

‎examples/pipeline_multiple_add/pipeline_multiple_add.py

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -106,6 +106,7 @@ def mkTest(numports=8):
106106
fsm.add(v(0))
107107
fsm.goto_next(cond=reset_done)
108108
fsm.add(v(1))
109+
fsm.goto_next()
109110
fsm.add(d(d + i + 1), cond=r)
110111
fsm.add(count.inc(), cond=r)
111112
fsm.goto_next(cond=AndList(count==10, r))

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