Merge branch 'develop' into feature_fsm_extension

Author: shtaxxx

.github/workflows/main.yml

@@ -0,0 +1,44 @@
+name: CI
+
+# Controls when the workflow will run
+on:
+  # Triggers the workflow on push or pull request events but only for the develop branch
+  push:
+    branches-ignore: [ feature_systemverilog ]
+  pull_request:
+    branches-ignore: [ feature_systemverilog ]
+
+  # Allows you to run this workflow manually from the Actions tab
+  workflow_dispatch:
+
+# A workflow run is made up of one or more jobs that can run sequentially or in parallel
+jobs:
+  # This workflow contains a single job called "build"
+  build:
+    # The type of runner that the job will run on
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        python-version: [3.7, 3.8, 3.9]
+
+    # Steps represent a sequence of tasks that will be executed as part of the job
+    steps:
+      # Checks-out your repository under $GITHUB_WORKSPACE, so your job can access it
+      - uses: actions/checkout@v2
+      # Setup Python
+      - name: Set up Python ${{ matrix.python-version }}
+        uses: actions/setup-python@v2
+        with:
+          python-version: ${{ matrix.python-version }}
+      # Install apt dependencies
+      - name: Install apt dependencies
+        run: sudo apt install iverilog verilator
+      # Install dependencies
+      - name: Install dependencies
+        run: |
+          python -m pip install --upgrade pip
+          pip install pytest pytest-pythonpath pyverilog numpy
+      # Run pytest
+      - name: Test with pytest
+        run: |
+          python -m pytest tests examples

README.md

@@ -1,7 +1,8 @@
 Veriloggen
 ==============================
 
-[![Build Status](https://www.travis-ci.com/PyHDI/veriloggen.svg?branch=develop)](https://www.travis-ci.com/github/PyHDI/veriloggen)
+[![CI](https://github.com/PyHDI/veriloggen/actions/workflows/main.yml/badge.svg?branch=develop)](https://github.com/PyHDI/veriloggen/actions/workflows/main.yml)
+[![Build Status](https://www.travis-ci.com/PyHDI/veriloggen.svg?branch=develop)](https://www.travis-ci.com/PyHDI/veriloggen)
 
 A Mixed-Paradigm Hardware Construction Framework