In FSM and Seq, Else is realized as a property, and actual Else operation is synthesized when add() is called. So FSM.goto() and related methods can use Else condition, as well as value assignment.

Author: shtaxxx

tests/extension/fsm_/state/Makefile

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+TARGET=$(shell ls *.py | grep -v test | grep -v parsetab.py)
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py .cache *.out *.png *.dot tmp.v uut.vcd

tests/extension/fsm_/state/fsm_state.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import sys
+import os
+
+# the next line can be removed after installation
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(
+    os.path.dirname(os.path.dirname(os.path.abspath(__file__)))))))
+
+from veriloggen import *
+
+
+def mkLed():
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    valid = m.OutputReg('valid', initval=0)
+    counter = m.Reg('counter', 8, initval=0)
+
+    fsm = FSM(m, 'fsm', clk, rst)
+
+    s0 = fsm.init  # -> State(fsm, 0)
+    s1 = s0.If(valid).goto_next()  # -> State(fsm, 1)
+    s2 = s1.If(valid).goto_next()  # -> State(fsm, 2)
+    s3 = s2.If(counter[0] == 0).goto(s2.next)  # -> State(fsm, 3)
+    s1_ = s2.Elif(counter[1] == 1).goto(s1)  # -> State(fsm, 1)
+    s2_ = s2.Else.goto(s2)  # -> State(fsm, 2)
+    s0_ = s3.goto(s0)  # -> State(fsm, 0)
+
+    fsm.Always.If(counter <= 2 ** 8 - 1)(
+        counter.inc()
+    ).Else(
+        counter(0)
+    )
+
+    s0.If(counter == 10)(
+        valid(0)
+    )
+    s0.Else(
+        valid(1)
+    )
+
+    s1.If(counter == 20)(
+        valid(0)
+    )
+    s1.Else(
+        valid(1)
+    )
+
+    s2.If(counter == 30)(
+        valid(0)
+    )
+    s2.Else(
+        valid(1)
+    )
+
+    s0_.If(counter == 40)(
+        valid(0)
+    )
+    s0_.Else(
+        valid(1)
+    )
+
+    return m
+
+
+def mkTest():
+    m = Module('test')
+    clk = m.Reg('CLK')
+    rst = m.Reg('RST')
+    valid = m.Wire('valid')
+
+    uut = m.Instance(mkLed(), 'uut',
+                     ports=(('CLK', clk), ('RST', rst), ('valid', valid)))
+
+    # simulation.setup_waveform(m, uut)
+    simulation.setup_clock(m, clk, hperiod=5)
+    init = simulation.setup_reset(m, rst, period=100)
+
+    init.add(
+        Delay(1000),
+        Systask('finish'),
+    )
+
+    return m
+
+
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)

tests/extension/fsm_/state/test_fsm_state.py

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+from __future__ import absolute_import
+from __future__ import print_function
+import veriloggen
+import fsm_state
+
+expected_verilog = """
+module test;
+
+  reg CLK;
+  reg RST;
+  wire valid;
+
+  blinkled
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .valid(valid)
+  );
+
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = !CLK;
+    end
+  end
+
+
+  initial begin
+    RST = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #1000;
+    $finish;
+  end
+
+
+endmodule
+
+
+
+module blinkled
+(
+  input CLK,
+  input RST,
+  output reg valid
+);
+
+  reg [8-1:0] counter;
+  reg [32-1:0] fsm;
+  localparam fsm_init = 0;
+  localparam fsm_1 = 1;
+  localparam fsm_2 = 2;
+  localparam fsm_3 = 3;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      fsm <= fsm_init;
+      valid <= 0;
+      counter <= 0;
+    end else begin
+      if(counter <= 255) begin
+        counter <= counter + 1;
+      end else begin
+        counter <= 0;
+      end
+      case(fsm)
+        fsm_init: begin
+          if(counter == 10) begin
+            valid <= 0;
+          end else begin
+            valid <= 1;
+          end
+          if(counter == 40) begin
+            valid <= 0;
+          end else begin
+            valid <= 1;
+          end
+          if(valid) begin
+            fsm <= fsm_1;
+          end 
+        end
+        fsm_1: begin
+          if(counter == 20) begin
+            valid <= 0;
+          end else begin
+            valid <= 1;
+          end
+          if(valid) begin
+            fsm <= fsm_2;
+          end 
+        end
+        fsm_2: begin
+          if(counter == 30) begin
+            valid <= 0;
+          end else begin
+            valid <= 1;
+          end
+          if(counter[0] == 0) begin
+            fsm <= fsm_3;
+          end 
+          if(!(counter[0] == 0) && (counter[1] == 1)) begin
+            fsm <= fsm_1;
+          end 
+          if(!(counter[0] == 0) && !(counter[1] == 1)) begin
+            fsm <= fsm_2;
+          end 
+        end
+        fsm_3: begin
+          fsm <= fsm_init;
+        end
+      endcase
+    end
+  end
+
+
+endmodule
+"""
+
+
+def test():
+    veriloggen.reset()
+    test_module = fsm_state.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)