lib_parallel is added: parallel substituion manager

Author: shtaxxx

sample/tests/lib_parallel/Makefile

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+.PHONY: clean
+clean:
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make clean -C {} 
+
+.PHONY: test
+test:
+	find . -maxdepth 1 -type d |grep "./" | xargs -I {} make test -C {} 

sample/tests/lib_parallel/adder/Makefile

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+TARGET=led.py
+TEST=test_led.py
+ARGS=
+
+PYTHON=python3
+#PYTHON=python
+#OPT=-m pdb
+#OPT=-m cProfile -s time
+#OPT=-m cProfile -o profile.rslt
+
+.PHONY: all
+all: test
+
+.PHONY: run
+run:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS)
+
+.PHONY: test
+test:
+	$(PYTHON) -m pytest -vv $(TEST)
+
+.PHONY: check
+check:
+	$(PYTHON) $(OPT) $(TARGET) $(ARGS) > tmp.v
+	iverilog -tnull -Wall tmp.v
+	rm -f tmp.v
+
+.PHONY: clean
+clean:
+	rm -rf *.pyc __pycache__ parsetab.py *.out tmp.v uut.vcd
+
+.PHONY: sim
+sim:
+	iverilog -Wall tmp.v
+	./a.out
+
+.PHONY: view
+view:
+	gtkwave --giga uut.vcd &

sample/tests/lib_parallel/adder/led.py

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+import sys
+import os
+import math
+
+from veriloggen import *
+
+try:
+    log2 = math.log2
+except:
+    def log2(v):
+        return math.log(v, 2)
+
+def mkLed(numports=4):
+    if log2(numports) % 1.0 != 0.0:
+        raise ValueError('numports must be power of 2')
+    
+    m = Module('blinkled')
+    clk = m.Input('CLK')
+    rst = m.Input('RST')
+    
+    idata = [ m.Input('idata' + str(i), 32) for i in range(numports) ]
+    ivalid = [ m.Input('ivalid' + str(i)) for i in range(numports) ]
+    odata = m.OutputReg('odata', 32, initval=0)
+    ovalid = m.OutputReg('ovalid', initval=0)
+
+    par = lib.Parallel(m, 'par')
+    pdata = idata
+    pvalid = ivalid
+    ndata = []
+    nvalid = []
+    
+    for s in range( int(log2(numports)) ):
+        for i in range( numports >> (s+1) ):
+            td = m.TmpReg(32, initval=0)
+            tv = m.TmpReg(initval=0)
+            ndata.append(td)
+            nvalid.append(tv)
+            cond = AndList(pvalid[i*2], pvalid[i*2+1])
+            par.add( tv(cond) )
+            par.add( td(pdata[i*2] + pdata[i*2+1]), cond=cond )
+        pdata = ndata
+        pvalid = nvalid
+
+    par.add( odata(pdata[-1]) )
+    par.add( ovalid(pvalid[-1]) )
+        
+    par.make_always(clk, rst)
+
+    return m
+
+def mkTest():
+    m = Module('test')
+
+    # target instance
+    led = mkLed()
+    
+    # copy paras and ports
+    params = m.copy_params(led)
+    ports = m.copy_sim_ports(led)
+
+    clk = ports['CLK']
+    rst = ports['RST']
+    idata = [ p for k, p in sorted(ports.items(), key=lambda x:x[0]) if k.startswith('idata') ]
+    ivalid = [ p for k, p in sorted(ports.items(), key=lambda x:x[0]) if k.startswith('ivalid') ]
+    
+    uut = m.Instance(led, 'uut',
+                     params=m.connect_params(led),
+                     ports=m.connect_ports(led))
+
+    reset_stmt = []
+    for d in idata:
+        reset_stmt.append( d(0) )
+    for v in ivalid:
+        reset_stmt.append( v(0) )
+    
+    lib.simulation.setup_waveform(m, uut)
+    lib.simulation.setup_clock(m, clk, hperiod=5)
+    init = lib.simulation.setup_reset(m, rst, reset_stmt, period=100)
+
+    nclk = lib.simulation.next_clock
+    
+    init.add(
+        Delay(1000),
+        nclk(clk),
+        
+        [ d(0) for d in idata ],
+        [ v(0) for v in ivalid ],
+        nclk(clk),
+        
+        [ d(i+1) for i, d in enumerate(idata) ],
+        [ v(1) for v in ivalid ],
+        nclk(clk),
+        
+        [ d(1) for d in idata ],
+        [ v(0) for v in ivalid ],
+        nclk(clk),
+        
+        [ d(i+10) for i, d in enumerate(idata) ],
+        [ v(1) for v in ivalid ],
+        nclk(clk),
+        
+        [ v(0) for v in ivalid ],
+        [ nclk(clk) for _ in range(10) ],
+        
+        Systask('finish'),
+    )
+
+    return m
+    
+if __name__ == '__main__':
+    test = mkTest()
+    verilog = test.to_verilog('tmp.v')
+    print(verilog)

sample/tests/lib_parallel/adder/test_led.py

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+import led
+
+expected_verilog = """
+module test;
+  reg CLK;
+  reg RST;
+  reg [32-1:0] idata0;
+  reg [32-1:0] idata1;
+  reg [32-1:0] idata2;
+  reg [32-1:0] idata3;
+  reg ivalid0;
+  reg ivalid1;
+  reg ivalid2;
+  reg ivalid3;
+  wire [32-1:0] odata;
+  wire ovalid;
+
+  blinkled
+  uut
+  (
+    .CLK(CLK),
+    .RST(RST),
+    .idata0(idata0),
+    .idata1(idata1),
+    .idata2(idata2),
+    .idata3(idata3),
+    .ivalid0(ivalid0),
+    .ivalid1(ivalid1),
+    .ivalid2(ivalid2),
+    .ivalid3(ivalid3),
+    .odata(odata),
+    .ovalid(ovalid)
+  );
+
+  initial begin
+    $dumpfile("uut.vcd");
+    $dumpvars(0, uut);
+  end
+
+  initial begin
+    CLK = 0;
+    forever begin
+      #5 CLK = (!CLK);
+    end
+  end
+
+  initial begin
+    RST = 0;
+    idata0 = 0;
+    idata1 = 0;
+    idata2 = 0;
+    idata3 = 0;
+    ivalid0 = 0;
+    ivalid1 = 0;
+    ivalid2 = 0;
+    ivalid3 = 0;
+    #100;
+    RST = 1;
+    #100;
+    RST = 0;
+    #1000;
+    @(posedge CLK);
+    #1;
+    idata0 = 0;
+    idata1 = 0;
+    idata2 = 0;
+    idata3 = 0;
+    ivalid0 = 0;
+    ivalid1 = 0;
+    ivalid2 = 0;
+    ivalid3 = 0;
+    @(posedge CLK);
+    #1;
+    idata0 = 1;
+    idata1 = 2;
+    idata2 = 3;
+    idata3 = 4;
+    ivalid0 = 1;
+    ivalid1 = 1;
+    ivalid2 = 1;
+    ivalid3 = 1;
+    @(posedge CLK);
+    #1;
+    idata0 = 1;
+    idata1 = 1;
+    idata2 = 1;
+    idata3 = 1;
+    ivalid0 = 0;
+    ivalid1 = 0;
+    ivalid2 = 0;
+    ivalid3 = 0;
+    @(posedge CLK);
+    #1;
+    idata0 = 10;
+    idata1 = 11;
+    idata2 = 12;
+    idata3 = 13;
+    ivalid0 = 1;
+    ivalid1 = 1;
+    ivalid2 = 1;
+    ivalid3 = 1;
+    @(posedge CLK);
+    #1;
+    ivalid0 = 0;
+    ivalid1 = 0;
+    ivalid2 = 0;
+    ivalid3 = 0;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    @(posedge CLK);
+    #1;
+    $finish;
+  end
+
+endmodule
+
+module blinkled
+  (
+   input CLK,
+   input RST,
+   input [32-1:0] idata0,
+   input [32-1:0] idata1,
+   input [32-1:0] idata2,
+   input [32-1:0] idata3,
+   input ivalid0,
+   input ivalid1,
+   input ivalid2,
+   input ivalid3,
+   output reg [32-1:0] odata,
+   output reg ovalid
+  );
+
+  reg [32-1:0] _tmp_0;
+  reg _tmp_1;
+  reg [32-1:0] _tmp_2;
+  reg _tmp_3;
+  reg [32-1:0] _tmp_4;
+  reg _tmp_5;
+
+  always @(posedge CLK) begin
+    if(RST) begin
+      odata <= 0;
+      ovalid <= 0;
+      _tmp_0 <= 0;
+      _tmp_1 <= 0;
+      _tmp_2 <= 0;
+      _tmp_3 <= 0;
+      _tmp_4 <= 0;
+      _tmp_5 <= 0;
+    end else begin
+      _tmp_1 <= ivalid0 && ivalid1;
+      if(ivalid0 && ivalid1) begin
+        _tmp_0 <= idata0 + idata1;
+      end 
+      _tmp_3 <= ivalid2 && ivalid3;
+      if(ivalid2 && ivalid3) begin
+        _tmp_2 <= idata2 + idata3;
+      end 
+      _tmp_5 <= _tmp_1 && _tmp_3;
+      if(_tmp_1 && _tmp_3) begin
+        _tmp_4 <= _tmp_0 + _tmp_2;
+      end 
+      odata <= _tmp_4;
+      ovalid <= _tmp_5;
+    end
+  end
+
+endmodule
+"""
+
+def test_led():
+    test_module = led.mkTest()
+    code = test_module.to_verilog()
+
+    from pyverilog.vparser.parser import VerilogParser
+    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
+    parser = VerilogParser()
+    expected_ast = parser.parse(expected_verilog)
+    codegen = ASTCodeGenerator()
+    expected_code = codegen.visit(expected_ast)
+
+    assert(expected_code == code)

sample/tests/lib_parallel/adder/veriloggen

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+../../../../veriloggen