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| 1 | +from __future__ import absolute_import |
| 2 | +from __future__ import print_function |
| 3 | +import sys |
| 4 | +import os |
| 5 | + |
| 6 | +# the next line can be removed after installation |
| 7 | +sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname( |
| 8 | + os.path.dirname(os.path.dirname(os.path.abspath(__file__))))))) |
| 9 | + |
| 10 | +from veriloggen import * |
| 11 | +import veriloggen.thread as vthread |
| 12 | +import veriloggen.types.axi as axi |
| 13 | + |
| 14 | + |
| 15 | +def mkLed(): |
| 16 | + m = Module('blinkled') |
| 17 | + clk = m.Input('CLK') |
| 18 | + rst = m.Input('RST') |
| 19 | + |
| 20 | + datawidth = 32 |
| 21 | + addrwidth = 10 |
| 22 | + myaxi = vthread.AXIM(m, 'myaxi', clk, rst, datawidth) |
| 23 | + ram_a = vthread.RAM(m, 'ram_a', clk, rst, datawidth, addrwidth) |
| 24 | + ram_b = vthread.RAM(m, 'ram_b', clk, rst, datawidth, addrwidth) |
| 25 | + ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth) |
| 26 | + |
| 27 | + strm = vthread.Stream(m, 'mystream', clk, rst) |
| 28 | + a = strm.source('a') |
| 29 | + b = strm.source('b') |
| 30 | + bias = strm.constant('bias') |
| 31 | + c = a * b + bias |
| 32 | + strm.sink(c, 'c') |
| 33 | + |
| 34 | + def comp_stream(size, offset): |
| 35 | + strm.set_source('a', ram_a, offset, size) |
| 36 | + strm.set_source('b', ram_b, offset, size) |
| 37 | + strm.set_constant('bias', 10) |
| 38 | + strm.set_sink('c', ram_c, offset, size) |
| 39 | + strm.run() |
| 40 | + |
| 41 | + # double buffer of comp and cmd |
| 42 | + strm.set_source('a', ram_a, offset + size, size) |
| 43 | + strm.set_source('b', ram_b, offset + size, size) |
| 44 | + strm.set_constant('bias', 100) |
| 45 | + strm.set_sink('c', ram_c, offset + size, size) |
| 46 | + strm.source_join() |
| 47 | + |
| 48 | + strm.run() |
| 49 | + |
| 50 | + # double buffer of comp and cmd |
| 51 | + strm.set_source('a', ram_a, offset + size + size, size) |
| 52 | + strm.set_source('b', ram_b, offset + size + size, size) |
| 53 | + strm.set_constant('bias', 1000) |
| 54 | + strm.set_sink('c', ram_c, offset + size + size, size) |
| 55 | + strm.source_join() |
| 56 | + |
| 57 | + strm.run() |
| 58 | + |
| 59 | + strm.source_join() |
| 60 | + strm.sink_join() |
| 61 | + |
| 62 | + def comp_sequential(size, offset): |
| 63 | + sum = 0 |
| 64 | + for i in range(size): |
| 65 | + a = ram_a.read(i + offset) |
| 66 | + b = ram_b.read(i + offset) |
| 67 | + sum = a * b + 10 |
| 68 | + ram_c.write(i + offset, sum) |
| 69 | + |
| 70 | + for i in range(size): |
| 71 | + a = ram_a.read(i + offset + size) |
| 72 | + b = ram_b.read(i + offset + size) |
| 73 | + sum = a * b + 100 |
| 74 | + ram_c.write(i + offset + size, sum) |
| 75 | + |
| 76 | + for i in range(size): |
| 77 | + a = ram_a.read(i + offset + size + size) |
| 78 | + b = ram_b.read(i + offset + size + size) |
| 79 | + sum = a * b + 1000 |
| 80 | + ram_c.write(i + offset + size + size, sum) |
| 81 | + |
| 82 | + def check(size, offset_stream, offset_seq): |
| 83 | + all_ok = True |
| 84 | + for i in range(size): |
| 85 | + st = ram_c.read(i + offset_stream) |
| 86 | + sq = ram_c.read(i + offset_seq) |
| 87 | + if vthread.verilog.NotEql(st, sq): |
| 88 | + all_ok = False |
| 89 | + if all_ok: |
| 90 | + print('# verify: PASSED') |
| 91 | + else: |
| 92 | + print('# verify: FAILED') |
| 93 | + |
| 94 | + def comp(size): |
| 95 | + new_size = size + size + size |
| 96 | + offset = 0 |
| 97 | + myaxi.dma_read(ram_a, offset, 0, new_size) |
| 98 | + myaxi.dma_read(ram_b, offset, 512, new_size) |
| 99 | + comp_stream(size, offset) |
| 100 | + myaxi.dma_write(ram_c, offset, 1024, new_size) |
| 101 | + |
| 102 | + offset = new_size |
| 103 | + myaxi.dma_read(ram_a, offset, 0, new_size) |
| 104 | + myaxi.dma_read(ram_b, offset, 512, new_size) |
| 105 | + comp_sequential(size, offset) |
| 106 | + myaxi.dma_write(ram_c, offset, 1024 * 2, new_size) |
| 107 | + |
| 108 | + check(new_size, 0, offset) |
| 109 | + |
| 110 | + vthread.finish() |
| 111 | + |
| 112 | + th = vthread.Thread(m, 'th_comp', clk, rst, comp) |
| 113 | + fsm = th.start(32) |
| 114 | + |
| 115 | + return m |
| 116 | + |
| 117 | + |
| 118 | +def mkTest(memimg_name=None): |
| 119 | + m = Module('test') |
| 120 | + |
| 121 | + # target instance |
| 122 | + led = mkLed() |
| 123 | + |
| 124 | + # copy paras and ports |
| 125 | + params = m.copy_params(led) |
| 126 | + ports = m.copy_sim_ports(led) |
| 127 | + |
| 128 | + clk = ports['CLK'] |
| 129 | + rst = ports['RST'] |
| 130 | + |
| 131 | + memory = axi.AxiMemoryModel(m, 'memory', clk, rst, memimg_name=memimg_name) |
| 132 | + memory.connect(ports, 'myaxi') |
| 133 | + |
| 134 | + uut = m.Instance(led, 'uut', |
| 135 | + params=m.connect_params(led), |
| 136 | + ports=m.connect_ports(led)) |
| 137 | + |
| 138 | + # simulation.setup_waveform(m, uut) |
| 139 | + simulation.setup_clock(m, clk, hperiod=5) |
| 140 | + init = simulation.setup_reset(m, rst, m.make_reset(), period=100) |
| 141 | + |
| 142 | + init.add( |
| 143 | + Delay(1000000), |
| 144 | + Systask('finish'), |
| 145 | + ) |
| 146 | + |
| 147 | + return m |
| 148 | + |
| 149 | + |
| 150 | +def run(filename='tmp.v', simtype='iverilog', outputfile=None): |
| 151 | + |
| 152 | + if outputfile is None: |
| 153 | + outputfile = os.path.splitext(os.path.basename(__file__))[0] + '.out' |
| 154 | + |
| 155 | + memimg_name = 'memimg_' + outputfile |
| 156 | + |
| 157 | + test = mkTest(memimg_name=memimg_name) |
| 158 | + |
| 159 | + if filename is not None: |
| 160 | + test.to_verilog(filename) |
| 161 | + |
| 162 | + sim = simulation.Simulator(test, sim=simtype) |
| 163 | + rslt = sim.run(outputfile=outputfile) |
| 164 | + lines = rslt.splitlines() |
| 165 | + if simtype == 'verilator' and lines[-1].startswith('-'): |
| 166 | + rslt = '\n'.join(lines[:-1]) |
| 167 | + return rslt |
| 168 | + |
| 169 | + |
| 170 | +if __name__ == '__main__': |
| 171 | + rslt = run(filename='tmp.v') |
| 172 | + print(rslt) |
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