@@ -8,6 +8,8 @@ function source_entry_to_configs(::Cross{false})
88 return Dict(Pair{Int64, Vector{BitVector}}[5 => [[1, 0, 0, 1, 0, 0, 1, 0, 1], [1, 0, 1, 0, 0, 0, 1, 0, 1]], 12 => [[0, 1, 0, 0, 1, 0, 1, 0, 1], [0, 0, 1, 0, 1, 0, 1, 0, 1]], 8 => [[0, 1, 0, 0, 1, 0, 0, 1, 0], [0, 0, 1, 0, 1, 0, 0, 1, 0], [0, 1, 0, 0, 1, 0, 1, 0, 0], [0, 0, 1, 0, 1, 0, 1, 0, 0]], 1 => [[1, 0, 0, 1, 0, 0, 0, 1, 0], [1, 0, 1, 0, 0, 0, 0, 1, 0], [1, 0, 0, 1, 0, 0, 1, 0, 0], [1, 0, 1, 0, 0, 0, 1, 0, 0]], 0 => [[0, 1, 0, 1, 0, 0, 0, 1, 0], [0, 1, 0, 1, 0, 0, 1, 0, 0]], 6 => [[0, 1, 0, 1, 0, 1, 0, 0, 1]], 11 => [[1, 0, 1, 0, 1, 1, 0, 1, 0]], 9 => [[1, 0, 1, 0, 1, 0, 0, 1, 0], [1, 0, 1, 0, 1, 0, 1, 0, 0]], 14 => [[0, 1, 0, 0, 1, 1, 0, 0, 1], [0, 0, 1, 0, 1, 1, 0, 0, 1]], 3 => [[1, 0, 0, 1, 0, 1, 0, 1, 0], [1, 0, 1, 0, 0, 1, 0, 1, 0]], 7 => [[1, 0, 0, 1, 0, 1, 0, 0, 1], [1, 0, 1, 0, 0, 1, 0, 0, 1]], 4 => [[0, 1, 0, 1, 0, 0, 1, 0, 1]], 13 => [[1, 0, 1, 0, 1, 0, 1, 0, 1]], 15 => [[1, 0, 1, 0, 1, 1, 0, 0, 1]], 2 => [[0, 1, 0, 1, 0, 1, 0, 1, 0]], 10 => [[0, 1, 0, 0, 1, 1, 0, 1, 0], [0, 0, 1, 0, 1, 1, 0, 1, 0]]])
99end
1010
11+ mis_overhead (:: Cross{false} ) = - 1.0
12+
1113
1214function mapped_entry_to_compact (:: Cross{true} )
1315 return Dict ([5 => 5 , 12 => 12 , 8 => 0 , 1 => 0 , 0 => 0 , 6 => 6 , 11 => 11 , 9 => 9 , 14 => 14 , 3 => 3 , 7 => 7 , 4 => 0 , 13 => 13 , 15 => 15 , 2 => 0 , 10 => 10 ])
@@ -17,42 +19,52 @@ function source_entry_to_configs(::Cross{true})
1719 return Dict (Pair{Int64, Vector{BitVector}}[5 => [], 12 => [[0 , 0 , 1 , 0 , 0 , 1 ]], 8 => [[0 , 0 , 1 , 0 , 1 , 0 ]], 1 => [[1 , 0 , 0 , 0 , 1 , 0 ]], 0 => [[0 , 1 , 0 , 0 , 1 , 0 ]], 6 => [[0 , 1 , 0 , 1 , 0 , 1 ]], 11 => [[1 , 0 , 1 , 1 , 0 , 0 ]], 9 => [[1 , 0 , 1 , 0 , 1 , 0 ]], 14 => [[0 , 0 , 1 , 1 , 0 , 1 ]], 3 => [[1 , 0 , 0 , 1 , 0 , 0 ]], 7 => [], 4 => [[0 , 1 , 0 , 0 , 0 , 1 ]], 13 => [], 15 => [], 2 => [[0 , 1 , 0 , 1 , 0 , 0 ]], 10 => [[0 , 0 , 1 , 1 , 0 , 0 ]]])
1820end
1921
22+ mis_overhead (:: Cross{true} ) = - 1.0
23+
2024
2125function mapped_entry_to_compact (:: Turn )
2226 return Dict ([0 => 0 , 2 => 0 , 3 => 3 , 1 => 0 ])
2327end
2428
2529function source_entry_to_configs (:: Turn )
26- return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 1 , 0 , 1 , 0 ]], 2 => [[0 , 0 , 1 , 0 , 1 ], [0 , 1 , 0 , 0 , 1 ]], 3 => [[1 , 0 , 1 , 0 , 1 ]], 1 => [[1 , 0 , 1 , 0 , 0 ], [1 , 0 , 0 , 1 , 0 ]]])
30+ return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 1 , 0 , 1 , 0 ]], 2 => [[0 , 0 , 1 , 0 , 1 ], [0 , 1 , 0 , 0 , 1 ]], 3 => [[1 , 0 , 1 , 0 , 1 ]], 1 => [[1 , 0 , 0 , 1 , 0 ], [1 , 0 , 1 , 0 , 0 ]]])
2731end
2832
33+ mis_overhead (:: Turn ) = - 1.0
34+
2935
3036function mapped_entry_to_compact (:: WTurn )
3137 return Dict ([0 => 0 , 2 => 0 , 3 => 3 , 1 => 0 ])
3238end
3339
3440function source_entry_to_configs (:: WTurn )
35- return Dict (Pair{Int64, Vector{BitVector}}[0 => [[1 , 0 , 1 , 0 , 0 ]], 2 => [[0 , 0 , 0 , 1 , 1 ], [1 , 0 , 0 , 0 , 1 ]], 3 => [[0 , 1 , 0 , 1 , 1 ]], 1 => [[0 , 1 , 0 , 1 , 0 ], [0 , 1 , 1 , 0 , 0 ]]])
41+ return Dict (Pair{Int64, Vector{BitVector}}[0 => [[1 , 0 , 1 , 0 , 0 ]], 2 => [[1 , 0 , 0 , 0 , 1 ], [0 , 0 , 0 , 1 , 1 ]], 3 => [[0 , 1 , 0 , 1 , 1 ]], 1 => [[0 , 1 , 1 , 0 , 0 ], [0 , 1 , 0 , 1 , 0 ]]])
3642end
3743
44+ mis_overhead (:: WTurn ) = - 1.0
45+
3846
3947function mapped_entry_to_compact (:: Branch )
4048 return Dict ([0 => 0 , 4 => 0 , 5 => 5 , 6 => 6 , 2 => 0 , 7 => 7 , 3 => 3 , 1 => 0 ])
4149end
4250
4351function source_entry_to_configs (:: Branch )
44- return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 1 , 0 , 1 , 0 , 0 , 1 , 0 ]], 4 => [[0 , 0 , 1 , 0 , 0 , 1 , 0 , 1 ], [0 , 1 , 0 , 0 , 0 , 1 , 0 , 1 ], [0 , 1 , 0 , 1 , 0 , 0 , 0 , 1 ]], 5 => [[1 , 0 , 1 , 0 , 0 , 1 , 0 , 1 ]], 6 => [[0 , 0 , 1 , 0 , 1 , 1 , 0 , 1 ], [0 , 1 , 0 , 0 , 1 , 1 , 0 , 1 ]], 2 => [[0 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ], [0 , 1 , 0 , 0 , 1 , 0 , 1 , 0 ], [0 , 0 , 1 , 0 , 1 , 1 , 0 , 0 ], [0 , 1 , 0 , 0 , 1 , 1 , 0 , 0 ]], 7 => [[1 , 0 , 1 , 0 , 1 , 1 , 0 , 1 ]], 3 => [[1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ], [1 , 0 , 1 , 0 , 1 , 1 , 0 , 0 ]], 1 => [[1 , 0 , 1 , 0 , 0 , 0 , 1 , 0 ], [1 , 0 , 1 , 0 , 0 , 1 , 0 , 0 ], [1 , 0 , 0 , 1 , 0 , 0 , 1 , 0 ]]])
52+ return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 1 , 0 , 1 , 0 , 0 , 1 , 0 ]], 4 => [[0 , 1 , 0 , 0 , 0 , 1 , 0 , 1 ], [0 , 0 , 1 , 0 , 0 , 1 , 0 , 1 ], [0 , 1 , 0 , 1 , 0 , 0 , 0 , 1 ]], 5 => [[1 , 0 , 1 , 0 , 0 , 1 , 0 , 1 ]], 6 => [[0 , 1 , 0 , 0 , 1 , 1 , 0 , 1 ], [0 , 0 , 1 , 0 , 1 , 1 , 0 , 1 ]], 2 => [[0 , 1 , 0 , 0 , 1 , 0 , 1 , 0 ], [0 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ], [0 , 1 , 0 , 0 , 1 , 1 , 0 , 0 ], [0 , 0 , 1 , 0 , 1 , 1 , 0 , 0 ]], 7 => [[1 , 0 , 1 , 0 , 1 , 1 , 0 , 1 ]], 3 => [[1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ], [1 , 0 , 1 , 0 , 1 , 1 , 0 , 0 ]], 1 => [[1 , 0 , 1 , 0 , 0 , 0 , 1 , 0 ], [1 , 0 , 1 , 0 , 0 , 1 , 0 , 0 ], [1 , 0 , 0 , 1 , 0 , 0 , 1 , 0 ]]])
4553end
4654
55+ mis_overhead (:: Branch ) = - 1.0
56+
4757
4858function mapped_entry_to_compact (:: BranchFix )
4959 return Dict ([0 => 0 , 2 => 2 , 3 => 1 , 1 => 1 ])
5060end
5161
5262function source_entry_to_configs (:: BranchFix )
53- return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 0 , 1 , 0 , 1 , 0 ], [0 , 1 , 0 , 0 , 1 , 0 ], [0 , 1 , 0 , 1 , 0 , 0 ]], 2 => [[0 , 1 , 0 , 1 , 0 , 1 ]], 3 => [[1 , 0 , 1 , 0 , 0 , 1 ], [1 , 0 , 0 , 1 , 0 , 1 ]], 1 => [[1 , 0 , 1 , 0 , 1 , 0 ]]])
63+ return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 1 , 0 , 0 , 1 , 0 ], [0 , 0 , 1 , 0 , 1 , 0 ], [0 , 1 , 0 , 1 , 0 , 0 ]], 2 => [[0 , 1 , 0 , 1 , 0 , 1 ]], 3 => [[1 , 0 , 1 , 0 , 0 , 1 ], [1 , 0 , 0 , 1 , 0 , 1 ]], 1 => [[1 , 0 , 1 , 0 , 1 , 0 ]]])
5464end
5565
66+ mis_overhead (:: BranchFix ) = - 1.0
67+
5668
5769function mapped_entry_to_compact (:: TrivialTurn )
5870 return Dict ([0 => 0 , 2 => 2 , 3 => 3 , 1 => 1 ])
@@ -62,6 +74,8 @@ function source_entry_to_configs(::TrivialTurn)
6274 return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 0 ]], 2 => [[0 , 1 ]], 3 => [], 1 => [[1 , 0 ]]])
6375end
6476
77+ mis_overhead (:: TrivialTurn ) = - 0.0
78+
6579
6680function mapped_entry_to_compact (:: TCon )
6781 return Dict ([0 => 0 , 4 => 0 , 5 => 5 , 6 => 6 , 2 => 2 , 7 => 7 , 3 => 3 , 1 => 0 ])
@@ -71,6 +85,8 @@ function source_entry_to_configs(::TCon)
7185 return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 0 , 1 , 0 ]], 4 => [[0 , 0 , 0 , 1 ]], 5 => [[1 , 0 , 0 , 1 ]], 6 => [[0 , 1 , 0 , 1 ]], 2 => [[0 , 1 , 1 , 0 ]], 7 => [], 3 => [], 1 => [[1 , 0 , 0 , 0 ]]])
7286end
7387
88+ mis_overhead (:: TCon ) = - 0.0
89+
7490
7591function mapped_entry_to_compact (:: BranchFixB )
7692 return Dict ([0 => 0 , 2 => 2 , 3 => 3 , 1 => 1 ])
7995function source_entry_to_configs (:: BranchFixB )
8096 return Dict (Pair{Int64, Vector{BitVector}}[0 => [[0 , 1 , 0 , 0 ], [0 , 0 , 1 , 0 ]], 2 => [[0 , 0 , 1 , 1 ]], 3 => [[1 , 0 , 0 , 1 ]], 1 => [[1 , 1 , 0 , 0 ]]])
8197end
98+
99+ mis_overhead (:: BranchFixB ) = - 1.0
100+
101+
102+ function mapped_entry_to_compact (:: UnitDiskMapping.DanglingLeg )
103+ return Dict ([0 => 0 , 1 => 1 ])
104+ end
105+
106+ function source_entry_to_configs (:: UnitDiskMapping.DanglingLeg )
107+ return Dict (Pair{Int64, Vector{BitVector}}[0 => [[1 , 0 , 0 ], [0 , 1 , 0 ]], 1 => [[1 , 0 , 1 ]]])
108+ end
109+
110+ mis_overhead (:: UnitDiskMapping.DanglingLeg ) = - 1.0
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