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| 1 | +#include <rtthread.h> |
| 2 | +#include <rtdevice.h> |
| 3 | + |
| 4 | +#include "spi_flash.h" |
| 5 | +#include "spi_flash_w25qxx_mtd.h" |
| 6 | + |
| 7 | +#include <stdint.h> |
| 8 | +#include <stdio.h> |
| 9 | +#include <string.h> |
| 10 | +#include <stdlib.h> |
| 11 | + |
| 12 | +#define FLASH_DEBUG |
| 13 | + |
| 14 | +#ifdef FLASH_DEBUG |
| 15 | +#define FLASH_TRACE printf |
| 16 | +#else |
| 17 | +#define FLASH_TRACE(...) |
| 18 | +#endif /* #ifdef FLASH_DEBUG */ |
| 19 | + |
| 20 | +/* JEDEC Manufacturer¡¯s ID */ |
| 21 | +#define MF_ID (0xEF) |
| 22 | +/* JEDEC Device ID: Memory type and Capacity */ |
| 23 | +#define MTC_W25Q80_BV (0x4014) /* W25Q80BV */ |
| 24 | +#define MTC_W25Q16_BV_CL_CV (0x4015) /* W25Q16BV W25Q16CL W25Q16CV */ |
| 25 | +#define MTC_W25Q16_DW (0x6015) /* W25Q16DW */ |
| 26 | +#define MTC_W25Q32_BV (0x4016) /* W25Q32BV */ |
| 27 | +#define MTC_W25Q32_DW (0x6016) /* W25Q32DW */ |
| 28 | +#define MTC_W25Q64_BV_CV (0x4017) /* W25Q64BV W25Q64CV */ |
| 29 | +#define MTC_W25Q64_DW (0x4017) /* W25Q64DW */ |
| 30 | +#define MTC_W25Q128_BV (0x4018) /* W25Q128BV */ |
| 31 | +#define MTC_W25Q256_FV (TBD) /* W25Q256FV */ |
| 32 | + |
| 33 | +#define MTC_W25X80 (0x3014) |
| 34 | + |
| 35 | +/* command list */ |
| 36 | +#define CMD_WRSR (0x01) /* Write Status Register */ |
| 37 | +#define CMD_PP (0x02) /* Page Program */ |
| 38 | +#define CMD_READ (0x03) /* Read Data */ |
| 39 | +#define CMD_WRDI (0x04) /* Write Disable */ |
| 40 | +#define CMD_RDSR1 (0x05) /* Read Status Register-1 */ |
| 41 | +#define CMD_WREN (0x06) /* Write Enable */ |
| 42 | +#define CMD_FAST_READ (0x0B) /* Fast Read */ |
| 43 | +#define CMD_ERASE_4K (0x20) /* Sector Erase:4K */ |
| 44 | +#define CMD_RDSR2 (0x35) /* Read Status Register-2 */ |
| 45 | +#define CMD_ERASE_32K (0x52) /* 32KB Block Erase */ |
| 46 | +#define CMD_JEDEC_ID (0x9F) /* Read JEDEC ID */ |
| 47 | +#define CMD_ERASE_full (0xC7) /* Chip Erase */ |
| 48 | +#define CMD_ERASE_64K (0xD8) /* 64KB Block Erase */ |
| 49 | +#define CMD_MANU_ID (0x90) |
| 50 | + |
| 51 | +#define DUMMY (0xFF) |
| 52 | + |
| 53 | +#define FLASH_ERASE_CMD CMD_ERASE_4K |
| 54 | +#define FLASH_BLOCK_SIZE 4096 |
| 55 | +#define FLASH_PAGE_SIZE 256 |
| 56 | + |
| 57 | +static void w25qxx_lock(struct rt_mtd_nor_device *device) |
| 58 | +{ |
| 59 | + struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device; |
| 60 | + rt_mutex_take(&mtd->lock, RT_WAITING_FOREVER); |
| 61 | +} |
| 62 | + |
| 63 | +static void w25qxx_unlock(struct rt_mtd_nor_device *device) |
| 64 | +{ |
| 65 | + struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device; |
| 66 | + rt_mutex_release(&mtd->lock); |
| 67 | +} |
| 68 | + |
| 69 | +static rt_uint8_t w25qxx_read_status(struct rt_mtd_nor_device *device) |
| 70 | +{ |
| 71 | + struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device; |
| 72 | + return rt_spi_sendrecv8(mtd->rt_spi_device, CMD_RDSR1); |
| 73 | +} |
| 74 | + |
| 75 | +static void w25qxx_wait_busy(struct rt_mtd_nor_device *device) |
| 76 | +{ |
| 77 | + while( w25qxx_read_status(device) & (0x01)); |
| 78 | +} |
| 79 | + |
| 80 | +static rt_err_t w25qxx_read_id(struct rt_mtd_nor_device *device) |
| 81 | +{ |
| 82 | + rt_uint8_t cmd; |
| 83 | + rt_uint8_t id_recv[3]; |
| 84 | + |
| 85 | + struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device; |
| 86 | + |
| 87 | + w25qxx_lock(device); |
| 88 | + |
| 89 | + cmd = 0xFF; /* reset SPI FLASH, cancel all cmd in processing. */ |
| 90 | + rt_spi_send(mtd->rt_spi_device, &cmd, 1); |
| 91 | + |
| 92 | + cmd = CMD_WRDI; |
| 93 | + rt_spi_send(mtd->rt_spi_device, &cmd, 1); |
| 94 | + |
| 95 | + /* read flash id */ |
| 96 | + cmd = CMD_JEDEC_ID; |
| 97 | + rt_spi_send_then_recv(mtd->rt_spi_device, &cmd, 1, id_recv, 3); |
| 98 | + |
| 99 | + w25qxx_unlock(device); |
| 100 | + |
| 101 | + return (rt_uint32_t)(id_recv[0] << 16) | (id_recv[1] << 8) | id_recv[2]; |
| 102 | +} |
| 103 | + |
| 104 | +static rt_size_t w25qxx_read(struct rt_mtd_nor_device *device, rt_off_t offset, rt_uint8_t *buffer, rt_size_t length) |
| 105 | +{ |
| 106 | + struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device; |
| 107 | + rt_uint8_t send_buffer[4]; |
| 108 | + |
| 109 | + if((offset + length) > device->block_end * FLASH_BLOCK_SIZE) |
| 110 | + return 0; |
| 111 | + |
| 112 | + |
| 113 | + w25qxx_lock(device); |
| 114 | + |
| 115 | + send_buffer[0] = CMD_WRDI; |
| 116 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 1); |
| 117 | + |
| 118 | + send_buffer[0] = CMD_READ; |
| 119 | + send_buffer[1] = (rt_uint8_t)(offset>>16); |
| 120 | + send_buffer[2] = (rt_uint8_t)(offset>>8); |
| 121 | + send_buffer[3] = (rt_uint8_t)(offset); |
| 122 | + rt_spi_send_then_recv(mtd->rt_spi_device, |
| 123 | + send_buffer, 4, |
| 124 | + buffer, length); |
| 125 | + |
| 126 | + w25qxx_unlock(device); |
| 127 | + return length; |
| 128 | +} |
| 129 | + |
| 130 | +static rt_size_t w25qxx_write(struct rt_mtd_nor_device *device, rt_off_t offset, const rt_uint8_t *buffer, rt_size_t length) |
| 131 | +{ |
| 132 | + struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device; |
| 133 | + rt_uint8_t send_buffer[4]; |
| 134 | + rt_uint8_t *write_ptr ; |
| 135 | + rt_size_t write_size,write_total; |
| 136 | + |
| 137 | + if((offset + length) > device->block_end * FLASH_BLOCK_SIZE) |
| 138 | + return 0; |
| 139 | + |
| 140 | + w25qxx_lock(device); |
| 141 | + |
| 142 | + send_buffer[0] = CMD_WREN; |
| 143 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 1); |
| 144 | + w25qxx_wait_busy(device); // wait erase done. |
| 145 | + |
| 146 | + write_size = 0; |
| 147 | + write_total = 0; |
| 148 | + write_ptr = (rt_uint8_t *)buffer; |
| 149 | + while(write_total < length) |
| 150 | + { |
| 151 | + send_buffer[0] = CMD_WREN; |
| 152 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 1); |
| 153 | + |
| 154 | + //write first page... |
| 155 | + send_buffer[0] = CMD_PP; |
| 156 | + send_buffer[1] = (rt_uint8_t)(offset >> 16); |
| 157 | + send_buffer[2] = (rt_uint8_t)(offset >> 8); |
| 158 | + send_buffer[3] = (rt_uint8_t)(offset); |
| 159 | + |
| 160 | + //address % FLASH_PAGE_SIZE + length |
| 161 | + if(((offset & (FLASH_PAGE_SIZE - 1)) + (length - write_total)) > FLASH_PAGE_SIZE) |
| 162 | + { |
| 163 | + write_size = FLASH_PAGE_SIZE - (offset & (FLASH_PAGE_SIZE - 1)); |
| 164 | + } |
| 165 | + else |
| 166 | + { |
| 167 | + write_size = (length - write_total); |
| 168 | + } |
| 169 | + |
| 170 | + rt_spi_send_then_send(mtd->rt_spi_device, |
| 171 | + send_buffer, 4, |
| 172 | + write_ptr + write_total, write_size); |
| 173 | + w25qxx_wait_busy(device); |
| 174 | + |
| 175 | + |
| 176 | + offset += write_size; |
| 177 | + write_total += write_size; |
| 178 | + } |
| 179 | + |
| 180 | + send_buffer[0] = CMD_WRDI; |
| 181 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 1); |
| 182 | + |
| 183 | + w25qxx_unlock(device); |
| 184 | + |
| 185 | + return length; |
| 186 | +} |
| 187 | + |
| 188 | +static rt_err_t w25qxx_erase_block(struct rt_mtd_nor_device *device, rt_off_t offset, rt_uint32_t length) |
| 189 | +{ |
| 190 | + struct spi_flash_mtd *mtd = (struct spi_flash_mtd *)device; |
| 191 | + rt_uint8_t send_buffer[4]; |
| 192 | + rt_uint32_t erase_size = 0; |
| 193 | + |
| 194 | + //offset must be ALIGN_DOWN to BLOCKSIZE |
| 195 | + if(offset != RT_ALIGN_DOWN(offset,FLASH_BLOCK_SIZE)) |
| 196 | + return 0; |
| 197 | + |
| 198 | + if((offset + length) > device->block_end * FLASH_BLOCK_SIZE) |
| 199 | + return 0; |
| 200 | + |
| 201 | + /* check length must align to block size */ |
| 202 | + if(length % device->block_size != 0) |
| 203 | + { |
| 204 | + rt_kprintf("param length = %d ,error\n",length); |
| 205 | + return 0; |
| 206 | + } |
| 207 | + |
| 208 | + w25qxx_lock(device); |
| 209 | + |
| 210 | + send_buffer[0] = CMD_WREN; |
| 211 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 1); |
| 212 | + w25qxx_wait_busy(device); // wait erase done. |
| 213 | + while (erase_size < length) |
| 214 | + { |
| 215 | + send_buffer[0] = CMD_ERASE_4K; |
| 216 | + send_buffer[1] = (rt_uint8_t) (offset >> 16); |
| 217 | + send_buffer[2] = (rt_uint8_t) (offset >> 8); |
| 218 | + send_buffer[3] = (rt_uint8_t) (offset); |
| 219 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 4); |
| 220 | + w25qxx_wait_busy(device); // wait erase done. |
| 221 | + |
| 222 | + erase_size += 4096; |
| 223 | + offset += 4096; |
| 224 | + } |
| 225 | + send_buffer[0] = CMD_WRDI; |
| 226 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 1); |
| 227 | + |
| 228 | + w25qxx_unlock(device); |
| 229 | + return RT_EOK; |
| 230 | +} |
| 231 | + |
| 232 | +const static struct rt_mtd_nor_driver_ops w25qxx_mtd_ops = |
| 233 | +{ |
| 234 | + w25qxx_read_id, |
| 235 | + w25qxx_read, |
| 236 | + w25qxx_write, |
| 237 | + w25qxx_erase_block, |
| 238 | +}; |
| 239 | + |
| 240 | +rt_err_t w25qxx_mtd_init(const char *mtd_name,const char * spi_device_name) |
| 241 | +{ |
| 242 | + rt_err_t result = RT_EOK; |
| 243 | + rt_uint32_t id; |
| 244 | + rt_uint8_t send_buffer[3]; |
| 245 | + |
| 246 | + struct rt_spi_device* rt_spi_device; |
| 247 | + struct spi_flash_mtd* mtd = (struct spi_flash_mtd *)rt_malloc(sizeof(struct spi_flash_mtd)); |
| 248 | + |
| 249 | + RT_ASSERT(mtd != RT_NULL); |
| 250 | + |
| 251 | + /* initialize mutex */ |
| 252 | + if (rt_mutex_init(&mtd->lock, mtd_name, RT_IPC_FLAG_FIFO) != RT_EOK) |
| 253 | + { |
| 254 | + FLASH_TRACE("init mtd lock mutex failed\n"); |
| 255 | + result = -RT_ENOSYS; |
| 256 | + |
| 257 | + goto _error_exit; |
| 258 | + } |
| 259 | + |
| 260 | + rt_spi_device = (struct rt_spi_device *)rt_device_find(spi_device_name); |
| 261 | + if(rt_spi_device == RT_NULL) |
| 262 | + { |
| 263 | + FLASH_TRACE("spi device %s not found!\r\n", spi_device_name); |
| 264 | + result = -RT_ENOSYS; |
| 265 | + |
| 266 | + goto _error_exit; |
| 267 | + } |
| 268 | + mtd->rt_spi_device = rt_spi_device; |
| 269 | + /* config spi */ |
| 270 | + { |
| 271 | + struct rt_spi_configuration cfg; |
| 272 | + cfg.data_width = 8; |
| 273 | + cfg.mode = RT_SPI_MODE_0 | RT_SPI_MSB; /* SPI Compatible: Mode 0 and Mode 3 */ |
| 274 | + cfg.max_hz = 20 * 1000 * 1000; /* 20 */ |
| 275 | + rt_spi_configure(rt_spi_device, &cfg); |
| 276 | + } |
| 277 | + |
| 278 | + /* Init Flash device */ |
| 279 | + { |
| 280 | + w25qxx_lock(&mtd->mtd_device); |
| 281 | + |
| 282 | + send_buffer[0] = CMD_WREN; |
| 283 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 1); |
| 284 | + w25qxx_wait_busy(&mtd->mtd_device); |
| 285 | + |
| 286 | + send_buffer[0] = CMD_WRSR; |
| 287 | + send_buffer[1] = 0; |
| 288 | + send_buffer[2] = 0; |
| 289 | + rt_spi_send(mtd->rt_spi_device, send_buffer, 3); |
| 290 | + w25qxx_wait_busy(&mtd->mtd_device); |
| 291 | + |
| 292 | + w25qxx_unlock(&mtd->mtd_device); |
| 293 | + } |
| 294 | + |
| 295 | + id = w25qxx_read_id(&mtd->mtd_device); |
| 296 | + |
| 297 | + mtd->mtd_device.block_size = 4096; |
| 298 | + mtd->mtd_device.block_start = 0; |
| 299 | + switch(id & 0xFFFF) |
| 300 | + { |
| 301 | + case MTC_W25Q80_BV: /* W25Q80BV */ |
| 302 | + mtd->mtd_device.block_end = 256; |
| 303 | + break; |
| 304 | + case MTC_W25Q16_BV_CL_CV: /* W25Q16BV W25Q16CL W25Q16CV */ |
| 305 | + case MTC_W25Q16_DW: /* W25Q16DW */ |
| 306 | + mtd->mtd_device.block_end = 512; |
| 307 | + break; |
| 308 | + case MTC_W25Q32_BV: /* W25Q32BV */ |
| 309 | + case MTC_W25Q32_DW: /* W25Q32DW */ |
| 310 | + mtd->mtd_device.block_end = 1024; |
| 311 | + break; |
| 312 | + case MTC_W25Q64_BV_CV: /* W25Q64BV W25Q64CV */ |
| 313 | + mtd->mtd_device.block_end = 2048; |
| 314 | + break; |
| 315 | + case MTC_W25Q128_BV: /* W25Q128BV */ |
| 316 | + mtd->mtd_device.block_end = 4086; |
| 317 | + break; |
| 318 | + } |
| 319 | + mtd->mtd_device.ops = &w25qxx_mtd_ops; |
| 320 | + rt_mtd_nor_register_device(mtd_name,&mtd->mtd_device); |
| 321 | + |
| 322 | + return RT_EOK; |
| 323 | + |
| 324 | +_error_exit: |
| 325 | + if(mtd != RT_NULL) |
| 326 | + rt_free(mtd); |
| 327 | + return result; |
| 328 | +} |
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