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GuozhanxinGuozhanxin
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Merge pull request #4907 from YJ98/stm32f302
Add stm32f3 series bsp.
2 parents ce1734f + 53a4074 commit 5e277b0

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‎.github/workflows/action.yml‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -79,6 +79,7 @@ jobs:
7979
- {RTT_BSP: "stm32/stm32f103-yf-ufun", RTT_TOOL_CHAIN: "sourcery-arm"}
8080
- {RTT_BSP: "stm32/stm32f107-uc-eval", RTT_TOOL_CHAIN: "sourcery-arm"}
8181
- {RTT_BSP: "stm32/stm32f207-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
82+
- {RTT_BSP: "stm32/stm32f302-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
8283
- {RTT_BSP: "stm32/stm32f401-st-nucleo", RTT_TOOL_CHAIN: "sourcery-arm"}
8384
- {RTT_BSP: "stm32/stm32f405-smdz-breadfruit", RTT_TOOL_CHAIN: "sourcery-arm"}
8485
- {RTT_BSP: "stm32/stm32f407-atk-explorer", RTT_TOOL_CHAIN: "sourcery-arm"}

‎bsp/stm32/libraries/HAL_Drivers/config/f3/dma_config.h‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/*
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2019-01-02 zylx first version
9+
* 2019-01-08 SummerGift clean up the code
10+
*/
11+
12+
#ifndef __DMA_CONFIG_H__
13+
#define __DMA_CONFIG_H__
14+
15+
#include <rtthread.h>
16+
17+
#ifdef __cplusplus
18+
extern "C" {
19+
#endif
20+
21+
#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE)
22+
#define UART2_DMA_RX_IRQHandler DMA1_Channel5_IRQHandler
23+
#define UART2_RX_DMA_RCC RCC_AHBENR_DMA1EN
24+
#define UART2_RX_DMA_INSTANCE DMA1_Channel5
25+
#define UART2_RX_DMA_CHANNEL DMA1_Channel5_BASE
26+
#define UART2_RX_DMA_IRQ DMA1_Channel5_IRQn
27+
#endif
28+
29+
#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE)
30+
#define UART2_DMA_TX_IRQHandler DMA1_Channel6_IRQHandler
31+
#define UART2_TX_DMA_RCC RCC_AHBENR_DMA1EN
32+
#define UART2_TX_DMA_INSTANCE DMA1_Channel6
33+
#define UART2_TX_DMA_CHANNEL DMA1_Channel6_BASE
34+
#define UART2_TX_DMA_IRQ DMA1_Channel6_IRQn
35+
#endif
36+
37+
#ifdef __cplusplus
38+
}
39+
#endif
40+
41+
#endif /* __DMA_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f3/pwm_config.h‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,35 @@
1+
/*
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-12-13 zylx first version
9+
*/
10+
11+
#ifndef __PWM_CONFIG_H__
12+
#define __PWM_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#ifdef __cplusplus
17+
extern "C" {
18+
#endif
19+
20+
#ifdef BSP_USING_PWM1
21+
#ifndef PWM1_CONFIG
22+
#define PWM1_CONFIG \
23+
{ \
24+
.tim_handle.Instance = TIM1, \
25+
.name = "pwm1", \
26+
.channel = 0 \
27+
}
28+
#endif /* PWM1_CONFIG */
29+
#endif /* BSP_USING_PWM1 */
30+
31+
#ifdef __cplusplus
32+
}
33+
#endif
34+
35+
#endif /* __PWM_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f3/tim_config.h‎

Lines changed: 45 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,45 @@
1+
/*
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-12-11 zylx first version
9+
*/
10+
11+
#ifndef __TIM_CONFIG_H__
12+
#define __TIM_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#ifdef __cplusplus
17+
extern "C" {
18+
#endif
19+
20+
#ifndef TIM_DEV_INFO_CONFIG
21+
#define TIM_DEV_INFO_CONFIG \
22+
{ \
23+
.maxfreq = 1000000, \
24+
.minfreq = 3000, \
25+
.maxcnt = 0xFFFF, \
26+
.cntmode = HWTIMER_CNTMODE_UP, \
27+
}
28+
#endif /* TIM_DEV_INFO_CONFIG */
29+
30+
#ifdef BSP_USING_TIM1
31+
#ifndef TIM1_CONFIG
32+
#define TIM1_CONFIG \
33+
{ \
34+
.tim_handle.Instance = TIM1, \
35+
.tim_irqn = TIM1_IRQn, \
36+
.name = "timer1", \
37+
}
38+
#endif /* TIM1_CONFIG */
39+
#endif /* BSP_USING_TIM1 */
40+
41+
#ifdef __cplusplus
42+
}
43+
#endif
44+
45+
#endif /* __TIM_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f3/uart_config.h‎

Lines changed: 130 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,130 @@
1+
/*
2+
* Copyright (c) 2006-2021, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-10-30 SummerGift first version
9+
* 2019-01-03 zylx modify dma support
10+
*/
11+
12+
#ifndef __UART_CONFIG_H__
13+
#define __UART_CONFIG_H__
14+
15+
#include <rtthread.h>
16+
17+
#ifdef __cplusplus
18+
extern "C" {
19+
#endif
20+
21+
#if defined(BSP_USING_UART1)
22+
#ifndef UART1_CONFIG
23+
#define UART1_CONFIG \
24+
{ \
25+
.name = "uart1", \
26+
.Instance = USART1, \
27+
.irq_type = USART1_IRQn, \
28+
}
29+
#endif /* UART1_CONFIG */
30+
31+
#if defined(BSP_UART1_RX_USING_DMA)
32+
#ifndef UART1_DMA_RX_CONFIG
33+
#define UART1_DMA_RX_CONFIG \
34+
{ \
35+
.Instance = UART1_RX_DMA_INSTANCE, \
36+
.channel = UART1_RX_DMA_CHANNEL, \
37+
.dma_rcc = UART1_RX_DMA_RCC, \
38+
.dma_irq = UART1_RX_DMA_IRQ, \
39+
}
40+
#endif /* UART1_DMA_RX_CONFIG */
41+
#endif /* BSP_UART1_RX_USING_DMA */
42+
43+
#if defined(BSP_UART1_TX_USING_DMA)
44+
#ifndef UART1_DMA_TX_CONFIG
45+
#define UART1_DMA_TX_CONFIG \
46+
{ \
47+
.Instance = UART1_TX_DMA_INSTANCE, \
48+
.channel = UART1_TX_DMA_CHANNEL, \
49+
.dma_rcc = UART1_TX_DMA_RCC, \
50+
.dma_irq = UART1_TX_DMA_IRQ, \
51+
}
52+
#endif /* UART1_DMA_TX_CONFIG */
53+
#endif /* BSP_UART1_TX_USING_DMA */
54+
#endif /* BSP_USING_UART1 */
55+
56+
#if defined(BSP_USING_UART2)
57+
#ifndef UART2_CONFIG
58+
#define UART2_CONFIG \
59+
{ \
60+
.name = "uart2", \
61+
.Instance = USART2, \
62+
.irq_type = USART2_IRQn, \
63+
}
64+
#endif /* UART2_CONFIG */
65+
66+
#if defined(BSP_UART2_RX_USING_DMA)
67+
#ifndef UART2_DMA_RX_CONFIG
68+
#define UART2_DMA_RX_CONFIG \
69+
{ \
70+
.Instance = UART2_RX_DMA_INSTANCE, \
71+
.channel = UART2_RX_DMA_CHANNEL, \
72+
.dma_rcc = UART2_RX_DMA_RCC, \
73+
.dma_irq = UART2_RX_DMA_IRQ, \
74+
}
75+
#endif /* UART2_DMA_RX_CONFIG */
76+
#endif /* BSP_UART2_RX_USING_DMA */
77+
78+
#if defined(BSP_UART2_TX_USING_DMA)
79+
#ifndef UART2_DMA_TX_CONFIG
80+
#define UART2_DMA_TX_CONFIG \
81+
{ \
82+
.Instance = UART2_TX_DMA_INSTANCE, \
83+
.channel = UART2_TX_DMA_CHANNEL, \
84+
.dma_rcc = UART2_TX_DMA_RCC, \
85+
.dma_irq = UART2_TX_DMA_IRQ, \
86+
}
87+
#endif /* UART2_DMA_TX_CONFIG */
88+
#endif /* BSP_UART2_TX_USING_DMA */
89+
#endif /* BSP_USING_UART2 */
90+
91+
#if defined(BSP_USING_UART3)
92+
#ifndef UART3_CONFIG
93+
#define UART3_CONFIG \
94+
{ \
95+
.name = "uart3", \
96+
.Instance = USART3, \
97+
.irq_type = USART3_IRQn, \
98+
}
99+
#endif /* UART3_CONFIG */
100+
101+
#if defined(BSP_UART3_RX_USING_DMA)
102+
#ifndef UART3_DMA_RX_CONFIG
103+
#define UART3_DMA_RX_CONFIG \
104+
{ \
105+
.Instance = UART3_RX_DMA_INSTANCE, \
106+
.channel = UART3_RX_DMA_CHANNEL, \
107+
.dma_rcc = UART3_RX_DMA_RCC, \
108+
.dma_irq = UART3_RX_DMA_IRQ, \
109+
}
110+
#endif /* UART3_DMA_RX_CONFIG */
111+
#endif /* BSP_UART3_RX_USING_DMA */
112+
113+
#if defined(BSP_UART3_TX_USING_DMA)
114+
#ifndef UART3_DMA_TX_CONFIG
115+
#define UART3_DMA_TX_CONFIG \
116+
{ \
117+
.Instance = UART3_TX_DMA_INSTANCE, \
118+
.channel = UART3_TX_DMA_CHANNEL, \
119+
.dma_rcc = UART3_TX_DMA_RCC, \
120+
.dma_irq = UART3_TX_DMA_IRQ, \
121+
}
122+
#endif /* UART3_DMA_TX_CONFIG */
123+
#endif /* BSP_UART3_TX_USING_DMA */
124+
#endif /* BSP_USING_UART3 */
125+
126+
#ifdef __cplusplus
127+
}
128+
#endif
129+
130+
#endif

‎bsp/stm32/libraries/HAL_Drivers/drv_can.c‎

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -325,13 +325,13 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
325325
* STD ID | STID[10:3] | STDID[2:0] |<- 21bit ->|
326326
* EXT ID | EXTID[28:21] | EXTID[20:13] | EXTID[12:5] | EXTID[4:0] IDE RTR 0|
327327
* @note the 32bit STD ID must << 21 to fill CAN_FxR1[31:21] and EXT ID must << 3,
328-
* -> but the id bit of struct rt_can_filter_item is 29,
328+
* -> but the id bit of struct rt_can_filter_item is 29,
329329
* -> so STD id << 18 and EXT id Don't need << 3, when get the high 16bit.
330330
* -> FilterIdHigh : (((STDid << 18) or (EXT id)) >> 13) & 0xFFFF,
331-
* -> FilterIdLow: ((STDid << 18) or (EXT id << 3)) & 0xFFFF.
332-
* @note the mask bit of struct rt_can_filter_item is 32,
333-
* -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF
334-
* -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF
331+
* -> FilterIdLow: ((STDid << 18) or (EXT id << 3)) & 0xFFFF.
332+
* @note the mask bit of struct rt_can_filter_item is 32,
333+
* -> FilterMaskIdHigh: (((STD mask << 21) or (EXT mask <<3)) >> 16) & 0xFFFF
334+
* -> FilterMaskIdLow: ((STD mask << 21) or (EXT mask <<3)) & 0xFFFF
335335
*/
336336
if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDMASK)
337337
{
@@ -341,23 +341,23 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
341341
else if (filter_cfg->items[i].mode == CAN_FILTERMODE_IDLIST)
342342
{
343343
/* same as CAN_FxR1 */
344-
mask_l_tail = (filter_cfg->items[i].ide << 2) |
344+
mask_l_tail = (filter_cfg->items[i].ide << 2) |
345345
(filter_cfg->items[i].rtr << 1);
346346
}
347347
if (filter_cfg->items[i].ide == RT_CAN_STDID)
348348
{
349349
id_h = ((filter_cfg->items[i].id << 18) >> 13) & 0xFFFF;
350-
id_l = ((filter_cfg->items[i].id << 18) |
351-
(filter_cfg->items[i].ide << 2) |
350+
id_l = ((filter_cfg->items[i].id << 18) |
351+
(filter_cfg->items[i].ide << 2) |
352352
(filter_cfg->items[i].rtr << 1)) & 0xFFFF;
353353
mask_h = ((filter_cfg->items[i].mask << 21) >> 16) & 0xFFFF;
354354
mask_l = ((filter_cfg->items[i].mask << 21) | mask_l_tail) & 0xFFFF;
355355
}
356356
else if (filter_cfg->items[i].ide == RT_CAN_EXTID)
357357
{
358358
id_h = (filter_cfg->items[i].id >> 13) & 0xFFFF;
359-
id_l = ((filter_cfg->items[i].id << 3) |
360-
(filter_cfg->items[i].ide << 2) |
359+
id_l = ((filter_cfg->items[i].id << 3) |
360+
(filter_cfg->items[i].ide << 2) |
361361
(filter_cfg->items[i].rtr << 1)) & 0xFFFF;
362362
mask_h = ((filter_cfg->items[i].mask << 3) >> 16) & 0xFFFF;
363363
mask_l = ((filter_cfg->items[i].mask << 3) | mask_l_tail) & 0xFFFF;

‎bsp/stm32/libraries/HAL_Drivers/drv_config.h‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -44,6 +44,11 @@ extern "C" {
4444
#include "f2/tim_config.h"
4545
#include "f2/sdio_config.h"
4646
#include "f2/pwm_config.h"
47+
#elif defined(SOC_SERIES_STM32F3)
48+
#include "f3/uart_config.h"
49+
#include "f3/tim_config.h"
50+
#include "f3/pwm_config.h"
51+
#include "f3/dma_config.h"
4752
#elif defined(SOC_SERIES_STM32F4)
4853
#include "f4/dma_config.h"
4954
#include "f4/uart_config.h"

‎bsp/stm32/libraries/HAL_Drivers/drv_dma.h‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ extern "C" {
2020
#endif
2121

2222
#if defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32L0) \
23-
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)
23+
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4) || defined(SOC_SERIES_STM32WB)|| defined(SOC_SERIES_STM32F3)
2424
#define DMA_INSTANCE_TYPE DMA_Channel_TypeDef
2525
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)\
2626
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
@@ -32,7 +32,7 @@ struct dma_config {
3232
rt_uint32_t dma_rcc;
3333
IRQn_Type dma_irq;
3434

35-
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
35+
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)|| defined(SOC_SERIES_STM32F3)
3636
rt_uint32_t channel;
3737
#endif
3838

‎bsp/stm32/libraries/HAL_Drivers/drv_flash/drv_flash_h7.c‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -78,7 +78,7 @@ int stm32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size)
7878
LOG_E("write outrange flash size! addr is (0x%p)", (void *)(addr + size));
7979
return -RT_EINVAL;
8080
}
81-
81+
8282
if(addr % 32 != 0)
8383
{
8484
LOG_E("write addr must be 32-byte alignment");
@@ -171,7 +171,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
171171
{
172172
size_bank1 = 0;
173173
addr_bank2 = addr;
174-
size_bank2 = size;
174+
size_bank2 = size;
175175
}
176176
else
177177
{
@@ -188,7 +188,7 @@ int stm32_flash_erase(rt_uint32_t addr, size_t size)
188188
EraseInitStruct.TypeErase = FLASH_TYPEERASE_SECTORS;
189189
EraseInitStruct.VoltageRange = FLASH_VOLTAGE_RANGE_3;
190190
SCB_DisableDCache();
191-
191+
192192
if(size_bank1)
193193
{
194194
EraseInitStruct.Sector = (addr_bank1 - FLASH_BANK1_BASE) / FLASH_SECTOR_SIZE;

‎bsp/stm32/libraries/HAL_Drivers/drv_gpio.c‎

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -101,6 +101,23 @@ static const struct pin_irq_map pin_irq_map[] =
101101
{GPIO_PIN_13, EXTI13_IRQn},
102102
{GPIO_PIN_14, EXTI14_IRQn},
103103
{GPIO_PIN_15, EXTI15_IRQn},
104+
#elif defined(SOC_SERIES_STM32F3)
105+
{GPIO_PIN_0, EXTI0_IRQn},
106+
{GPIO_PIN_1, EXTI1_IRQn},
107+
{GPIO_PIN_2, EXTI2_TSC_IRQn},
108+
{GPIO_PIN_3, EXTI3_IRQn},
109+
{GPIO_PIN_4, EXTI4_IRQn},
110+
{GPIO_PIN_5, EXTI9_5_IRQn},
111+
{GPIO_PIN_6, EXTI9_5_IRQn},
112+
{GPIO_PIN_7, EXTI9_5_IRQn},
113+
{GPIO_PIN_8, EXTI9_5_IRQn},
114+
{GPIO_PIN_9, EXTI9_5_IRQn},
115+
{GPIO_PIN_10, EXTI15_10_IRQn},
116+
{GPIO_PIN_11, EXTI15_10_IRQn},
117+
{GPIO_PIN_12, EXTI15_10_IRQn},
118+
{GPIO_PIN_13, EXTI15_10_IRQn},
119+
{GPIO_PIN_14, EXTI15_10_IRQn},
120+
{GPIO_PIN_15, EXTI15_10_IRQn},
104121
#else
105122
{GPIO_PIN_0, EXTI0_IRQn},
106123
{GPIO_PIN_1, EXTI1_IRQn},

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