Merge pull request #4461 from mysterywolf/at32

[at32] auto formatted

Author: BernardXiong

bsp/at32/Libraries/rt_drivers/drv_adc.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -17,7 +17,7 @@
 #include <drv_log.h>
 
 struct at32_adc
-{  
+{
     struct rt_adc_device at32_adc_device;
     ADC_Type *ADC_Handler;
     char *name;
@@ -109,9 +109,9 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
     ADC_InitType ADC_InitStructure;
     RT_ASSERT(device != RT_NULL);
     at32_adc_handler = device->parent.user_data;
-  
+
     at32_msp_adc_init(at32_adc_handler);
-  
+
     /* ADCx configuration ------------------------------------------------------*/
     ADC_StructInit(&ADC_InitStructure);
     ADC_InitStructure.ADC_Mode              = ADC_Mode_Independent;
@@ -121,14 +121,14 @@ static rt_err_t at32_adc_enabled(struct rt_adc_device *device, rt_uint32_t chann
     ADC_InitStructure.ADC_DataAlign         = ADC_DataAlign_Right;
     ADC_InitStructure.ADC_NumOfChannel      = 1;
     ADC_Init(at32_adc_handler, &ADC_InitStructure);
-  
-    /* ADCx regular channels configuration */ 
-    ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5); 
-    
+
+    /* ADCx regular channels configuration */
+    ADC_RegularChannelConfig(at32_adc_handler, at32_adc_get_channel(channel), 1, ADC_SampleTime_28_5);
+
     /* Enable ADCx */
     ADC_Ctrl(at32_adc_handler, ENABLE);
-  
-    /* Enable ADCx reset calibration register */   
+
+    /* Enable ADCx reset calibration register */
     ADC_RstCalibration(at32_adc_handler);
     /* Check the end of ADCx reset calibration register */
     while(ADC_GetResetCalibrationStatus(at32_adc_handler));
@@ -161,7 +161,7 @@ static rt_err_t at32_get_adc_value(struct rt_adc_device *device, rt_uint32_t cha
 
     at32_adc_handler = device->parent.user_data;
 
-    /* Start ADCx Software Conversion */ 
+    /* Start ADCx Software Conversion */
     ADC_SoftwareStartConvCtrl(at32_adc_handler, ENABLE);
 
     /* Wait for the ADC to convert */

bsp/at32/Libraries/rt_drivers/drv_adc.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -19,32 +19,32 @@ extern "C" {
 #endif
 
 #if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2) || defined(BSP_USING_ADC3)
-  
+
 #ifndef ADC1_CONFIG
 #define ADC1_CONFIG                 \
     {                              \
        .ADC_Handler = ADC1,        \
        .name        = "adc1",      \
-    }  
+    }
 #endif /* ADC1_CONFIG */
-    
+
 #ifndef ADC2_CONFIG
 #define ADC2_CONFIG                \
     {                              \
        .ADC_Handler = ADC2,        \
        .name        = "adc2",      \
-    }  
+    }
 #endif /* ADC2_CONFIG */
-    
+
 #ifndef ADC3_CONFIG
 #define ADC3_CONFIG                \
     {                              \
        .ADC_Handler = ADC3,        \
        .name        = "adc3",      \
-    }  
-#endif /* ADC3_CONFIG */    
-    
-#endif  
+    }
+#endif /* ADC3_CONFIG */
+
+#endif
 
 
 #ifdef __cplusplus

bsp/at32/Libraries/rt_drivers/drv_can.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -311,8 +311,8 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg)
             {
                 can_instance->CanConfig.FilterConfig.CAN_FilterNumber = filter_cfg->items[i].hdr & (0x1fU);
                 can_instance->CanConfig.FilterConfig.CAN_FilterIdHigh = (filter_cfg->items[i].id >> 13) & 0xFFFF;
-                can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) | 
-                                                    (filter_cfg->items[i].ide << 2) | 
+                can_instance->CanConfig.FilterConfig.CAN_FilterIdLow = ((filter_cfg->items[i].id << 3) |
+                                                    (filter_cfg->items[i].ide << 2) |
                                                     (filter_cfg->items[i].rtr << 1)) & 0xFFFF;
                 can_instance->CanConfig.FilterConfig.CAN_FilterMskIdHigh = (filter_cfg->items[i].mask >> 16) & 0xFFFF;
                 can_instance->CanConfig.FilterConfig.CAN_FilterMskIdLow = filter_cfg->items[i].mask & 0xFFFF;
@@ -499,7 +499,7 @@ static int _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo)
     else
         pmsg->ide = RxMessage.ExtId;
     pmsg->rtr = RxMessage.RTR;
-    
+
     return RT_EOK;
 }
 

bsp/at32/Libraries/rt_drivers/drv_can.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -22,7 +22,7 @@ extern "C" {
 #define CAN_TX_MAILBOX0             (0x00000001U)  /*!< Tx Mailbox 0  */
 #define CAN_TX_MAILBOX1             (0x00000002U)  /*!< Tx Mailbox 1  */
 #define CAN_TX_MAILBOX2             (0x00000004U)  /*!< Tx Mailbox 2  */
-  
+
 struct at32_baud_rate_tab
 {
     rt_uint32_t baud_rate;

bsp/at32/Libraries/rt_drivers/drv_eth.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -28,8 +28,8 @@
 //#define DRV_DEBUG
 #define LOG_TAG             "drv.emac"
 
-#define ETH_RXBUFNB        	4
-#define ETH_TXBUFNB        	2
+#define ETH_RXBUFNB         4
+#define ETH_TXBUFNB         2
 
 #define LINK_THREAD_STACK_SIZE   256
 #define LINK_THREAD_PREORITY     21
@@ -131,14 +131,14 @@ void NVIC_Configuration(void)
     NVIC_SetVectorTable(NVIC_VectTab_FLASH, 0x0);
 
     /* 2 bit for pre-emption priority, 2 bits for subpriority */
-    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2); 
+    NVIC_PriorityGroupConfig(NVIC_PriorityGroup_2);
 
     /* Enable the Ethernet global Interrupt */
     NVIC_InitStructure.NVIC_IRQChannel = ETH_IRQn;
     NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
     NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
-    NVIC_Init(&NVIC_InitStructure);  
+    NVIC_Init(&NVIC_InitStructure);
 }
 
 /**
@@ -173,7 +173,7 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
 
-	/*MII Mode GPIO configuration*/
+    /*MII Mode GPIO configuration*/
 #ifdef MII_MODE
 /**********************MII Tx Pin Define****************************/
     /*
@@ -193,7 +193,7 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
-	/**********************MII Rx Pin Define****************************/
+    /**********************MII Rx Pin Define****************************/
 #if MII_RX_REMAP  /*IO PIN remaped*/
     /*
     ETH_MII_RX_DV-->PD8
@@ -208,7 +208,7 @@ void GPIO_Configuration(void)
     */
     GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10 | GPIO_Pins_11 | GPIO_Pins_12;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-    GPIO_Init(GPIOD, &GPIO_InitStructure); 
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
 
     GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_3;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@@ -233,11 +233,11 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOA, &GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;   
+    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;  
+    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_0 | GPIO_Pins_1 | GPIO_Pins_10;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOB, &GPIO_InitStructure);
 
@@ -255,8 +255,8 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_MaxSpeed = GPIO_MaxSpeed_50MHz;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
     GPIO_Init(GPIOB, &GPIO_InitStructure);
-	
-	/**********************RMII Rx Pin Define****************************/
+
+    /**********************RMII Rx Pin Define****************************/
 #if MII_RX_REMAP  /*IO PIN remaped*/
     /*
     ETH_RMII_RX_DV-->PD8
@@ -266,7 +266,7 @@ void GPIO_Configuration(void)
     */
     GPIO_InitStructure.GPIO_Pins = GPIO_Pins_8 | GPIO_Pins_9 | GPIO_Pins_10;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
-    GPIO_Init(GPIOD, &GPIO_InitStructure); 
+    GPIO_Init(GPIOD, &GPIO_InitStructure);
 
     GPIO_InitStructure.GPIO_Pins =  GPIO_Pins_1;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
@@ -282,7 +282,7 @@ void GPIO_Configuration(void)
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOA, &GPIO_InitStructure);
 
-    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;   
+    GPIO_InitStructure.GPIO_Pins = GPIO_Pins_4 | GPIO_Pins_5;
     GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IN_FLOATING;
     GPIO_Init(GPIOC, &GPIO_InitStructure);
 
@@ -314,7 +314,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
 
     RCC_AHBPeriphClockCmd(RCC_AHBPERIPH_ETHMAC | RCC_AHBPERIPH_ETHMACTX |
                           RCC_AHBPERIPH_ETHMACRX, ENABLE);
-    
+
     /* MII/RMII Media interface selection ------------------------------------------*/
 #ifdef MII_MODE /* Mode MII with AT32F407-EVAL  */
     GPIO_ETH_MediaInterfaceConfig(GPIO_ETH_MediaInterface_MII);
@@ -361,31 +361,31 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
     ETH_InitStructure.ETH_ChecksumOffload = ETH_ChecksumOffload_Enable;
 #endif
 
-    /*------------------------   DMA   -----------------------------------*/  
+    /*------------------------   DMA   -----------------------------------*/
 
-    /* When we use the Checksum offload feature, we need to enable the Store and Forward mode: 
-    the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum, 
+    /* When we use the Checksum offload feature, we need to enable the Store and Forward mode:
+    the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,
     if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */
-    ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable; 
-    ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;         
-    ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;     
-
-    ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;       
-    ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;   
-    ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;                                                          
-    ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;      
-    ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;                
-    ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;          
-    ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;                                                                 
+    ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;//ETH_DropTCPIPChecksumErrorFrame_Enable;
+    ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;
+    ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;
+
+    ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;
+    ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;
+    ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;
+    ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;
+    ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;
+    ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;
+    ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;
     ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;
 
     /* Configure Ethernet, check error */
     if(ETH_Init(&ETH_InitStructure, PHY_ADDRESS) == ((uint32_t)0)) {
         return RT_ERROR;
-    }    
+    }
 
     /* Enable DMA Receive interrupt (need to enable in this case Normal interrupt) */
-    ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);  
+    ETH_DMAITConfig(ETH_DMA_INT_NIS | ETH_DMA_INT_R, ENABLE);
 
     /* Initialize Tx Descriptors list: Chain Mode */
     ETH_DMATxDescChainInit(DMATxDscrTab, &Tx_Buff[0][0], ETH_TXBUFNB);
@@ -396,7 +396,7 @@ static rt_err_t rt_at32_eth_init(rt_device_t dev)
     ETH_MACAddressConfig(ETH_MAC_Address0, (u8*)&at32_eth_device.dev_addr[0]);
 
     /* Enable ETH transmition and recetion */
-    ETH_Start();    
+    ETH_Start();
 
     return RT_EOK;
 }
@@ -581,7 +581,7 @@ struct pbuf *rt_at32_eth_rx(rt_device_t dev)
             {
                 rt_uint32_t i;
                 rt_uint8_t *ptr = (rt_uint8_t*)(DMARxDescToGet->Buffer1Addr);
-                
+
                 AT32_ETH_PRINTF("rx_dump, len:%d\r\n", p->tot_len);
                 for(i=0; i<p->tot_len; i++)
                 {

bsp/at32/Libraries/rt_drivers/drv_eth.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *

bsp/at32/Libraries/rt_drivers/drv_flash.c

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *
@@ -160,14 +160,14 @@ int at32_flash_erase(rt_uint32_t addr, size_t size)
         addr += FLASH_PAGE_SIZE;
     }
 
-		FLASH_Lock();
-		
-__exit:    
+        FLASH_Lock();
+
+__exit:
     if(result != RT_EOK)
     {
         return result;
     }
-    
+
     return size;
 }
 
@@ -177,7 +177,7 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size);
 static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size);
 static int fal_flash_erase(long offset, size_t size);
 
-const struct fal_flash_dev at32_onchip_flash = 
+const struct fal_flash_dev at32_onchip_flash =
 {
     "onchip_flash",
     AT32_FLASH_START_ADRESS,

bsp/at32/Libraries/rt_drivers/drv_flash.h

@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2006-2018, RT-Thread Development Team
+ * Copyright (c) 2006-2021, RT-Thread Development Team
  *
  * SPDX-License-Identifier: Apache-2.0
  *