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BernardXiongBernardXiong
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Merge pull request #2058 from greedyhao/master
[WIP][🏅BSP][stm32] 添加野火stm32f767开发板bsp
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‎bsp/stm32/README.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@ STM32 系列 BSP 目前支持情况如下表所示：
99
| [stm32f407-atk-explorer](stm32f407-atk-explorer/) | 正点原子 F407 探索者开发板 |
1010
| [stm32f429-atk-apollo](stm32f429-atk-apollo/) | 正点原子 F429 阿波罗开发板 |
1111
| [stm32f429-fire-challenger](stm32f429-fire-challenger/) | 野火 F429 挑战者开发板 |
12+
| [stm32f767-fire-challenger](stm32f767-fire-challenger/) | 野火 F767 挑战者开发板 |
1213

1314
了解每个 BSP 的详细情况可以阅读该 BSP 下的 readme 文件，如需使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档：
1415

‎bsp/stm32/docs/STM32系列BSP添加教程.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@ STM32 BSP 由三部分组成，分别是 (1) 通用库、(2) BSP 模板和 (3)
5959
| ------- | ---- |
6060
| libraries/templates/stm32f10x | F1系列芯片模板 |
6161
| libraries/templates/stm32f4xx | F4系列芯片模板 |
62+
| libraries/templates/stm32f7xx | F7系列芯片模板 |
6263
| libraries/templates/stm32l4xx | L4系列芯片模板 |
6364

6465
拷贝 `stm32/libraries/templates/stm32f10x` 文件夹并改名为 `stm32/stm32f103-atk-nano` 。如下图所示：

‎bsp/stm32/libraries/HAL_Drivers/SConscript‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,9 @@ if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F1']):
4747
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F4']):
4848
src += ['drv_flash/drv_flash_f4.c']
4949

50+
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32F7']):
51+
src += ['drv_flash/drv_flash_f7.c']
52+
5053
if GetDepend(['BSP_USING_ON_CHIP_FLASH', 'SOC_SERIES_STM32L4']):
5154
src += ['drv_flash/drv_flash_l4.c']
5255

‎bsp/stm32/libraries/HAL_Drivers/config/f7/adc_config.h‎

Lines changed: 79 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,79 @@
1+
/*
2+
* Copyright (c) 2006-2018, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-12-06 zylx first version
9+
*/
10+
11+
#ifndef __ADC_CONFIG_H__
12+
#define __ADC_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#ifdef BSP_USING_ADC1
17+
#ifndef ADC1_CONFIG
18+
#define ADC1_CONFIG \
19+
{ \
20+
.Instance = ADC1, \
21+
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
22+
.Init.Resolution = ADC_RESOLUTION_12B, \
23+
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
24+
.Init.ScanConvMode = DISABLE, \
25+
.Init.EOCSelection = DISABLE, \
26+
.Init.ContinuousConvMode = DISABLE, \
27+
.Init.NbrOfConversion = 1, \
28+
.Init.DiscontinuousConvMode = DISABLE, \
29+
.Init.NbrOfDiscConversion = 0, \
30+
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
31+
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
32+
.Init.DMAContinuousRequests = DISABLE, \
33+
}
34+
#endif /* ADC1_CONFIG */
35+
#endif /* BSP_USING_ADC1 */
36+
37+
#ifdef BSP_USING_ADC2
38+
#ifndef ADC2_CONFIG
39+
#define ADC2_CONFIG \
40+
{ \
41+
.Instance = ADC2, \
42+
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
43+
.Init.Resolution = ADC_RESOLUTION_12B, \
44+
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
45+
.Init.ScanConvMode = DISABLE, \
46+
.Init.EOCSelection = DISABLE, \
47+
.Init.ContinuousConvMode = DISABLE, \
48+
.Init.NbrOfConversion = 1, \
49+
.Init.DiscontinuousConvMode = DISABLE, \
50+
.Init.NbrOfDiscConversion = 0, \
51+
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
52+
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
53+
.Init.DMAContinuousRequests = DISABLE, \
54+
}
55+
#endif /* ADC2_CONFIG */
56+
#endif /* BSP_USING_ADC2 */
57+
58+
#ifdef BSP_USING_ADC3
59+
#ifndef ADC3_CONFIG
60+
#define ADC3_CONFIG \
61+
{ \
62+
.Instance = ADC3, \
63+
.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV4, \
64+
.Init.Resolution = ADC_RESOLUTION_12B, \
65+
.Init.DataAlign = ADC_DATAALIGN_RIGHT, \
66+
.Init.ScanConvMode = DISABLE, \
67+
.Init.EOCSelection = DISABLE, \
68+
.Init.ContinuousConvMode = DISABLE, \
69+
.Init.NbrOfConversion = 1, \
70+
.Init.DiscontinuousConvMode = DISABLE, \
71+
.Init.NbrOfDiscConversion = 0, \
72+
.Init.ExternalTrigConv = ADC_SOFTWARE_START, \
73+
.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE, \
74+
.Init.DMAContinuousRequests = DISABLE, \
75+
}
76+
#endif /* ADC3_CONFIG */
77+
#endif /* BSP_USING_ADC3 */
78+
79+
#endif /* __ADC_CONFIG_H__ */

‎bsp/stm32/libraries/HAL_Drivers/config/f7/spi_config.h‎

Lines changed: 133 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,133 @@
1+
/*
2+
* Copyright (c) 2006-2018, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-11-06 SummerGift change to new framework
9+
*/
10+
11+
#ifndef __SPI_CONFIG_H__
12+
#define __SPI_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#ifdef BSP_USING_SPI1
17+
#define SPI1_BUS_CONFIG \
18+
{ \
19+
.Instance = SPI1, \
20+
.bus_name = "spi1", \
21+
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
22+
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
23+
.dma_rx.Instance = DMA2_Stream2, \
24+
.dma_rx.channel = DMA_CHANNEL_3, \
25+
.dma_rx.dma_irq = DMA2_Stream2_IRQn, \
26+
.dma_tx.Instance = DMA2_Stream3, \
27+
.dma_tx.channel = DMA_CHANNEL_3, \
28+
.dma_tx.dma_irq = DMA2_Stream3_IRQn, \
29+
}
30+
31+
#define SPI1_DMA_RX_IRQHandler DMA2_Stream2_IRQHandler
32+
#define SPI1_DMA_TX_IRQHandler DMA2_Stream3_IRQHandler
33+
#endif
34+
35+
#ifdef BSP_USING_SPI2
36+
#define SPI2_BUS_CONFIG \
37+
{ \
38+
.Instance = SPI2, \
39+
.bus_name = "spi2", \
40+
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
41+
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
42+
.dma_rx.Instance = DMA1_Stream3, \
43+
.dma_rx.channel = DMA_CHANNEL_0, \
44+
.dma_rx.dma_irq = DMA1_Stream3_IRQn, \
45+
.dma_tx.Instance = DMA1_Stream4, \
46+
.dma_tx.channel = DMA_CHANNEL_0, \
47+
.dma_tx.dma_irq = DMA1_Stream4_IRQn, \
48+
}
49+
50+
#define SPI2_DMA_RX_IRQHandler DMA1_Stream3_IRQHandler
51+
#define SPI2_DMA_TX_IRQHandler DMA1_Stream4_IRQHandler
52+
#endif
53+
54+
#ifdef BSP_USING_SPI3
55+
#define SPI3_BUS_CONFIG \
56+
{ \
57+
.Instance = SPI3, \
58+
.bus_name = "spi3", \
59+
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
60+
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA1EN, \
61+
.dma_rx.Instance = DMA1_Stream0, \
62+
.dma_rx.channel = DMA_CHANNEL_0, \
63+
.dma_rx.dma_irq = DMA1_Stream0_IRQn, \
64+
.dma_tx.Instance = DMA1_Stream7, \
65+
.dma_tx.channel = DMA_CHANNEL_0, \
66+
.dma_tx.dma_irq = DMA1_Stream7_IRQn, \
67+
}
68+
69+
#define SPI3_DMA_RX_IRQHandler DMA1_Stream0_IRQHandler
70+
#define SPI3_DMA_TX_IRQHandler DMA1_Stream7_IRQHandler
71+
#endif
72+
73+
#ifdef BSP_USING_SPI4
74+
#define SPI4_BUS_CONFIG \
75+
{ \
76+
.Instance = SPI4, \
77+
.bus_name = "spi4", \
78+
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
79+
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
80+
.dma_rx.Instance = DMA2_Stream0, \
81+
.dma_rx.channel = DMA_CHANNEL_4, \
82+
.dma_rx.dma_irq = DMA2_Stream0_IRQn, \
83+
.dma_tx.Instance = DMA2_Stream1, \
84+
.dma_tx.channel = DMA_CHANNEL_4, \
85+
.dma_tx.dma_irq = DMA2_Stream1_IRQn, \
86+
}
87+
88+
#define SPI4_DMA_RX_IRQHandler DMA2_Stream0_IRQHandler
89+
#define SPI4_DMA_TX_IRQHandler DMA2_Stream1_IRQHandler
90+
#endif
91+
92+
#ifdef BSP_USING_SPI5
93+
#define SPI5_BUS_CONFIG \
94+
{ \
95+
.Instance = SPI5, \
96+
.bus_name = "spi5", \
97+
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
98+
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
99+
.dma_rx.Instance = DMA2_Stream3, \
100+
.dma_rx.channel = DMA_CHANNEL_2, \
101+
.dma_rx.dma_irq = DMA2_Stream3_IRQn, \
102+
.dma_tx.Instance = DMA2_Stream4, \
103+
.dma_tx.channel = DMA_CHANNEL_2, \
104+
.dma_tx.dma_irq = DMA2_Stream4_IRQn, \
105+
}
106+
107+
#define SPI5_DMA_RX_IRQHandler DMA2_Stream3_IRQHandler
108+
#define SPI5_DMA_TX_IRQHandler DMA2_Stream4_IRQHandler
109+
#endif
110+
111+
#ifdef BSP_USING_SPI6
112+
#define SPI5_BUS_CONFIG \
113+
{ \
114+
.Instance = SPI6, \
115+
.bus_name = "spi6", \
116+
.dma_rx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
117+
.dma_tx.dma_rcc = RCC_AHB1ENR_DMA2EN, \
118+
.dma_rx.Instance = DMA2_Stream6, \
119+
.dma_rx.channel = DMA_CHANNEL_1, \
120+
.dma_rx.dma_irq = DMA2_Stream6_IRQn, \
121+
.dma_tx.Instance = DMA2_Stream5, \
122+
.dma_tx.channel = DMA_CHANNEL_1, \
123+
.dma_tx.dma_irq = DMA2_Stream5_IRQn, \
124+
}
125+
126+
#define SPI6_DMA_RX_IRQHandler DMA2_Stream6_IRQHandler
127+
#define SPI6_DMA_TX_IRQHandler DMA2_Stream5_IRQHandler
128+
#endif
129+
130+
#endif /*__SPI_CONFIG_H__ */
131+
132+
133+

‎bsp/stm32/libraries/HAL_Drivers/config/f7/uart_config.h‎

Lines changed: 91 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,91 @@
1+
/*
2+
* Copyright (c) 2006-2018, RT-Thread Development Team
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*
6+
* Change Logs:
7+
* Date Author Notes
8+
* 2018-10-30 SummerGift change to new framework
9+
*/
10+
11+
#ifndef __UART_CONFIG_H__
12+
#define __UART_CONFIG_H__
13+
14+
#include <rtthread.h>
15+
16+
#if defined(BSP_USING_UART1)
17+
#define UART1_CONFIG \
18+
{ \
19+
.name = "uart1", \
20+
.Instance = USART1, \
21+
.irq_type = USART1_IRQn, \
22+
.dma.stream_channel.Instance = DMA2_Stream5, \
23+
.dma.stream_channel.channel = DMA_CHANNEL_4, \
24+
.dma_rcc = RCC_AHB1ENR_DMA2EN, \
25+
.dma_irq = DMA2_Stream5_IRQn, \
26+
}
27+
28+
#define USART1_RX_DMA_ISR DMA2_Stream5_IRQHandler
29+
#endif
30+
31+
#if defined(BSP_USING_UART2)
32+
#define UART2_CONFIG \
33+
{ \
34+
.name = "uart2", \
35+
.Instance = USART2, \
36+
.irq_type = USART2_IRQn, \
37+
.dma.stream_channel.Instance = DMA1_Stream5, \
38+
.dma.stream_channel.channel = DMA_CHANNEL_4, \
39+
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
40+
.dma_irq = DMA1_Stream5_IRQn, \
41+
}
42+
43+
#define USART2_RX_DMA_ISR DMA1_Stream5_IRQHandler
44+
#endif
45+
46+
#if defined(BSP_USING_UART3)
47+
#define UART3_CONFIG \
48+
{ \
49+
.name = "uart3", \
50+
.Instance = USART3, \
51+
.irq_type = USART3_IRQn, \
52+
.dma.stream_channel.Instance = DMA1_Stream1, \
53+
.dma.stream_channel.channel = DMA_CHANNEL_4, \
54+
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
55+
.dma_irq = DMA1_Stream1_IRQn, \
56+
}
57+
58+
#define USART3_RX_DMA_ISR DMA1_Stream1_IRQHandler
59+
#endif
60+
61+
#if defined(BSP_USING_UART4)
62+
#define UART4_CONFIG \
63+
{ \
64+
.name = "uart4", \
65+
.Instance = UART4, \
66+
.irq_type = UART4_IRQn, \
67+
.dma.stream_channel.Instance = DMA1_Stream2, \
68+
.dma.stream_channel.channel = DMA_CHANNEL_4, \
69+
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
70+
.dma_irq = DMA1_Stream2_IRQn, \
71+
}
72+
73+
#define USART4_RX_DMA_ISR DMA1_Stream2_IRQHandler
74+
#endif
75+
76+
#if defined(BSP_USING_UART5)
77+
#define UART5_CONFIG \
78+
{ \
79+
.name = "uart5", \
80+
.Instance = UART5, \
81+
.irq_type = UART5_IRQn, \
82+
.dma.stream_channel.Instance = DMA1_Stream0, \
83+
.dma.stream_channel.channel = DMA_CHANNEL_4, \
84+
.dma_rcc = RCC_AHB1ENR_DMA1EN, \
85+
.dma_irq = DMA1_Stream0_IRQn, \
86+
}
87+
88+
#define USART5_RX_DMA_ISR DMA1_Stream0_IRQHandler
89+
#endif
90+
91+
#endif

‎bsp/stm32/libraries/HAL_Drivers/drv_adc.c‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
* Change Logs:
77
* Date Author Notes
88
* 2018-12-05 zylx first version
9+
* 2018-12-12 greedyhao Porting for stm32f7xx
910
*/
1011

1112
#include <board.h>
@@ -126,7 +127,7 @@ static rt_uint32_t stm32_adc_get_channel(rt_uint32_t channel)
126127
case 17:
127128
stm32_channel = ADC_CHANNEL_17;
128129
break;
129-
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
130+
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
130131
case 18:
131132
stm32_channel = ADC_CHANNEL_18;
132133
break;
@@ -148,7 +149,7 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
148149

149150
#if defined(SOC_SERIES_STM32F1)
150151
if (channel <= 17)
151-
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
152+
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
152153
if (channel <= 18)
153154
#endif
154155
{
@@ -159,20 +160,20 @@ static rt_err_t stm32_get_adc_value(struct rt_adc_device *device, rt_uint32_t ch
159160
{
160161
#if defined(SOC_SERIES_STM32F1)
161162
LOG_E("ADC channel must be between 0 and 17.");
162-
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
163+
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
163164
LOG_E("ADC channel must be between 0 and 18.");
164165
#endif
165166
return -RT_ERROR;
166167
}
167168
ADC_ChanConf.Rank = 1;
168169
#if defined(SOC_SERIES_STM32F1)
169170
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_55CYCLES_5;
170-
#elif defined(SOC_SERIES_STM32F4)
171+
#elif defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
171172
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_112CYCLES;
172173
#elif defined(SOC_SERIES_STM32L4)
173174
ADC_ChanConf.SamplingTime = ADC_SAMPLETIME_247CYCLES_5;
174175
#endif
175-
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32L4)
176+
#if defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4)
176177
ADC_ChanConf.Offset = 0;
177178
#endif
178179
#ifdef SOC_SERIES_STM32L4

‎bsp/stm32/libraries/HAL_Drivers/drv_config.h‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -22,6 +22,10 @@
2222
#include "f4/uart_config.h"
2323
#include "f4/spi_config.h"
2424
#include "f4/adc_config.h"
25+
#elif defined(SOC_SERIES_STM32F7)
26+
#include "f7/uart_config.h"
27+
#include "f7/spi_config.h"
28+
#include "f7/adc_config.h"
2529
#elif defined(SOC_SERIES_STM32L4)
2630
#include "l4/uart_config.h"
2731
#include "l4/spi_config.h"

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