11/*
2- * Copyright (c) 2006-2021 , RT-Thread Development Team
2+ * Copyright (c) 2006-2018 , RT-Thread Development Team
33 *
44 * SPDX-License-Identifier: Apache-2.0
55 *
66 * Change Logs:
77 * Date Author Notes
88 * 2018-11-06 SummerGift first version
9+ * 2021-03-27 xph open rtc clk to support ble stack
910 */
1011
1112#include "board.h"
@@ -26,9 +27,7 @@ void SystemClock_Config(void)
2627 /** Initializes the RCC Oscillators according to the specified parameters
2728 * in the RCC_OscInitTypeDef structure.
2829 */
29- RCC_OscInitStruct .OscillatorType = RCC_OSCILLATORTYPE_HSI |RCC_OSCILLATORTYPE_LSI1
30- |RCC_OSCILLATORTYPE_HSE |RCC_OSCILLATORTYPE_LSE
31- |RCC_OSCILLATORTYPE_MSI ;
30+ RCC_OscInitStruct .OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI1 | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI ;
3231 RCC_OscInitStruct .HSEState = RCC_HSE_ON ;
3332 RCC_OscInitStruct .LSEState = RCC_LSE_ON ;
3433 RCC_OscInitStruct .HSIState = RCC_HSI_ON ;
@@ -50,9 +49,7 @@ void SystemClock_Config(void)
5049 }
5150 /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
5251 */
53- RCC_ClkInitStruct .ClockType = RCC_CLOCKTYPE_HCLK4 |RCC_CLOCKTYPE_HCLK2
54- |RCC_CLOCKTYPE_HCLK |RCC_CLOCKTYPE_SYSCLK
55- |RCC_CLOCKTYPE_PCLK1 |RCC_CLOCKTYPE_PCLK2 ;
52+ RCC_ClkInitStruct .ClockType = RCC_CLOCKTYPE_HCLK4 | RCC_CLOCKTYPE_HCLK2 | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2 ;
5653 RCC_ClkInitStruct .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK ;
5754 RCC_ClkInitStruct .AHBCLKDivider = RCC_SYSCLK_DIV1 ;
5855 RCC_ClkInitStruct .APB1CLKDivider = RCC_HCLK_DIV1 ;
@@ -64,22 +61,12 @@ void SystemClock_Config(void)
6461 {
6562 Error_Handler ();
6663 }
67- /** Initializes the peripherals clocks
68- */
69- PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_SMPS |RCC_PERIPHCLK_RTC
70- |RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_LPUART1
71- |RCC_PERIPHCLK_USB |RCC_PERIPHCLK_ADC ;
72- PeriphClkInitStruct .PLLSAI1 .PLLN = 24 ;
73- PeriphClkInitStruct .PLLSAI1 .PLLP = RCC_PLLP_DIV2 ;
74- PeriphClkInitStruct .PLLSAI1 .PLLQ = RCC_PLLQ_DIV2 ;
75- PeriphClkInitStruct .PLLSAI1 .PLLR = RCC_PLLR_DIV2 ;
76- PeriphClkInitStruct .PLLSAI1 .PLLSAI1ClockOut = RCC_PLLSAI1_USBCLK |RCC_PLLSAI1_ADCCLK ;
64+ PeriphClkInitStruct .PeriphClockSelection = RCC_PERIPHCLK_SMPS | RCC_PERIPHCLK_RFWAKEUP | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_LPUART1 ;
7765 PeriphClkInitStruct .Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2 ;
7866 PeriphClkInitStruct .Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1 ;
79- PeriphClkInitStruct .UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1 ;
80- PeriphClkInitStruct .AdcClockSelection = RCC_ADCCLKSOURCE_PLLSAI1 ;
81- PeriphClkInitStruct .RTCClockSelection = RCC_RTCCLKSOURCE_LSI ;
82- PeriphClkInitStruct .SmpsClockSelection = RCC_SMPSCLKSOURCE_HSI ;
67+ PeriphClkInitStruct .RTCClockSelection = RCC_RTCCLKSOURCE_LSE ;
68+ PeriphClkInitStruct .RFWakeUpClockSelection = RCC_RFWKPCLKSOURCE_LSE ;
69+ PeriphClkInitStruct .SmpsClockSelection = RCC_SMPSCLKSOURCE_HSE ;
8370 PeriphClkInitStruct .SmpsDivSelection = RCC_SMPSCLKDIV_RANGE1 ;
8471 if (HAL_RCCEx_PeriphCLKConfig (& PeriphClkInitStruct ) != HAL_OK )
8572 {
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