11/*
2- * File : drv_sdio.c
3- * This file is part of RT-Thread RTOS
4- * COPYRIGHT (C) 2017, RT-Thread Development Team
2+ * Copyright (c) 2006-2021, RT-Thread Development Team
53 *
6- * This program is free software; you can redistribute it and/or modify
7- * it under the terms of the GNU General Public License as published by
8- * the Free Software Foundation; either version 2 of the License, or
9- * (at your option) any later version.
10- *
11- * This program is distributed in the hope that it will be useful,
12- * but WITHOUT ANY WARRANTY; without even the implied warranty of
13- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14- * GNU General Public License for more details.
15- *
16- * You should have received a copy of the GNU General Public License along
17- * with this program; if not, write to the Free Software Foundation, Inc.,
18- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
4+ * SPDX-License-Identifier: Apache-2.0
195 *
206 * Change Logs:
217 * Date Author Notes
3420
3521
3622#define DBG_TAG "MMC"
37- // #define DBG_LVL DBG_LOG
38- // #define DBG_LVL DBG_INFO
23+ // #define DBG_LVL DBG_LOG
24+ // #define DBG_LVL DBG_INFO
3925#define DBG_LVL DBG_WARNING
40- // #define DBG_LVL DBG_ERROR
26+ // #define DBG_LVL DBG_ERROR
4127#include <rtdbg.h>
4228
4329#ifdef RT_USING_SDIO
4733struct mmc_xfe_des
4834{
4935 rt_uint32_t size ; /* block size */
50- rt_uint32_t num ; /* block num */
51- rt_uint8_t * buff ; /* buff addr */
52- rt_uint32_t flag ; /* write or read or stream */
53- #define MMC_DATA_WRITE (1 << 0)
54- #define MMC_DATA_READ (1 << 1)
55- #define MMC_DATA_STREAM (1 << 2)
36+ rt_uint32_t num ; /* block num */
37+ rt_uint8_t * buff ; /* buff addr */
38+ rt_uint32_t flag ; /* write or read or stream */
39+ #define MMC_DATA_WRITE (1 << 0)
40+ #define MMC_DATA_READ (1 << 1)
41+ #define MMC_DATA_STREAM (1 << 2)
5642};
5743
5844struct mmc_flag
@@ -71,7 +57,7 @@ struct sdio_drv
7157 tina_mmc_t mmc_des ;
7258 rt_uint8_t * mmc_buf ;
7359 rt_uint8_t usedma ;
74-
60+
7561};
7662
7763#ifdef CONFIG_MMC_USE_DMA
@@ -136,7 +122,7 @@ static int mmc_update_clk(tina_mmc_t mmc)
136122 mmc -> risr_reg = mmc -> risr_reg ;
137123 return RT_EOK ;
138124}
139-
125+
140126static rt_err_t mmc_trans_data_by_dma (tina_mmc_t mmc , struct mmc_xfe_des * xfe )
141127{
142128 ALIGN (32 ) static struct mmc_des_v4p1 pdes [128 ]; // mast ALIGN(32)
@@ -145,7 +131,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
145131 unsigned length = xfe -> size * xfe -> num ;
146132 unsigned buff_frag_num = length >> SDXC_DES_NUM_SHIFT ;
147133 unsigned remain = length & (SDXC_DES_BUFFER_MAX_LEN - 1 );
148-
134+
149135 if (remain )
150136 {
151137 buff_frag_num ++ ;
@@ -156,7 +142,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
156142 }
157143 memset (pdes , 0 , sizeof (pdes ));
158144 mmu_clean_dcache ((rt_uint32_t )(xfe -> buff ), length );
159- for (i = 0 , des_idx = 0 ; i < buff_frag_num ; i ++ , des_idx ++ )
145+ for (i = 0 , des_idx = 0 ; i < buff_frag_num ; i ++ , des_idx ++ )
160146 {
161147 // memset((void*)&pdes[des_idx], 0, sizeof(struct mmc_v4p1));
162148 pdes [des_idx ].des_chain = 1 ;
@@ -182,8 +168,8 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
182168 pdes [des_idx ].last_des = 1 ;
183169 pdes [des_idx ].end_of_ring = 1 ;
184170 pdes [des_idx ].buf_addr_ptr2 = 0 ;
185- }
186- else
171+ }
172+ else
187173 {
188174 pdes [des_idx ].buf_addr_ptr2 = (unsigned long )& pdes [des_idx + 1 ];
189175 }
@@ -217,7 +203,7 @@ static rt_err_t mmc_trans_data_by_dma(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
217203 mmc -> dmac_reg = (1 << 1 ) | (1 << 7 ); /* idma on */
218204 rval = mmc -> idie_reg & (~3 );
219205 if (xfe -> flag == MMC_DATA_WRITE )
220- rval |= (1 << 0 );
206+ rval |= (1 << 0 );
221207 else
222208 rval |= (1 << 1 );
223209 mmc -> idie_reg = rval ;
@@ -236,7 +222,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
236222
237223 if (xfe -> flag == MMC_DATA_WRITE )
238224 {
239- for (i = 0 ; i < (byte_cnt >> 2 ); i ++ )
225+ for (i = 0 ; i < (byte_cnt >> 2 ); i ++ )
240226 {
241227 while (-- timeout && (mmc -> star_reg & (1 << 3 )));
242228
@@ -251,7 +237,7 @@ static rt_err_t mmc_trans_data_by_cpu(tina_mmc_t mmc, struct mmc_xfe_des *xfe)
251237 }
252238 else
253239 {
254- for (i = 0 ; i < (byte_cnt >> 2 ); i ++ )
240+ for (i = 0 ; i < (byte_cnt >> 2 ); i ++ )
255241 {
256242 while (-- timeout && (mmc -> star_reg & (1 << 2 )));
257243
@@ -290,7 +276,7 @@ static rt_err_t mmc_config_clock(tina_mmc_t mmc, int clk)
290276 {
291277 mmc_set_clk (SDMMC1 , clk );
292278 }
293-
279+
294280 /* Re-enable card clock */
295281 rval = mmc -> ckcr_reg ;
296282 rval |= (0x1 << 16 ); //(3 << 16);
@@ -383,7 +369,7 @@ static int mmc_send_cmd(struct rt_mmcsd_host *host, struct rt_mmcsd_cmd *cmd)
383369 cmdval |= (1 << 7 );
384370 if ((resp_type (cmd ) != RESP_R3 ) && (resp_type (cmd ) != RESP_R4 ))
385371 cmdval |= (1 << 8 );
386-
372+
387373 if (data )
388374 {
389375 cmdval |= (1 << 9 ) | (1 << 13 );
@@ -606,7 +592,7 @@ static void sdio_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *r
606592
607593 memset (& sdio -> flag , 0 , sizeof (struct mmc_flag ));
608594 mmc_send_cmd (host , req -> cmd );
609-
595+
610596 return ;
611597}
612598
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