|
| 1 | +/* |
| 2 | + * Copyright (C) 2018 Shanghai Eastsoft Microelectronics Co., Ltd. |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: Apache-2.0 |
| 5 | + * |
| 6 | + * Change Logs: |
| 7 | + * Date Author Notes |
| 8 | + * 2019-3-19 wangyq the first version |
| 9 | + */ |
| 10 | + |
| 11 | +#include <rthw.h> |
| 12 | +#include <rtthread.h> |
| 13 | +#include <rtdevice.h> |
| 14 | +#include <drv_hwtimer.h> |
| 15 | +#include <board.h> |
| 16 | +#include <ald_cmu.h> |
| 17 | +#include <ald_timer.h> |
| 18 | + |
| 19 | +#ifdef RT_USING_HWTIMER |
| 20 | + |
| 21 | +struct es32f0_hwtimer_dev |
| 22 | +{ |
| 23 | + rt_hwtimer_t parent; |
| 24 | + timer_handle_t *hwtimer_periph; |
| 25 | + IRQn_Type IRQn; |
| 26 | +}; |
| 27 | + |
| 28 | +#ifdef BSP_USING_HWTIMER0 |
| 29 | +static struct es32f0_hwtimer_dev hwtimer0; |
| 30 | + |
| 31 | +void BS16T0_Handler(void) |
| 32 | +{ |
| 33 | + timer_clear_flag_status(hwtimer0.hwtimer_periph, TIMER_FLAG_UPDATE); |
| 34 | + rt_device_hwtimer_isr(&hwtimer0.parent); |
| 35 | + |
| 36 | + if (HWTIMER_MODE_ONESHOT == hwtimer0.parent.mode) |
| 37 | + { |
| 38 | + timer_base_stop(hwtimer0.hwtimer_periph); |
| 39 | + } |
| 40 | +} |
| 41 | +#endif |
| 42 | + |
| 43 | +#ifdef BSP_USING_HWTIMER1 |
| 44 | +static struct es32f0_hwtimer_dev hwtimer1; |
| 45 | + |
| 46 | +void BS16T1_UART2_Handler(void) |
| 47 | +{ |
| 48 | + if (timer_get_it_status(hwtimer1.hwtimer_periph, TIMER_IT_UPDATE) && |
| 49 | + timer_get_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE)) |
| 50 | + { |
| 51 | + timer_clear_flag_status(hwtimer1.hwtimer_periph, TIMER_FLAG_UPDATE); |
| 52 | + rt_device_hwtimer_isr(&hwtimer1.parent); |
| 53 | + |
| 54 | + if (HWTIMER_MODE_ONESHOT == hwtimer1.parent.mode) |
| 55 | + { |
| 56 | + timer_base_stop(hwtimer1.hwtimer_periph); |
| 57 | + } |
| 58 | + } |
| 59 | +} |
| 60 | +#endif |
| 61 | + |
| 62 | +#ifdef BSP_USING_HWTIMER2 |
| 63 | +static struct es32f0_hwtimer_dev hwtimer2; |
| 64 | + |
| 65 | +void BS16T2_UART3_Handler(void) |
| 66 | +{ |
| 67 | + if (timer_get_it_status(hwtimer2.hwtimer_periph, TIMER_IT_UPDATE) && |
| 68 | + timer_get_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE)) |
| 69 | + { |
| 70 | + timer_clear_flag_status(hwtimer2.hwtimer_periph, TIMER_FLAG_UPDATE); |
| 71 | + rt_device_hwtimer_isr(&hwtimer2.parent); |
| 72 | + |
| 73 | + if (HWTIMER_MODE_ONESHOT == hwtimer2.parent.mode) |
| 74 | + { |
| 75 | + timer_base_stop(hwtimer2.hwtimer_periph); |
| 76 | + } |
| 77 | + } |
| 78 | +} |
| 79 | +#endif |
| 80 | + |
| 81 | +#ifdef BSP_USING_HWTIMER3 |
| 82 | +static struct es32f0_hwtimer_dev hwtimer3; |
| 83 | +/* can not use when DAC0 Handler is enabled */ |
| 84 | +void BS16T3_DAC0_Handler(void) |
| 85 | +{ |
| 86 | + /* if BS16T3 it */ |
| 87 | + if (timer_get_it_status(hwtimer3.hwtimer_periph, TIMER_IT_UPDATE) && |
| 88 | + timer_get_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE)) |
| 89 | + { |
| 90 | + timer_clear_flag_status(hwtimer3.hwtimer_periph, TIMER_FLAG_UPDATE); |
| 91 | + rt_device_hwtimer_isr(&hwtimer3.parent); |
| 92 | + |
| 93 | + if (HWTIMER_MODE_ONESHOT == hwtimer3.parent.mode) |
| 94 | + { |
| 95 | + timer_base_stop(hwtimer3.hwtimer_periph); |
| 96 | + } |
| 97 | + } |
| 98 | +} |
| 99 | +#endif |
| 100 | + |
| 101 | +static struct rt_hwtimer_info es32f0_hwtimer_info = |
| 102 | +{ |
| 103 | + 48000000, /* maximum count frequency */ |
| 104 | + 1, /* minimum count frequency */ |
| 105 | + 65535, /* counter maximum value */ |
| 106 | + HWTIMER_CNTMODE_UP |
| 107 | +}; |
| 108 | + |
| 109 | +static void es32f0_hwtimer_init(rt_hwtimer_t *timer, rt_uint32_t state) |
| 110 | +{ |
| 111 | + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; |
| 112 | + |
| 113 | + RT_ASSERT(hwtimer != RT_NULL); |
| 114 | + |
| 115 | + if (1 == state) |
| 116 | + { |
| 117 | + timer_base_init(hwtimer->hwtimer_periph); |
| 118 | + timer_interrupt_config(hwtimer->hwtimer_periph, TIMER_IT_UPDATE, ENABLE); |
| 119 | + NVIC_EnableIRQ(hwtimer->IRQn); |
| 120 | + } |
| 121 | + hwtimer->parent.freq = cmu_get_pclk1_clock(); |
| 122 | + es32f0_hwtimer_info.maxfreq = cmu_get_pclk1_clock(); |
| 123 | + es32f0_hwtimer_info.minfreq = cmu_get_pclk1_clock(); |
| 124 | +} |
| 125 | + |
| 126 | +static rt_err_t es32f0_hwtimer_start(rt_hwtimer_t *timer, |
| 127 | + rt_uint32_t cnt, |
| 128 | + rt_hwtimer_mode_t mode) |
| 129 | +{ |
| 130 | + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; |
| 131 | + |
| 132 | + RT_ASSERT(hwtimer != RT_NULL); |
| 133 | + |
| 134 | + WRITE_REG(hwtimer->hwtimer_periph->perh->AR, cnt); |
| 135 | + timer_base_start(hwtimer->hwtimer_periph); |
| 136 | + |
| 137 | + return RT_EOK; |
| 138 | +} |
| 139 | + |
| 140 | +static void es32f0_hwtimer_stop(rt_hwtimer_t *timer) |
| 141 | +{ |
| 142 | + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; |
| 143 | + |
| 144 | + RT_ASSERT(hwtimer != RT_NULL); |
| 145 | + |
| 146 | + timer_base_stop(hwtimer->hwtimer_periph); |
| 147 | +} |
| 148 | + |
| 149 | +static rt_uint32_t es32f0_hwtimer_count_get(rt_hwtimer_t *timer) |
| 150 | +{ |
| 151 | + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; |
| 152 | + uint32_t hwtimer_count = 0; |
| 153 | + |
| 154 | + RT_ASSERT(hwtimer != RT_NULL); |
| 155 | + |
| 156 | + hwtimer_count = READ_REG(hwtimer->hwtimer_periph->perh->COUNT); |
| 157 | + |
| 158 | + return hwtimer_count; |
| 159 | +} |
| 160 | + |
| 161 | +static rt_err_t es32f0_hwtimer_control(rt_hwtimer_t *timer, |
| 162 | + rt_uint32_t cmd, |
| 163 | + void *args) |
| 164 | +{ |
| 165 | + rt_err_t ret = RT_EOK; |
| 166 | + rt_uint32_t freq = 0; |
| 167 | + struct es32f0_hwtimer_dev *hwtimer = (struct es32f0_hwtimer_dev *)timer->parent.user_data; |
| 168 | + |
| 169 | + RT_ASSERT(hwtimer != RT_NULL); |
| 170 | + |
| 171 | + switch (cmd) |
| 172 | + { |
| 173 | + case HWTIMER_CTRL_FREQ_SET: |
| 174 | + freq = *(rt_uint32_t *)args; |
| 175 | + if (freq != cmu_get_pclk1_clock()) |
| 176 | + { |
| 177 | + ret = -RT_ERROR; |
| 178 | + } |
| 179 | + break; |
| 180 | + |
| 181 | + case HWTIMER_CTRL_STOP: |
| 182 | + timer_base_stop(hwtimer->hwtimer_periph); |
| 183 | + break; |
| 184 | + |
| 185 | + default: |
| 186 | + ret = RT_EINVAL; |
| 187 | + break; |
| 188 | + } |
| 189 | + |
| 190 | + return ret; |
| 191 | +} |
| 192 | + |
| 193 | +static struct rt_hwtimer_ops es32f0_hwtimer_ops = |
| 194 | +{ |
| 195 | + es32f0_hwtimer_init, |
| 196 | + es32f0_hwtimer_start, |
| 197 | + es32f0_hwtimer_stop, |
| 198 | + es32f0_hwtimer_count_get, |
| 199 | + es32f0_hwtimer_control |
| 200 | +}; |
| 201 | + |
| 202 | +int rt_hw_hwtimer_init(void) |
| 203 | +{ |
| 204 | + rt_err_t ret = RT_EOK; |
| 205 | + |
| 206 | +#ifdef BSP_USING_HWTIMER0 |
| 207 | + static timer_handle_t _hwtimer_periph0; |
| 208 | + _hwtimer_periph0.perh = BS16T0; |
| 209 | + hwtimer0.IRQn = BS16T0_IRQn; |
| 210 | + hwtimer0.hwtimer_periph = &_hwtimer_periph0; |
| 211 | + hwtimer0.parent.info = &es32f0_hwtimer_info; |
| 212 | + hwtimer0.parent.ops = &es32f0_hwtimer_ops; |
| 213 | + ret = rt_device_hwtimer_register(&hwtimer0.parent, "timer0", &hwtimer0); |
| 214 | +#endif |
| 215 | + |
| 216 | +#ifdef BSP_USING_HWTIMER1 |
| 217 | + static timer_handle_t _hwtimer_periph1; |
| 218 | + _hwtimer_periph1.perh = BS16T1; |
| 219 | + hwtimer1.IRQn = BS16T1_UART2_IRQn; |
| 220 | + hwtimer1.hwtimer_periph = &_hwtimer_periph1; |
| 221 | + hwtimer1.parent.info = &es32f0_hwtimer_info; |
| 222 | + hwtimer1.parent.ops = &es32f0_hwtimer_ops; |
| 223 | + ret = rt_device_hwtimer_register(&hwtimer1.parent, "timer1", &hwtimer1); |
| 224 | +#endif |
| 225 | + |
| 226 | +#ifdef BSP_USING_HWTIMER2 |
| 227 | + static timer_handle_t _hwtimer_periph2; |
| 228 | + _hwtimer_periph2.perh = BS16T2; |
| 229 | + hwtimer2.IRQn = BS16T2_UART3_IRQn; |
| 230 | + hwtimer2.hwtimer_periph = &_hwtimer_periph2; |
| 231 | + hwtimer2.parent.info = &es32f0_hwtimer_info; |
| 232 | + hwtimer2.parent.ops = &es32f0_hwtimer_ops; |
| 233 | + ret = rt_device_hwtimer_register(&hwtimer2.parent, "timer2", &hwtimer2); |
| 234 | +#endif |
| 235 | + |
| 236 | +#ifdef BSP_USING_HWTIMER3 |
| 237 | + static timer_handle_t _hwtimer_periph3; |
| 238 | + _hwtimer_periph3.perh = BS16T3; |
| 239 | + hwtimer3.IRQn = BS16T3_DAC0_IRQn; |
| 240 | + hwtimer3.hwtimer_periph = &_hwtimer_periph3; |
| 241 | + hwtimer3.parent.info = &es32f0_hwtimer_info; |
| 242 | + hwtimer3.parent.ops = &es32f0_hwtimer_ops; |
| 243 | + ret = rt_device_hwtimer_register(&hwtimer3.parent, "timer3", &hwtimer3); |
| 244 | +#endif |
| 245 | + |
| 246 | + return ret; |
| 247 | +} |
| 248 | +INIT_BOARD_EXPORT(rt_hw_hwtimer_init); |
| 249 | + |
| 250 | +#endif |
0 commit comments