diff --git a/basil/HL/agilent_33250a.yaml b/basil/HL/agilent_33250a.yaml index 169c4ff1c..ad7293734 100644 --- a/basil/HL/agilent_33250a.yaml +++ b/basil/HL/agilent_33250a.yaml @@ -177,7 +177,7 @@ set_system_lock: SYSTem:RWLock ###### # PLL commands ###### -set_pll_phase: PHASe #{Angle|MINimum|MAXimum} +set_pll_phase: PHASe #{<:LQNHO>|MINimum|MAXimum} get_pll_phase: PHASe? #[MINimum|MAXimum] set_pll_reference: PHASe:REFerence set_pll_phase_error_state: PHASe:UNLock:ERRor:STATe #{OFF|ON} diff --git a/basil/HL/fadc_rx.py b/basil/HL/fadc_rx.py index 8b24f2889..e5dd1785e 100644 --- a/basil/HL/fadc_rx.py +++ b/basil/HL/fadc_rx.py @@ -22,7 +22,10 @@ class fadc_rx(RegisterHardwareLayer): 'SINGLE_DATA': {'descr': {'addr': 2, 'size': 1, 'offset': 2}}, 'SAMPLE_DLY': {'descr': {'addr': 7, 'size': 8}}, 'COUNT': {'descr': {'addr': 3, 'size': 24}}, - 'COUNT_LOST': {'descr': {'addr': 8, 'size': 8, 'properties': ['ro']}}} + 'COUNT_LOST': {'descr': {'addr': 8, 'size': 8, 'properties': ['ro']}}, + 'CONF_TRIGGER_THRESHOLD' : {'descr':{'addr' : 9, 'size' : 8}}, + 'CONF_SET_TRIGGER_THRESHOLD' : {'descr':{'addr' : 10, 'size' : 16}}, + 'FEEDBACK_THRESHOLD_TRIGGERED' : {'descr':{'addr' : 12, 'size' : 8, 'properties' : ['ro']}}} _require_version = "==1" @@ -79,3 +82,21 @@ def is_ready(self): def get_done(self): return self.is_ready + + def set_threshold_trigger(self, mode): + self.CONF_TRIGGER_THRESHOLD = mode + # MODE 1: Check if value is smaller than threshold + # MODE 2: Check if value exceeds threshold + # MODE 3: Check if value changes more than threshold + + def get_threshold_trigger_mode(self): + return self.CONF_TRIGGER_THRESHOLD + + def set_threshold_trigger_value(self, val): + self.CONF_SET_TRIGGER_THRESHOLD = val + + def get_threshold_trigger_value(self): + return self.CONF_SET_TRIGGER_THRESHOLD + + def get_threshold_trigger_feedback(self): + return self.FEEDBACK_THRESHOLD_TRIGGERED \ No newline at end of file diff --git a/basil/HL/seq_gen.py b/basil/HL/seq_gen.py index 33e6025f8..99a6aebb6 100644 --- a/basil/HL/seq_gen.py +++ b/basil/HL/seq_gen.py @@ -18,15 +18,14 @@ class seq_gen(RegisterHardwareLayer): 'START': {'descr': {'addr': 1, 'size': 8, 'properties': ['writeonly']}}, 'EN_EXT_START': {'descr': {'addr': 2, 'size': 1}}, 'CLK_DIV': {'descr': {'addr': 3, 'size': 8}}, - 'SIZE': {'descr': {'addr': 4, 'size': 32}}, - 'WAIT': {'descr': {'addr': 8, 'size': 32}}, - 'REPEAT': {'descr': {'addr': 12, 'size': 32}}, - 'REPEAT_START': {'descr': {'addr': 16, 'size': 32}}, - 'NESTED_START': {'descr': {'addr': 20, 'size': 32}}, - 'NESTED_STOP': {'descr': {'addr': 24, 'size': 32}}, - 'NESTED_REPEAT': {'descr': {'addr': 28, 'size': 32}}, - 'MEM_BYTES': {'descr': {'addr': 32, 'size': 32, 'properties': ['ro']}}, - } + 'SIZE': {'descr': {'addr': 4, 'size': 16}}, + 'WAIT': {'descr': {'addr': 6, 'size': 16}}, + 'REPEAT': {'descr': {'addr': 8, 'size': 16}}, + 'REPEAT_START': {'descr': {'addr': 10, 'size': 16}}, + 'NESTED_START': {'descr': {'addr': 12, 'size': 16}}, + 'NESTED_STOP': {'descr': {'addr': 14, 'size': 16}}, + 'NESTED_REPEAT': {'descr': {'addr': 16, 'size': 16}}, + 'MEM_BYTES': {'descr': {'addr': 18, 'size': 16, 'properties': ['ro']}},} _require_version = "==3" def __init__(self, intf, conf): diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v index 545122ed7..076a6d5e9 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx.v @@ -32,7 +32,9 @@ module gpac_adc_rx #( input wire BUS_RD, input wire BUS_WR, - output wire LOST_ERROR + output wire LOST_ERROR, + output wire [0:1] status_LED + ); wire IP_RD, IP_WR; @@ -79,7 +81,8 @@ gpac_adc_rx_core #( .FIFO_READ(FIFO_READ), .FIFO_EMPTY(FIFO_EMPTY), .FIFO_DATA(FIFO_DATA), - .LOST_ERROR(LOST_ERROR) + .LOST_ERROR(LOST_ERROR), + .status_LED(status_LED) ); diff --git a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v index 66e690a45..4652237ef 100644 --- a/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v +++ b/basil/firmware/modules/gpac_adc_rx/gpac_adc_rx_core.v @@ -30,7 +30,8 @@ module gpac_adc_rx_core #( input wire BUS_WR, input wire BUS_RD, - output wire LOST_ERROR + output wire LOST_ERROR, + output wire status_LED ); localparam VERSION = 1; @@ -41,6 +42,8 @@ localparam VERSION = 1; //TODO: // - external trigger /rising falling + + wire SOFT_RST; assign SOFT_RST = (BUS_ADD==0 && BUS_WR); @@ -60,6 +63,10 @@ always @(posedge BUS_CLK) begin status_regs[6] <= 1; status_regs[7] <= 0; status_regs[8] <= 0; + status_regs[9] <= 0; + status_regs[10] <= 0; + status_regs[11] <= 0; + status_regs[12] <= 0; end else if(BUS_WR && BUS_ADD < 16) status_regs[BUS_ADD[3:0]] <= BUS_DATA_IN; @@ -74,6 +81,7 @@ assign CONF_START_WITH_SYNC = status_regs[2][0]; wire CONF_EN_EX_TRIGGER; assign CONF_EN_EX_TRIGGER = status_regs[2][1]; + wire CONF_SINGLE_DATA; assign CONF_SINGLE_DATA = status_regs[2][2]; @@ -91,6 +99,14 @@ reg CONF_DONE; wire [7:0] BUS_STATUS_OUT; assign BUS_STATUS_OUT = status_regs[BUS_ADD[3:0]]; + +// Triggering on threshold condition registers +wire [7:0] CONF_TRIGGER_THRESHOLD = status_regs[9]; // Enable threshold triggering +wire [13:0] CONF_SET_TRIGGER_THRESHOLD = {status_regs[11][5:0], status_regs[10]}; // set the value for the threshold (depends on mode) +reg [7:0] FEEDBACK_THRESHOLD_TRIGGERED; // A statusregister that gives basil a feedback, that it found an event +reg [7:0] ADC_THRESHOLD; // The register that will hold the trigger information +reg [13:0] ADC_IN_DLY_BUF; // Stores the most recent buf num + always @(posedge BUS_CLK) begin if(BUS_RD) begin if(BUS_ADD == 0) @@ -99,6 +115,8 @@ always @(posedge BUS_CLK) begin BUS_DATA_OUT <= {7'b0, CONF_DONE}; else if(BUS_ADD == 8) BUS_DATA_OUT <= CONF_ERROR_LOST; +// else if (BUS_ADD == 12) +// BUS_DATA_OUT <= FEEDBACK_THRESHOLD_TRIGGERED; else if(BUS_ADD < 16) BUS_DATA_OUT <= BUS_STATUS_OUT; end @@ -147,7 +165,7 @@ always @(posedge ADC_ENC) begin end wire start_data_count; -assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER); +assign start_data_count = (CONF_START_WITH_SYNC ? (adc_sync_wait && adc_sync_pulse) : start_adc_sync) || ( CONF_EN_EX_TRIGGER && ADC_TRIGGER) || (CONF_TRIGGER_THRESHOLD && ADC_THRESHOLD); reg [23:0] rec_cnt; @@ -202,11 +220,27 @@ always @(posedge ADC_ENC) always @(posedge ADC_ENC) adc_dly_mem <= dly_mem[dly_addr_read]; +reg status_LED_temp; + + + always @(*) begin + ADC_IN_DLY_BUF = ADC_IN_DLY; dly_addr_read = dly_addr_write - CONF_SAMPEL_DLY; ADC_IN_DLY = CONF_SAMPEL_DLY == 0 ? ADC_IN : adc_dly_mem; + if(CONF_TRIGGER_THRESHOLD==1 || CONF_TRIGGER_THRESHOLD==4) begin // MODE 1: Check if value is smaller than threshold + ADC_THRESHOLD = (ADC_IN_DLY < CONF_SET_TRIGGER_THRESHOLD); end + else if(CONF_TRIGGER_THRESHOLD==2) begin // MODE 2: Check if value exceeds threshold + ADC_THRESHOLD = (ADC_IN_DLY > CONF_SET_TRIGGER_THRESHOLD);end + else if(CONF_TRIGGER_THRESHOLD==3) begin// MODE 3: Check if value changes more than threshold + ADC_THRESHOLD = (ADC_IN_DLY_BUF-ADC_IN_DLY > CONF_SET_TRIGGER_THRESHOLD);end + if(ADC_THRESHOLD) begin + FEEDBACK_THRESHOLD_TRIGGERED = FEEDBACK_THRESHOLD_TRIGGERED+1; end end -// + +assign status_LED = status_LED_temp; + + always @(posedge ADC_ENC) begin prev_data <= ADC_IN_DLY; @@ -228,10 +262,15 @@ end reg [31:0] data_to_fifo; always @(*) begin - if(CONF_SINGLE_DATA) - data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY}; - else + if(CONF_SINGLE_DATA) begin + if (!CONF_TRIGGER_THRESHOLD)begin + data_to_fifo = {HEADER_ID, ADC_ID, CONF_EN_EX_TRIGGER ? rec_cnt == 1 : ADC_SYNC, 14'b0, ADC_IN_DLY};end + else begin + data_to_fifo = {HEADER_ID, ADC_ID, CONF_TRIGGER_THRESHOLD ? (rec_cnt == 1) : ADC_SYNC, 14'b0, ADC_IN_DLY};end + end + else begin data_to_fifo = {HEADER_ID, ADC_ID, prev_sync, prev_data, ADC_IN_DLY}; + end if(CONF_SINGLE_DATA) cdc_fifo_write = cdc_fifo_write_single; @@ -239,7 +278,6 @@ always @(*) begin cdc_fifo_write = cdc_fifo_write_double; end - wire [31:0] cdc_data_out; cdc_syncfifo #( .DSIZE(32), diff --git a/basil/firmware/modules/seq_gen/seq_gen.v b/basil/firmware/modules/seq_gen/seq_gen.v index a6a51d353..c33ddc873 100644 --- a/basil/firmware/modules/seq_gen/seq_gen.v +++ b/basil/firmware/modules/seq_gen/seq_gen.v @@ -13,7 +13,7 @@ module seq_gen #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16384, - parameter OUT_BITS = 8 + parameter OUT_BITS = 16 ) ( input wire BUS_CLK, input wire BUS_RST, diff --git a/basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v b/basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v new file mode 100644 index 000000000..b89ded3f1 --- /dev/null +++ b/basil/firmware/modules/seq_gen/seq_gen_blk_mem_16x8196.v @@ -0,0 +1,162 @@ +/** + * ------------------------------------------------------------ + * Copyright (c) All rights reserved + * SiLab, Institute of Physics, University of Bonn + * ------------------------------------------------------------ + */ +`timescale 1ps/1ps +`default_nettype none + +module seq_gen_blk_mem ( + clka, clkb, wea, addra, dina, web, addrb, dinb, douta, doutb +); + +input wire clka; +input wire clkb; +input wire [0 : 0] wea; +input wire [13 : 0] addra; +input wire [7 : 0] dina; +input wire [0 : 0] web; +input wire [12 : 0] addrb; +input wire [15 : 0] dinb; +output wire [7 : 0] douta; +output wire [15 : 0] doutb; + +RAMB16_S1_S2 mem0 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[7]}), + .DIB({dinb[15], dinb[7]}), + .DOA({douta[7]}), + .DOB({doutb[15], doutb[7]}) +); + +RAMB16_S1_S2 mem1 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[6]}), + .DIB({dinb[14], dinb[6]}), + .DOA({douta[6]}), + .DOB({doutb[14], doutb[6]}) +); + +RAMB16_S1_S2 mem2 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[5]}), + .DIB({dinb[13], dinb[5]}), + .DOA({douta[5]}), + .DOB({doutb[13], doutb[5]}) +); + +RAMB16_S1_S2 mem3 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[4]}), + .DIB({dinb[12], dinb[4]}), + .DOA({douta[4]}), + .DOB({doutb[12], doutb[4]}) +); + +RAMB16_S1_S2 mem4 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[3]}), + .DIB({dinb[11], dinb[3]}), + .DOA({douta[3]}), + .DOB({doutb[11], doutb[3]}) +); + +RAMB16_S1_S2 mem5 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[2]}), + .DIB({dinb[10], dinb[2]}), + .DOA({douta[2]}), + .DOB({doutb[10], doutb[2]}) +); + +RAMB16_S1_S2 mem6 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[1]}), + .DIB({dinb[9], dinb[1]}), + .DOA({douta[1]}), + .DOB({doutb[9], doutb[1]}) +); + +RAMB16_S1_S2 mem7 ( + .CLKA(clka), + .CLKB(clkb), + .ENB(1'b1), + .SSRB(1'b0), + .WEA(wea[0]), + .WEB(web[0]), + .ENA(1'b1), + .SSRA(1'b0), + .ADDRA(addra[13:0]), + .ADDRB(addrb[12:0]), + .DIA({dina[0]}), + .DIB({dinb[8], dinb[0]}), + .DOA({douta[0]}), + .DOB({doutb[8], doutb[0]}) +); + +endmodule + diff --git a/basil/firmware/modules/seq_gen/seq_gen_core.v b/basil/firmware/modules/seq_gen/seq_gen_core.v index 3d39836fe..2524cca3a 100644 --- a/basil/firmware/modules/seq_gen/seq_gen_core.v +++ b/basil/firmware/modules/seq_gen/seq_gen_core.v @@ -10,7 +10,7 @@ module seq_gen_core #( parameter ABUSWIDTH = 16, parameter MEM_BYTES = 16384, - parameter OUT_BITS = 8 + parameter OUT_BITS = 16 //4,8,16,32 ) ( BUS_CLK, BUS_RST, @@ -26,7 +26,6 @@ module seq_gen_core #( ); localparam VERSION = 3; -localparam MEM_OFFSET = 64; input wire BUS_CLK; input wire BUS_RST; @@ -39,10 +38,11 @@ output reg [7:0] BUS_DATA_OUT; input wire SEQ_EXT_START; input wire SEQ_CLK; output reg [OUT_BITS-1:0] SEQ_OUT; +`include "../../../git/basil/basil/firmware/modules/includes/log2func.v" +//`include "../includes/log2func.v" -localparam DEF_BIT_OUT = (OUT_BITS > 8) ? (MEM_BYTES/(OUT_BITS/8)) : (MEM_BYTES*(8/OUT_BITS)); -localparam ADDR_SIZEA = $clog2(MEM_BYTES); -localparam ADDR_SIZEB = $clog2(DEF_BIT_OUT); +localparam ADDR_SIZEA = `CLOG2(MEM_BYTES); +localparam ADDR_SIZEB = (OUT_BITS > 8) ? `CLOG2(MEM_BYTES/(OUT_BITS/8)) : `CLOG2(MEM_BYTES*(8/OUT_BITS)); reg [7:0] status_regs [31:0]; @@ -51,54 +51,38 @@ wire SOFT_RST; assign RST = BUS_RST || SOFT_RST; +localparam DEF_BIT_OUT = MEM_BYTES; + always @(posedge BUS_CLK) begin if(RST) begin status_regs[0] <= 0; status_regs[1] <= 0; status_regs[2] <= 0; - status_regs[3] <= 1; // CONF_CLK_DIV - - status_regs[4] <= DEF_BIT_OUT[7:0]; // bits - status_regs[5] <= DEF_BIT_OUT[15:8]; // -||- - status_regs[6] <= DEF_BIT_OUT[23:16]; // -||- - status_regs[7] <= DEF_BIT_OUT[31:24]; // -||- + status_regs[3] <= 1; - status_regs[8] <= 0; // wait - status_regs[9] <= 0; // -||- - status_regs[10] <= 0; // -||- - status_regs[11] <= 0; // -||- + status_regs[4] <= DEF_BIT_OUT[7:0]; //bits + status_regs[5] <= DEF_BIT_OUT[15:8]; //bits - status_regs[12] <= 1; // repeat + status_regs[6] <= 0; //wait + status_regs[7] <= 0; //wait + status_regs[8] <= 0; // 7 repeat + status_regs[9] <= 0; // 7 repeat + status_regs[10] <= 0; //repeat start + status_regs[11] <= 0; //repeat start + status_regs[12] <= 0; // nested loop start status_regs[13] <= 0; // -||- - status_regs[14] <= 0; // -||- + status_regs[14] <= 0; // nested loop stop status_regs[15] <= 0; // -||- - - status_regs[16] <= 0; //repeat start + status_regs[16] <= 0; // nested loop repat count status_regs[17] <= 0; // -||- - status_regs[18] <= 0; // -||- - status_regs[19] <= 0; // -||- - - status_regs[20] <= 0; // nested loop start - status_regs[21] <= 0; // -||- - status_regs[22] <= 0; // -||- - status_regs[23] <= 0; // -||- - - status_regs[24] <= 0; // nested loop stop - status_regs[25] <= 0; // -||- - status_regs[26] <= 0; // -||- - status_regs[27] <= 0; // -||- - - status_regs[28] <= 0; // nested loop repat count - status_regs[29] <= 0; // -||- - status_regs[30] <= 0; // -||- - status_regs[31] <= 0; // -||- end - else if(BUS_WR && BUS_ADD < MEM_OFFSET) + else if(BUS_WR && BUS_ADD < 32) status_regs[BUS_ADD[4:0]] <= BUS_DATA_IN; end -wire [7:0] BUS_IN_MEM; +reg [7:0] BUS_IN_MEM; +reg [7:0] BUS_OUT_MEM; // 1 - finished @@ -113,26 +97,26 @@ wire [7:0] CONF_CLK_DIV; assign CONF_CLK_DIV = status_regs[3] - 1; reg CONF_DONE; -wire [31:0] CONF_COUNT; -assign CONF_COUNT = {status_regs[7], status_regs[6], status_regs[5], status_regs[4]}; +wire [15:0] CONF_COUNT; +assign CONF_COUNT = {status_regs[5], status_regs[4]}; -wire [31:0] CONF_WAIT; -assign CONF_WAIT = {status_regs[11], status_regs[10], status_regs[9], status_regs[8]}; +wire [15:0] CONF_WAIT; +assign CONF_WAIT = {status_regs[7], status_regs[6]}; -wire [31:0] CONF_REPEAT; -assign CONF_REPEAT = {status_regs[15], status_regs[14], status_regs[13], status_regs[12]}; +wire [15:0] CONF_REPEAT; +assign CONF_REPEAT = {status_regs[9], status_regs[8]}; -wire [31:0] CONF_REP_START; -assign CONF_REP_START = {status_regs[19], status_regs[18], status_regs[17], status_regs[16]}; +wire [15:0] CONF_REP_START; +assign CONF_REP_START = {status_regs[11], status_regs[10]}; -wire [31:0] CONF_NESTED_START; -assign CONF_NESTED_START = {status_regs[23], status_regs[22], status_regs[21], status_regs[20]}; +wire [15:0] CONF_NESTED_START; +assign CONF_NESTED_START = {status_regs[13], status_regs[12]}; -wire [31:0] CONF_NESTED_STOP; -assign CONF_NESTED_STOP = {status_regs[27], status_regs[26], status_regs[25], status_regs[24]}; +wire [15:0] CONF_NESTED_STOP; +assign CONF_NESTED_STOP = {status_regs[15], status_regs[14]}; -wire [31:0] CONF_NESTED_REPEAT; -assign CONF_NESTED_REPEAT = {status_regs[31], status_regs[30], status_regs[29], status_regs[28]}; +wire [15:0] CONF_NESTED_REPEAT; +assign CONF_NESTED_REPEAT = {status_regs[17], status_regs[16]}; wire [7:0] BUS_STATUS_OUT; assign BUS_STATUS_OUT = status_regs[BUS_ADD[4:0]]; @@ -144,15 +128,11 @@ always @(posedge BUS_CLK) begin BUS_DATA_OUT_REG <= VERSION; else if(BUS_ADD == 1) BUS_DATA_OUT_REG <= {7'b0, CONF_DONE}; - else if(BUS_ADD == 32) - BUS_DATA_OUT_REG <= MEM_BYTES[7:0]; - else if(BUS_ADD == 33) - BUS_DATA_OUT_REG <= MEM_BYTES[15:8]; - else if(BUS_ADD == 34) - BUS_DATA_OUT_REG <= MEM_BYTES[23:16]; - else if(BUS_ADD == 35) - BUS_DATA_OUT_REG <= MEM_BYTES[31:24]; - else if(BUS_ADD < MEM_OFFSET) + else if(BUS_ADD == 18) + BUS_DATA_OUT_REG <= DEF_BIT_OUT[7:0]; + else if(BUS_ADD == 19) + BUS_DATA_OUT_REG <= DEF_BIT_OUT[15:8]; + else if(BUS_ADD < 32) BUS_DATA_OUT_REG <= BUS_STATUS_OUT; end end @@ -167,15 +147,15 @@ always @(posedge BUS_CLK) begin end always @(*) begin - if(PREV_BUS_ADD < MEM_OFFSET) + if(PREV_BUS_ADD < 32) BUS_DATA_OUT = BUS_DATA_OUT_REG; - else if(PREV_BUS_ADD < MEM_OFFSET + MEM_BYTES ) + else if(PREV_BUS_ADD < 32 + MEM_BYTES ) BUS_DATA_OUT = BUS_IN_MEM; else BUS_DATA_OUT = 8'hxx; end -reg [31:0] out_bit_cnt; +reg [15:0] out_bit_cnt; wire [ADDR_SIZEB-1:0] memout_addrb; //assign memout_addrb = out_bit_cnt-1; @@ -183,27 +163,59 @@ assign memout_addrb = out_bit_cnt < CONF_COUNT ? out_bit_cnt-1 : CONF_COUNT-1; / wire [ADDR_SIZEA-1:0] memout_addra; wire [ABUSWIDTH-1:0] BUS_ADD_MEM; -assign BUS_ADD_MEM = BUS_ADD - MEM_OFFSET; +assign BUS_ADD_MEM = BUS_ADD - 32; -assign memout_addra = BUS_ADD_MEM; +generate + if (OUT_BITS<=8) begin + assign memout_addra = BUS_ADD_MEM; + end else begin + assign memout_addra = {BUS_ADD_MEM[ABUSWIDTH-1:OUT_BITS/8-1], {(OUT_BITS/8-1){1'b0}}} + (OUT_BITS/8-1) - (BUS_ADD_MEM % (OUT_BITS/8)); //Byte order + end +endgenerate -wire [OUT_BITS-1:0] SEQ_OUT_MEM; +reg [OUT_BITS-1:0] SEQ_OUT_MEM; wire WEA; -assign WEA = BUS_WR && BUS_ADD >=MEM_OFFSET && BUS_ADD < MEM_OFFSET+MEM_BYTES; - -ramb_8_to_n #(.SIZE(MEM_BYTES), .WIDTH(OUT_BITS)) mem ( - .clkA(BUS_CLK), - .clkB(SEQ_CLK), - .weA(WEA), - .weB(1'b0), - .addrA(memout_addra), - .addrB(memout_addrb), - .diA(BUS_DATA_IN), - .doA(BUS_IN_MEM), - .diB({OUT_BITS{1'b0}}), - .doB(SEQ_OUT_MEM) -); +assign WEA = BUS_WR && BUS_ADD >=32 && BUS_ADD < 32+MEM_BYTES; + +generate + if (OUT_BITS==8) begin + reg [7:0] mem [(2**ADDR_SIZEA)-1:0]; + + // synthesis translate_off + //to make simulator happy (no X propagation) + integer i; + initial begin + for(i = 0; i<(2**ADDR_SIZEA); i = i + 1) + mem[i] = 0; + end + // synthesis translate_on + + always @(posedge BUS_CLK) begin + if (WEA) + mem[memout_addra] <= BUS_DATA_IN; + BUS_IN_MEM <= mem[memout_addra]; + end + + always @(posedge SEQ_CLK) + SEQ_OUT_MEM <= mem[memout_addrb]; + + end else begin + wire [7:0] douta; + wire [OUT_BITS-1:0] doutb; + seq_gen_blk_mem memout( + .clka(BUS_CLK), .clkb(SEQ_CLK), .douta(douta), .doutb(doutb), + .wea(WEA), .web(1'b0), .addra(memout_addra), .addrb(memout_addrb), + .dina(BUS_DATA_IN), .dinb({OUT_BITS{1'b0}}) + ); + + always @(*) begin + BUS_IN_MEM = douta; + SEQ_OUT_MEM = doutb; + end + end +endgenerate + wire RST_SYNC; wire RST_SOFT_SYNC; @@ -219,13 +231,14 @@ wire START_SYNC_PRE; assign START_SYNC_PRE = (START_SYNC_CDC | (SEQ_EXT_START & CONF_EN_EXT_START)); assign START_SYNC = START_SYNC_PRE & DONE; //no START if previous not finished -wire [31:0] STOP_BIT; +wire [15:0] STOP_BIT; assign STOP_BIT = CONF_COUNT + CONF_WAIT; -reg [31:0] REPEAT_COUNT; -reg [31:0] REPEAT_NESTED_COUNT; +reg [15:0] REPEAT_COUNT; +reg [15:0] REPEAT_NESTED_COUNT; reg [7:0] dev_cnt; + wire REP_START; assign REP_START = (out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV && (CONF_REPEAT==0 || REPEAT_COUNT < CONF_REPEAT)); @@ -273,7 +286,7 @@ always @(posedge SEQ_CLK) DONE <= 1; else if(START_SYNC_PRE) DONE <= 0; - else if(REPEAT_COUNT > CONF_REPEAT & out_bit_cnt == STOP_BIT && dev_cnt == CONF_CLK_DIV) + else if(REPEAT_COUNT > CONF_REPEAT) DONE <= 1; always @(posedge SEQ_CLK) diff --git a/basil/firmware/modules/sram_fifo/sram_fifo_core.v b/basil/firmware/modules/sram_fifo/sram_fifo_core.v index e1d72634c..a6f65a14c 100644 --- a/basil/firmware/modules/sram_fifo/sram_fifo_core.v +++ b/basil/firmware/modules/sram_fifo/sram_fifo_core.v @@ -220,11 +220,18 @@ wire [15:0] DATA_TO_SRAM; assign DATA_TO_SRAM = wr_pointer[0]==0 ? FIFO_DATA_BUF[15:0] : FIFO_DATA_BUF[31:16]; //CG_MOD_neg icg(.ck_in(BUS_CLK270), .enable(write_sram), .ck_out(SRAM_WE_B)); - +/* ODDR WE_INST (.D1(~write_sram), .D2(1'b1), .C(~BUS_CLK), .CE(1'b1), .R(1'b0), .S(1'b0), .Q(SRAM_WE_B) ); - + */ + OFDDRRSE OFDDRRSE_ADC_ENC_BUF ( + .Q(SRAM_WE_B), + .C0(~BUS_CLK), .C1(BUS_CLK), + .CE(1'b1), + .D0(~write_sram), .D1(1'b1), + .R(1'b0), .S(1'b0) + ); assign SRAM_IO = write_sram ? DATA_TO_SRAM : 16'hzzzz; assign SRAM_A = (read_sram) ? rd_pointer : wr_pointer; assign SRAM_BHE_B = 0; diff --git a/basil/firmware/modules/utils/ramb_8_to_n.v b/basil/firmware/modules/utils/ramb_8_to_n.v index 27e75487b..ff5bdf270 100644 --- a/basil/firmware/modules/utils/ramb_8_to_n.v +++ b/basil/firmware/modules/utils/ramb_8_to_n.v @@ -15,17 +15,22 @@ module ramb_8_to_n (clkA, doA, diB, doB); - + + +`include "../../../git/basil/basil/firmware/modules/includes/log2func.v" +//`include "includes/log2func.v" + parameter SIZE = 1024; parameter WIDTH = 8; + localparam WIDTHA = 8; localparam SIZEA = SIZE; -localparam ADDRWIDTHA = $clog2(SIZEA); +localparam ADDRWIDTHA = clog2(SIZEA); localparam WIDTHB = WIDTH; localparam SIZEB = SIZEA*8/WIDTHB; -localparam ADDRWIDTHB = $clog2(SIZEB); +localparam ADDRWIDTHB = clog2(SIZEB); input wire clkA; input wire clkB; @@ -44,7 +49,7 @@ localparam maxSIZE = `max(SIZEA, SIZEB); localparam maxWIDTH = `max(WIDTHA, WIDTHB); localparam minWIDTH = `min(WIDTHA, WIDTHB); localparam RATIO = maxWIDTH / minWIDTH; -localparam log2RATIO = $clog2(RATIO); +localparam log2RATIO = clog2(RATIO); reg [minWIDTH-1:0] RAM [0:maxSIZE-1]; diff --git a/examples/MIO/ise/example.xise b/examples/MIO/ise/example.xise index 57a0decc0..385625a7c 100644 --- a/examples/MIO/ise/example.xise +++ b/examples/MIO/ise/example.xise @@ -17,27 +17,31 @@ - + - - - - - - - - - + - - + + + + + + + + + + + + + + diff --git a/examples/lab_devices/tektronixOscilloscope_pyvisa.yaml b/examples/lab_devices/tektronixOscilloscope_pyvisa.yaml index f31c3f590..5ad5d9b11 100644 --- a/examples/lab_devices/tektronixOscilloscope_pyvisa.yaml +++ b/examples/lab_devices/tektronixOscilloscope_pyvisa.yaml @@ -3,7 +3,7 @@ transfer_layer: - name : Visa type : Visa init : - resource_name : TCPIP::131.220.167.109 + resource_name : TCPIP::10.42.0.48 encoding: 'ascii' backend : "@py" #resource_name : USB0::0x0699::0x0409::C010877::INSTR # (works with NI VISA backend + USB + Windows 7)