Neurons without incoming synapses that are on a path from an input neuron are handled erroneously in hardware

[BGull00]

Neurons without incoming synapses that are on a path from an input neuron are not properly handled in the generated network SystemVerilog file. This causes signals to go to an undetermined state (symbolized by the dreaded X in Vivado's sim). For example, an output neuron with no incoming synapses is declared by logic signed [NET_CHARGE_WIDTH-1:0] neur_95_inp [0:-1]; and neur_95_inp is not assigned anywhere (as there is no input to the neuron). In this case, the neur_95_inp array should be of size 1 (i.e. neur_95_inp[0:0]), and the only array value should be directly connected to logic value 0.

[BGull00]

This also needs fixing inside of the neuron SystemVerilog file as NUM_INP can be equal to 0. This same bug of doing logic [NUM_<something>-1:0] when NUM_<something> could be 0 could exist elsewhere in the code base and lead to more future issues.

[keegandent]

So my understanding is these neurons existing in the network graph only makes sense if we agree that for TENNLab-UTK/framework-open#3, neurons with threshold + !threshold_inclusive <= 0 should spike every run unless they receive inhibitory input.