Networks and Input Spike Rasters for Integration Testing

[keegandent]

Problem

Issues like #30 and TENNLab-UTK/framework-open#3 are likely to continue lurking without some better example networks to verify behavior in simulation and HWIL.

Proposed Solution

Select some FPGA-compatible RISP networks. Provide a set of testing input spike and run calls that exercise as much of the network behavior as possible. There's no need to provide known output rasters, as the test scripts can use the simulator at test-time to validate results.

Hurdles

Many if not most of the simulator networks are floating-point?

Expected API Impacts

None.

[keegandent]

@BGull00, @charizzo, @aweis-9535 could one or two of you please take this?

[aweis-9535]

I can definitely take this; I'll need someone else to help with defining the RISP network.

[keegandent]

I can definitely take this; I'll need someone else to help with defining the RISP network.

@charizzo would that be you?