Make CLR logic synchronous #52
Description
Problem
CLR logic currently abuses the asynchronous reset of registers in the network. This is bad RTL practice, has caused issues with target FPGA portability, and most importantly likely isn't necessary for single clock per timestep functionality if resolved correctly.
Proposed Solution
The neuron, synapse, and network RTL modules should all add a clock-synchronous, positive-assert clr signal. This signal should allow them to process other input from the current cycle but behave as though no data from previous cycles is available. The network_arstn module should be retired.
Hurdles
No major challenges are anticipated, but solution will need rigorous regression testing.
Expected API Impacts
No changes to the software or hardware API should be required.