RMM does not trap some system registers which may cause abnormal behavior in realm

[Yiwei-Zhuang]

For example, RMM does not trap TID2 registers so that realm could directly read clidr_el1. However, at least in normal vm, this register is emulated by hypervisor and is hard-coded by kvmtool or qemu. Wrong value of clidr_el1 may cause guest getting wrong cpu cache information.

Are there any specific reasons that RMM decides only trapping those in sysreg_handlers?

[soby-mathew]

Thanks for reporting this. Indeed RMM should trap and emulate additional ID regs properly. There is some work ongoing related to this here : https://review.trustedfirmware.org/q/topic:%22sm/revlock%22

For the cache operations, I think RMM should trap DC setway instructions by setting HCR_EL2.TSW bit (which needs to be done). RMM makes use of FWB bit to bypass Stage 1 attributes.

The actual values in CLIDR_EL1, CCSIDR_EL1 should be set to some sensible defaults taking into consideration FWB, IDC, DIC settings.

[soby-mathew]

A patch pushed here for review : https://review.trustedfirmware.org/c/TF-RMM/tf-rmm/+/43833