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feat: update project tt_um_silicon_art from dxa4481/tiny
Commit: f6ba2671c44df1ac6487a752b118a1c84ac78726 Workflow: https://github.com/dxa4481/tiny/actions/runs/19954450932
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projects/tt_um_silicon_art/LICENSE

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9. Accepting Warranty or Additional Liability. While redistributing
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{
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"app": "Tiny Tapeout main bbd9aa18",
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"repo": "https://github.com/dxa4481/tiny",
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"commit": "f6ba2671c44df1ac6487a752b118a1c84ac78726",
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"workflow_url": "https://github.com/dxa4481/tiny/actions/runs/19954450932",
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"project_id": 3497,
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"sort_id": 1764832851934
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}
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<!---
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This file is used to generate your project datasheet. Please fill in the information below and delete any unused sections.
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-->
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## How it works
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This is a **Silicon Art** project for TinyTapeout using the **custom GDS** workflow. A **pixel pig** artwork and **canary token text** are directly written as metal polygons on the silicon, visible under a microscope when the chip is fabricated.
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The design includes:
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1. **Custom GDS** with pixel pig + canary token rendered on metal `.drawing` layers
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2. A decorative border frame around the design
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3. All required TinyTapeout pins properly defined on Metal4.pin layer
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4. Power pins (VPWR, VGND) on TopMetal1.pin layer
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5. A minimal Verilog stub that passes inputs through with an XOR pattern
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**Important DRC note:** Art uses `.drawing` layers (datatype 0) which are the only fabricated layers in TinyTapeout's IHP whitelist. All geometry meets DRC requirements:
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- Pixel art: ~7.88 µm pixels (min: 0.20 µm) ✅
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- Text strokes: ~0.19 µm at 3µm font (min: 0.16 µm) ✅
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- Border: 1.0 µm wide (min: 0.16 µm) ✅
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- Density fill: 2µm squares added to reach 35-60% metal coverage ✅
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The design fits in the 202.08 × 154.98 µm tile area (TinyTapeout IHP 1x1 tile). Pin positions are precisely calculated to match the TinyTapeout IHP template DEF file.
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## How to test
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The functional logic is minimal (just for TinyTapeout compatibility):
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1. Apply any 8-bit input pattern to `ui_in[7:0]`
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2. The output `uo_out[7:0]` will be the input XOR'd with 0xAA
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For example:
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- Input: 0x00 → Output: 0xAA
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- Input: 0xFF → Output: 0x55
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- Input: 0xAA → Output: 0x00
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## External hardware
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No external hardware required. This is primarily an art project.
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**To view the silicon art after fabrication:**
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- Use an optical microscope with at least 50-100x magnification
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- A metallurgical/reflected light microscope works best
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- Look for the pixel pig (left) and canary token text (right)
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- Art is on Metal1.drawing (8/0), Metal2.drawing (10/0), Metal3.drawing (30/0)
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- The patterns appear as bright/reflective metal under the microscope
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- The pig uses 81 pixels (~7.88 µm each), text uses 3µm font
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# Tiny Tapeout Silicon Art Project
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project:
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title: "Silicon Art - Pixel Pig + Canary Token"
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author: "Claude"
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discord: ""
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description: "Pixel pig + canary token art on silicon - visible under microscope"
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language: "Custom GDS"
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clock_hz: 0 # Not a clocked design
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# Tile size - use larger tiles for more text
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tiles: "1x1" # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2
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# Top module name - must start with "tt_um_"
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top_module: "tt_um_silicon_art"
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# Source files
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source_files:
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- project.v
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# Pinout (minimal - art project doesn't need complex I/O)
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pinout:
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# Inputs
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ui[0]: "in0"
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ui[1]: "in1"
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ui[2]: "in2"
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ui[3]: "in3"
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ui[4]: "in4"
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ui[5]: "in5"
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ui[6]: "in6"
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ui[7]: "in7"
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# Outputs (XOR pattern of inputs)
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uo[0]: "out0"
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uo[1]: "out1"
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uo[2]: "out2"
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uo[3]: "out3"
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uo[4]: "out4"
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uo[5]: "out5"
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uo[6]: "out6"
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uo[7]: "out7"
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# Bidirectional pins (unused)
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uio[0]: ""
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uio[1]: ""
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uio[2]: ""
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uio[3]: ""
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uio[4]: ""
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uio[5]: ""
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uio[6]: ""
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uio[7]: ""
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# Do not change!
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yaml_version: 6
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{
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"FLOW_NAME": "LibreLane",
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"FLOW_VERSION": "3.0.0.dev44",
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"PDK": "ihp-sg13g2",
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"PDK_SOURCE": "IHP-Open-PDK",
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"PDK_VERSION": "cb7daaa8901016cf7c5d272dfa322c41f024931f"
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}

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