Dear author:
As a intern digital designer, I am familiar with verilog HDL. However, I am not good at python. I tried to write a python script to do OutputToVerilog, but end up in failure.
Would you be so kind enough to upload a verilog vision for me to learn about?
Your sincerely
Vincent
Dear author:
As a intern digital designer, I am familiar with verilog HDL. However, I am not good at python. I tried to write a python script to do OutputToVerilog, but end up in failure.
Would you be so kind enough to upload a verilog vision for me to learn about?
Your sincerely
Vincent