I've used PyRtL's OutputToVerilog version, but the output is not readable:
how can i fix it?
I wrote these lines in tpu.py to convert it into verilog:
I added first three lines because if i didn't add it, it will output an error and can't change into verilog.
I've used PyRtL's OutputToVerilog version, but the output is not readable:
how can i fix it?
I wrote these lines in tpu.py to convert it into verilog:
I added first three lines because if i didn't add it, it will output an error and can't change into verilog.