Hello, thank you for the great paper and open-source code repo.
I can see that your work uses a Xilinx ZCU106 FPGA, an MPSoC with embedded PS.
I wonder if the project can be run on an Xilinx FPGA accelerator card, such as U55c.
This would require the PS part of your work to be done on Host CPU, with it communicating with PL over PCIe.