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1 parent 65c1f0d commit 77d7cbeCopy full SHA for 77d7cbe
vhdl_lang/src/analysis/association.rs
@@ -293,7 +293,7 @@ impl<'a> AnalyzeContext<'a> {
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let mut not_associated = Vec::new();
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for (idx, formal) in formal_region.iter().enumerate() {
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- if !(associated_indexes.contains(&idx)
+ if !(associated_indexes.contains(&idx)
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// Default may be unconnected
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|| formal.has_default()
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// Output ports are allowed to be unconnected
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