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Description
It seems that critical signals relative to the vector unit are hardcoded to zero.
Some examples:
- The
VSbits inmstatus
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/cp0/rtl/aq_cp0_trap_csr.v#L505 - Decoder signals
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L1011
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L934
https://github.com/T-head-Semi/openc906/blob/main/C906_RTL_FACTORY/gen_rtl/idu/rtl/aq_idu_id_decd.v#L3740
I tried to run some vector code, but it always triggers exceptions on the vector instructions (if I fix some of the hardcoded values, the exception is generated by some other disabled signals). This makes me think that the code was generated with incorrect settings, or that this version of the processor simply does not support the V extension. Can this be the case? If yes, are there any plans to open-source it?
Thanks a lot,
Matteo
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