diff --git a/boards/AlphaData/admpa100_2ms/1.0/LICENSE b/boards/AlphaData/admpa100_2ms/1.0/LICENSE
new file mode 100644
index 000000000..1097dfe3d
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Xilinx Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/AlphaData/admpa100_2ms/1.0/admpa100_image.jpg b/boards/AlphaData/admpa100_2ms/1.0/admpa100_image.jpg
new file mode 100644
index 000000000..0d317e46f
Binary files /dev/null and b/boards/AlphaData/admpa100_2ms/1.0/admpa100_image.jpg differ
diff --git a/boards/AlphaData/admpa100_2ms/1.0/board.xml b/boards/AlphaData/admpa100_2ms/1.0/board.xml
new file mode 100644
index 000000000..99e612288
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.0/board.xml
@@ -0,0 +1,2375 @@
+
+
+
+
+
+
+
+ ADM-PA100 PCI Express Reconfigurable Computing Card"
+
+
+
+
+
+ 1
+
+
+ 1.0
+
+ ADM-PA100/2MS PCI Express Reconfigurable Computing Card
+
+
+
+
+
+
+
+
+
+
+ The XCVC1902 ACAP.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 interface
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 interface (non-interleaved)
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 interface (interleaved)
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 0 controller system clock.
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 1 controller system clock.
+
+
+
+
+
+
+ Programmable oscillator (factory default 300 MHz) that can be used to clock PL.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_200.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_201.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_202.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_203.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_204.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_205.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK1_206.
+
+
+
+
+
+
+ Programmable oscillator (factory default 350 MHz) to GTY_REFCLK0_206.
+
+
+
+
+
+
+ Output clock 0 from SI5328 jitter attenuator to GTY_REFCLK1_201. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Output clock 1 from SI5328 jitter attenuator to GTY_REFCLK1_204. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Reference clock (CLKIN1) to SI5328. NOTE: Not fixed frequency - actual frequency determined by designer.
+
+
+
+
+ Site for an FPGA Mezzanine Card Plus (FMC+/HSPC).
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ User-defined LEDs: [1:0] = { user_led_g1_l, user_led_g0_l }.
+
+
+
+ User-defined switches: [1:0] = { usr_sw_1, usr_sw_0 }.
+
+
+
+ Board status signals: [3:0] = { hspc_prsnt_l, fmc_prsnt_l, srvc_md_l, fan_fail_l }.
+
+
+
+ Interface (I2C) to user-definable EEPROM.
+
+
+
+ Management interface (I2C) of FireFly connector.
+
+
+
+ Sideband input signals of FireFly connector: [1:0] = { firefly_int_l, firefly_modprs_l }.
+
+
+
+ Sideband output signals of FireFly connector: [0] = { firefly_rst_l }.
+
+
+
+ Management interface (I2C) of SI5328 jitter attenuator.
+
+
+
+ Sideband input signals of SI5328 jitter attenuator: [2:0] = { si5328_lol, si5328_c2b, si5328_int_c1b }.
+
+
+
+ Sideband output signals of SI5328 jitter attenuator: [0] = { si5328_rst_l }.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/AlphaData/admpa100_2ms/1.0/changelog.txt b/boards/AlphaData/admpa100_2ms/1.0/changelog.txt
new file mode 100644
index 000000000..237f8e679
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### ADM-PA100/2MS change log ##############
+
+1.0 - Vivado 2022.x
+ADM-PA100 Initial board support
diff --git a/boards/AlphaData/admpa100_2ms/1.0/part0_pins.xml b/boards/AlphaData/admpa100_2ms/1.0/part0_pins.xml
new file mode 100644
index 000000000..030fa4c54
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.0/part0_pins.xml
@@ -0,0 +1,924 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/AlphaData/admpa100_2ms/1.0/preset.xml b/boards/AlphaData/admpa100_2ms/1.0/preset.xml
new file mode 100644
index 000000000..447270b68
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.0/preset.xml
@@ -0,0 +1,365 @@
+
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diff --git a/boards/AlphaData/admpa100_2ms/1.0/xitem.json b/boards/AlphaData/admpa100_2ms/1.0/xitem.json
new file mode 100644
index 000000000..c0e174329
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "admpa100_2ms",
+ "display": "ADM-PA100/2MS",
+ "revision": "1.0",
+ "description": "ADM-PA100/2MS PCI Express Reconfigurable Computing Card",
+ "company": "alpha-data.com",
+ "company_display": "Alpha Data",
+ "author": "adps",
+ "contributors": [
+ {
+ "group": "Alpha Data",
+ "url": "www.alpha-data.com"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://www.alpha-data.com/product/adm-pa100/",
+ "logo": "admpa100_image.jpg",
+ "search-keywords": [
+ "admpa100_2ms",
+ "alpha-data.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/AlphaData/admpa100_2ms/1.2/LICENSE b/boards/AlphaData/admpa100_2ms/1.2/LICENSE
new file mode 100644
index 000000000..1097dfe3d
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Xilinx Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/AlphaData/admpa100_2ms/1.2/admpa100_image.jpg b/boards/AlphaData/admpa100_2ms/1.2/admpa100_image.jpg
new file mode 100644
index 000000000..0d317e46f
Binary files /dev/null and b/boards/AlphaData/admpa100_2ms/1.2/admpa100_image.jpg differ
diff --git a/boards/AlphaData/admpa100_2ms/1.2/board.xml b/boards/AlphaData/admpa100_2ms/1.2/board.xml
new file mode 100644
index 000000000..6e7aa4382
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.2/board.xml
@@ -0,0 +1,2643 @@
+
+
+
+
+
+
+
+ ADM-PA100 PCI Express Reconfigurable Computing Card"
+
+
+
+
+
+ 1
+
+
+ 1.2
+
+ ADM-PA100/2MS PCI Express Reconfigurable Computing Card
+
+
+
+
+
+
+
+
+
+
+ The XCVC1902 ACAP.
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 interface
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
+
+
+ DDR4 SDRAM bank 1 interface
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+ DDR4 SDRAM bank 1 interface (non-interleaved)
+
+
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+ DDR4 SDRAM bank 1 interface (interleaved)
+
+
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+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 0 controller system clock.
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 1 controller system clock.
+
+
+
+
+
+
+ Programmable oscillator (factory default 300 MHz) that can be used to clock PL.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_200.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_201.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_202.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_203.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_204.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_205.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK1_206.
+
+
+
+
+
+
+ Programmable oscillator (factory default 350 MHz) to GTY_REFCLK0_206.
+
+
+
+
+
+
+ Output clock 0 from SI5328 jitter attenuator to GTY_REFCLK1_201. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Output clock 1 from SI5328 jitter attenuator to GTY_REFCLK1_204. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Reference clock (CLKIN1) to SI5328. NOTE: Not fixed frequency - actual frequency determined by designer.
+
+
+
+
+
+ Reference clock (CLKIN2) to SI5328. NOTE: Not fixed frequency - actual frequency determined by designer. CONNECTED TO ACAP ONLY IN BOARD REVISION 4 AND LATER.
+
+
+
+
+ Site for an FPGA Mezzanine Card Plus (FMC+/HSPC).
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ User-defined LEDs: [1:0] = { user_led_g1_l, user_led_g0_l }.
+
+
+
+ User-defined switches: [1:0] = { usr_sw_1, usr_sw_0 }.
+
+
+
+ Board status signals: [3:0] = { hspc_prsnt_l, fmc_prsnt_l, srvc_md_l, fan_fail_l }.
+
+
+
+ Interface (I2C) to user-definable EEPROM.
+
+
+
+ Management interface (I2C) of FireFly connector.
+
+
+
+ Sideband input signals of FireFly connector: [1:0] = { firefly_int_l, firefly_modprs_l }.
+
+
+
+ Sideband output signals of FireFly connector: [0] = { firefly_rst_l }.
+
+
+
+ Management interface (I2C) of SI5328 jitter attenuator.
+
+
+
+ Sideband input signals of SI5328 jitter attenuator: [2:0] = { si5328_lol, si5328_c2b, si5328_int_c1b }.
+
+
+
+ Sideband output signals of SI5328 jitter attenuator: [0] = { si5328_rst_l }.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
diff --git a/boards/AlphaData/admpa100_2ms/1.2/changelog.txt b/boards/AlphaData/admpa100_2ms/1.2/changelog.txt
new file mode 100644
index 000000000..80b86991b
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.2/changelog.txt
@@ -0,0 +1,14 @@
+######### ADM-PA100/2MS change log ##############
+
+1.0 - Vivado 2022.x
+ADM-PA100 Initial board support
+
+1.1
+Changed CIPS IP block automation preset to only configure peripherals, PS reference clock & MIO I/O standards.
+Added CIPS IP presets for (a) Linux-capable configuration and (b) minimal configuration for booting the ACAP without peripherals.
+
+1.2
+Improved the way DDR4 SDRAM bank 1 interface is defined so that flipped pinout is correctly set regardless of single controller vs. 2 interleaved controllers choice. New designs should use "ddr4_bank1" interface in all cases but "ddr4_bank1_ilv" and "ddr4_bank1_non_ilv" interfaces are retained for backwards compatibility with older designs.
+SLEW for unidirectional DDR4 SDRAM pins is now MEDIUM (as opposed to FAST), to resolve SI issues caused by faster edge rate in newer Versal ACAPs.
+Added si5328_refclk_in2 component, interface & pins for rev. 4 board and later.
+No longer sets DM/DBI-related properties to force use of DBI for DDR4 SDRAM controllers; user can now decide whether or not to use DBI for reads and/or writes.
diff --git a/boards/AlphaData/admpa100_2ms/1.2/part0_pins.xml b/boards/AlphaData/admpa100_2ms/1.2/part0_pins.xml
new file mode 100644
index 000000000..20017becc
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.2/part0_pins.xml
@@ -0,0 +1,924 @@
+
+
+
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diff --git a/boards/AlphaData/admpa100_2ms/1.2/preset.xml b/boards/AlphaData/admpa100_2ms/1.2/preset.xml
new file mode 100644
index 000000000..45a6ba74d
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.2/preset.xml
@@ -0,0 +1,450 @@
+
+
+
+
+
+
+
+
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+
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+
diff --git a/boards/AlphaData/admpa100_2ms/1.2/xitem.json b/boards/AlphaData/admpa100_2ms/1.2/xitem.json
new file mode 100644
index 000000000..f8bc1ff98
--- /dev/null
+++ b/boards/AlphaData/admpa100_2ms/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "admpa100_2ms",
+ "display": "ADM-PA100/2MS",
+ "revision": "1.2",
+ "description": "ADM-PA100/2MS PCI Express Reconfigurable Computing Card",
+ "company": "alpha-data.com",
+ "company_display": "Alpha Data",
+ "author": "adps",
+ "contributors": [
+ {
+ "group": "Alpha Data",
+ "url": "www.alpha-data.com"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://www.alpha-data.com/product/adm-pa100/",
+ "logo": "admpa100_image.jpg",
+ "search-keywords": [
+ "admpa100_2ms",
+ "alpha-data.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/AlphaData/admpa101_2ms/1.1/LICENSE b/boards/AlphaData/admpa101_2ms/1.1/LICENSE
new file mode 100644
index 000000000..1097dfe3d
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Xilinx Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/AlphaData/admpa101_2ms/1.1/admpa101_image.jpg b/boards/AlphaData/admpa101_2ms/1.1/admpa101_image.jpg
new file mode 100644
index 000000000..6bb792558
Binary files /dev/null and b/boards/AlphaData/admpa101_2ms/1.1/admpa101_image.jpg differ
diff --git a/boards/AlphaData/admpa101_2ms/1.1/board.xml b/boards/AlphaData/admpa101_2ms/1.1/board.xml
new file mode 100644
index 000000000..4cb27b374
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.1/board.xml
@@ -0,0 +1,2399 @@
+
+
+
+
+
+
+
+ ADM-PA101 PCI Express Reconfigurable Computing Card"
+
+
+
+
+
+ 1
+
+
+ 1.1
+
+ ADM-PA101/2MS PCI Express Reconfigurable Computing Card
+
+
+
+
+
+
+
+
+
+
+ The XCVM1802 ACAP.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
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+
+
+
+
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+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 interface (non-interleaved)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 interface (interleaved)
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
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+
+
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+
+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
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+
+
+
+
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+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
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+
+
+
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+
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+
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+
+
+
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+
+
+
+
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+
+
+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 0 controller system clock.
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 1 controller system clock.
+
+
+
+
+
+
+ Programmable oscillator (factory default 300 MHz) that can be used to clock PL.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_200.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_201.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_202.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_203.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_204.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_205.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK1_206.
+
+
+
+
+
+
+ Programmable oscillator (factory default 350 MHz) to GTY_REFCLK0_206.
+
+
+
+
+
+
+ Output clock 0 from SI5328 jitter attenuator to GTY_REFCLK1_201. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Output clock 1 from SI5328 jitter attenuator to GTY_REFCLK1_204. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Reference clock (CLKIN1) to SI5328. NOTE: Not fixed frequency - actual frequency determined by designer.
+
+
+
+
+ Site for an FPGA Mezzanine Card Plus (FMC+/HSPC).
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ User-defined LEDs: [1:0] = { user_led_g1_l, user_led_g0_l }.
+
+
+
+ User-defined switches: [1:0] = { usr_sw_1, usr_sw_0 }.
+
+
+
+ Board status signals: [3:0] = { hspc_prsnt_l, fmc_prsnt_l, srvc_md_l, fan_fail_l }.
+
+
+
+ Interface (I2C) to user-definable EEPROM.
+
+
+
+ Management interface (I2C) of FireFly connector.
+
+
+
+ Sideband input signals of FireFly connector: [1:0] = { firefly_int_l, firefly_modprs_l }.
+
+
+
+ Sideband output signals of FireFly connector: [0] = { firefly_rst_l }.
+
+
+
+ Management interface (I2C) of SI5328 jitter attenuator.
+
+
+
+ Sideband input signals of SI5328 jitter attenuator: [2:0] = { si5328_lol, si5328_c2b, si5328_int_c1b }.
+
+
+
+ Sideband output signals of SI5328 jitter attenuator: [0] = { si5328_rst_l }.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/boards/AlphaData/admpa101_2ms/1.1/changelog.txt b/boards/AlphaData/admpa101_2ms/1.1/changelog.txt
new file mode 100644
index 000000000..06c1d3fcd
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.1/changelog.txt
@@ -0,0 +1,8 @@
+######### ADM-PA101/2MS change log ##############
+
+1.0 - Vivado 2022.x
+ADM-PA101 Initial board support
+
+1.1
+Changed CIPS IP block automation preset to only configure peripherals, PS reference clock & MIO I/O standards.
+Added CIPS IP presets for (a) Linux-capable configuration and (b) minimal configuration for booting the ACAP without peripherals.
diff --git a/boards/AlphaData/admpa101_2ms/1.1/part0_pins.xml b/boards/AlphaData/admpa101_2ms/1.1/part0_pins.xml
new file mode 100644
index 000000000..eb086d6eb
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.1/part0_pins.xml
@@ -0,0 +1,924 @@
+
+
+
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+
+
+
+
diff --git a/boards/AlphaData/admpa101_2ms/1.1/preset.xml b/boards/AlphaData/admpa101_2ms/1.1/preset.xml
new file mode 100644
index 000000000..e81b0043b
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.1/preset.xml
@@ -0,0 +1,381 @@
+
+
+
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+
+
diff --git a/boards/AlphaData/admpa101_2ms/1.1/xitem.json b/boards/AlphaData/admpa101_2ms/1.1/xitem.json
new file mode 100644
index 000000000..88ed77cf4
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.1/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "admpa101_2ms",
+ "display": "ADM-PA101/2MS",
+ "revision": "1.1",
+ "description": "ADM-PA101/2MS PCI Express Reconfigurable Computing Card",
+ "company": "alpha-data.com",
+ "company_display": "Alpha Data",
+ "author": "adps",
+ "contributors": [
+ {
+ "group": "Alpha Data",
+ "url": "www.alpha-data.com"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://www.alpha-data.com/product/adm-pa101/",
+ "logo": "admpa101_image.jpg",
+ "search-keywords": [
+ "admpa101_2ms",
+ "alpha-data.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/AlphaData/admpa101_2ms/1.2/LICENSE b/boards/AlphaData/admpa101_2ms/1.2/LICENSE
new file mode 100644
index 000000000..1097dfe3d
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Xilinx Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/AlphaData/admpa101_2ms/1.2/admpa101_image.jpg b/boards/AlphaData/admpa101_2ms/1.2/admpa101_image.jpg
new file mode 100644
index 000000000..6bb792558
Binary files /dev/null and b/boards/AlphaData/admpa101_2ms/1.2/admpa101_image.jpg differ
diff --git a/boards/AlphaData/admpa101_2ms/1.2/board.xml b/boards/AlphaData/admpa101_2ms/1.2/board.xml
new file mode 100644
index 000000000..f0a63877c
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.2/board.xml
@@ -0,0 +1,2643 @@
+
+
+
+
+
+
+
+ ADM-PA101 PCI Express Reconfigurable Computing Card"
+
+
+
+
+
+ 1
+
+
+ 1.2
+
+ ADM-PA101/2MS PCI Express Reconfigurable Computing Card
+
+
+
+
+
+
+
+
+
+
+ The XCVM1802 ACAP.
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
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+
+
+
+
+
+
+ DDR4 SDRAM bank 0 interface
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+ DDR4 SDRAM bank 1 interface
+
+
+
+
+
+
+
+
+
+
+
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+ DDR4 SDRAM bank 1 interface (non-interleaved)
+
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+ DDR4 SDRAM bank 1 interface (interleaved)
+
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+
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+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 (8 GB) @ DDR4-3200AA, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 0 controller system clock.
+
+
+
+
+
+
+ 300 MHz oscillator used as DDR4 SDRAM bank 1 controller system clock.
+
+
+
+
+
+
+ Programmable oscillator (factory default 300 MHz) that can be used to clock PL.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_200.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_201.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_202.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_203.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_204.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK0_205.
+
+
+
+
+
+
+ Programmable oscillator (factory default 156.25 MHz) to GTY_REFCLK1_206.
+
+
+
+
+
+
+ Programmable oscillator (factory default 350 MHz) to GTY_REFCLK0_206.
+
+
+
+
+
+
+ Output clock 0 from SI5328 jitter attenuator to GTY_REFCLK1_201. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Output clock 1 from SI5328 jitter attenuator to GTY_REFCLK1_204. NOTE: Not fixed frequency - actual frequency determined by SI5328 register map.
+
+
+
+
+ Reference clock (CLKIN1) to SI5328. NOTE: Not fixed frequency - actual frequency determined by designer.
+
+
+
+
+
+ Reference clock (CLKIN2) to SI5328. NOTE: Not fixed frequency - actual frequency determined by designer. CONNECTED TO ACAP ONLY IN BOARD REVISION 4 AND LATER.
+
+
+
+
+ Site for an FPGA Mezzanine Card Plus (FMC+/HSPC).
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ User-defined LEDs: [1:0] = { user_led_g1_l, user_led_g0_l }.
+
+
+
+ User-defined switches: [1:0] = { usr_sw_1, usr_sw_0 }.
+
+
+
+ Board status signals: [3:0] = { hspc_prsnt_l, fmc_prsnt_l, srvc_md_l, fan_fail_l }.
+
+
+
+ Interface (I2C) to user-definable EEPROM.
+
+
+
+ Management interface (I2C) of FireFly connector.
+
+
+
+ Sideband input signals of FireFly connector: [1:0] = { firefly_int_l, firefly_modprs_l }.
+
+
+
+ Sideband output signals of FireFly connector: [0] = { firefly_rst_l }.
+
+
+
+ Management interface (I2C) of SI5328 jitter attenuator.
+
+
+
+ Sideband input signals of SI5328 jitter attenuator: [2:0] = { si5328_lol, si5328_c2b, si5328_int_c1b }.
+
+
+
+ Sideband output signals of SI5328 jitter attenuator: [0] = { si5328_rst_l }.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
diff --git a/boards/AlphaData/admpa101_2ms/1.2/changelog.txt b/boards/AlphaData/admpa101_2ms/1.2/changelog.txt
new file mode 100644
index 000000000..d66b44987
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.2/changelog.txt
@@ -0,0 +1,14 @@
+######### ADM-PA101/2MS change log ##############
+
+1.0 - Vivado 2022.x
+ADM-PA101 Initial board support
+
+1.1
+Changed CIPS IP block automation preset to only configure peripherals, PS reference clock & MIO I/O standards.
+Added CIPS IP presets for (a) Linux-capable configuration and (b) minimal configuration for booting the ACAP without peripherals.
+
+1.2
+Improved the way DDR4 SDRAM bank 1 interface is defined so that flipped pinout is correctly set regardless of single controller vs. 2 interleaved controllers choice. New designs should use "ddr4_bank1" interface in all cases but "ddr4_bank1_ilv" and "ddr4_bank1_non_ilv" interfaces are retained for backwards compatibility with older designs.
+SLEW for unidirectional DDR4 SDRAM pins is now MEDIUM (as opposed to FAST), to resolve SI issues caused by faster edge rate in newer Versal ACAPs.
+Added si5328_refclk_in2 component, interface & pins for rev. 4 board and later.
+No longer sets DM/DBI-related properties to force use of DBI for DDR4 SDRAM controllers; user can now decide whether or not to use DBI for reads and/or writes.
diff --git a/boards/AlphaData/admpa101_2ms/1.2/part0_pins.xml b/boards/AlphaData/admpa101_2ms/1.2/part0_pins.xml
new file mode 100644
index 000000000..cd0c3fb68
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.2/part0_pins.xml
@@ -0,0 +1,924 @@
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
diff --git a/boards/AlphaData/admpa101_2ms/1.2/preset.xml b/boards/AlphaData/admpa101_2ms/1.2/preset.xml
new file mode 100644
index 000000000..45a6ba74d
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.2/preset.xml
@@ -0,0 +1,450 @@
+
+
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+
diff --git a/boards/AlphaData/admpa101_2ms/1.2/xitem.json b/boards/AlphaData/admpa101_2ms/1.2/xitem.json
new file mode 100644
index 000000000..2e8a8b1de
--- /dev/null
+++ b/boards/AlphaData/admpa101_2ms/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "admpa101_2ms",
+ "display": "ADM-PA101/2MS",
+ "revision": "1.2",
+ "description": "ADM-PA101/2MS PCI Express Reconfigurable Computing Card",
+ "company": "alpha-data.com",
+ "company_display": "Alpha Data",
+ "author": "adps",
+ "contributors": [
+ {
+ "group": "Alpha Data",
+ "url": "www.alpha-data.com"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://www.alpha-data.com/product/adm-pa101/",
+ "logo": "admpa101_image.jpg",
+ "search-keywords": [
+ "admpa101_2ms",
+ "alpha-data.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/AlphaData/admva600_dev/1.0/LICENSE b/boards/AlphaData/admva600_dev/1.0/LICENSE
new file mode 100644
index 000000000..1097dfe3d
--- /dev/null
+++ b/boards/AlphaData/admva600_dev/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Xilinx Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/AlphaData/admva600_dev/1.0/admva600_image.jpg b/boards/AlphaData/admva600_dev/1.0/admva600_image.jpg
new file mode 100644
index 000000000..7e94188da
Binary files /dev/null and b/boards/AlphaData/admva600_dev/1.0/admva600_image.jpg differ
diff --git a/boards/AlphaData/admva600_dev/1.0/board.xml b/boards/AlphaData/admva600_dev/1.0/board.xml
new file mode 100644
index 000000000..cf4676c2b
--- /dev/null
+++ b/boards/AlphaData/admva600_dev/1.0/board.xml
@@ -0,0 +1,1507 @@
+
+
+
+
+
+
+
+ ADM-VA600 VPX Reconfigurable Computing Card"
+
+
+
+
+
+ 1
+
+
+ 1.0
+
+ ADM-VA600/DEV VPX Reconfigurable Computing Card
+
+
+
+
+
+
+
+
+
+
+ The XCVC1902 ACAP.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 0 (8 GB) @ DDR4-2400T, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 SDRAM bank 1 (8 GB) @ DDR4-2400T, 72 bits wide.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 266.67 MHz oscillator used as DDR4 SDRAM bank 0 controller system clock.
+
+
+
+
+
+
+ 266.67 MHz oscillator used as DDR4 SDRAM bank 1 controller system clock.
+
+
+
+
+
+
+ Programmable oscillator (factory default 300 MHz) that can be used to clock PL.
+
+
+
+
+
+
+ 100 MHz PCIe reference clock for GTY Quad 103.
+
+
+
+
+
+
+ 100 MHz PCIe reference clock for GTY Quad 104.
+
+
+
+
+
+
+ 100 MHz PCIe reference clock for GTY Quad 105.
+
+
+
+
+
+
+ 100 MHz PCIe reference clock for GTY Quad 106.
+
+
+
+
+
+
+ Programmable clock to PL, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_103, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_104, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_105, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_106, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_206, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_200, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_201, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK0_202, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK0_203, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK1_204, factory default 200 MHz.
+
+
+
+
+
+
+ Programmable GTY reference clock to GTY_REFCLK0_205, factory default 200 MHz.
+
+
+
+
+
+
+ User-defined LEDs: [1:0] = { user_led_g_l1, user_led_g_l0 }.
+
+
+
+ User-defined switches: [3:0] = { sw_usr3, sw_usr2, sw_usr1, sw_usr0 }.
+
+
+
+ VPX System Management I2C/SMBus bus.
+
+
+
+ I2C temperature sensor connected to PL.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
diff --git a/boards/AlphaData/admva600_dev/1.0/changelog.txt b/boards/AlphaData/admva600_dev/1.0/changelog.txt
new file mode 100644
index 000000000..8c1cf8b43
--- /dev/null
+++ b/boards/AlphaData/admva600_dev/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### ADM-VA600/DEV change log ##############
+
+1.0 - Vivado 2022.x
+ADM-VA600/DEV Initial board support
diff --git a/boards/AlphaData/admva600_dev/1.0/part0_pins.xml b/boards/AlphaData/admva600_dev/1.0/part0_pins.xml
new file mode 100644
index 000000000..fb586e8bd
--- /dev/null
+++ b/boards/AlphaData/admva600_dev/1.0/part0_pins.xml
@@ -0,0 +1,1058 @@
+
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+
diff --git a/boards/AlphaData/admva600_dev/1.0/preset.xml b/boards/AlphaData/admva600_dev/1.0/preset.xml
new file mode 100644
index 000000000..ac18ac481
--- /dev/null
+++ b/boards/AlphaData/admva600_dev/1.0/preset.xml
@@ -0,0 +1,329 @@
+
+
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+
diff --git a/boards/AlphaData/admva600_dev/1.0/xitem.json b/boards/AlphaData/admva600_dev/1.0/xitem.json
new file mode 100644
index 000000000..91e05843d
--- /dev/null
+++ b/boards/AlphaData/admva600_dev/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "admva600_dev",
+ "display": "ADM-VA600/DEV",
+ "revision": "1.0",
+ "description": "ADM-VA600/DEV VPX Reconfigurable Computing Card",
+ "company": "alpha-data.com",
+ "company_display": "Alpha Data",
+ "author": "adps",
+ "contributors": [
+ {
+ "group": "Alpha Data",
+ "url": "www.alpha-data.com"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://www.alpha-data.com/product/adm-va600/",
+ "logo": "admva600_image.jpg",
+ "search-keywords": [
+ "admva600_dev",
+ "alpha-data.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/OpalKelly/BRK1900-7CG/2.0/BRK1900-Top.png b/boards/OpalKelly/BRK1900-7CG/2.0/BRK1900-Top.png
new file mode 100644
index 000000000..f0386fb09
Binary files /dev/null and b/boards/OpalKelly/BRK1900-7CG/2.0/BRK1900-Top.png differ
diff --git a/boards/OpalKelly/BRK1900-7CG/2.0/board.xml b/boards/OpalKelly/BRK1900-7CG/2.0/board.xml
new file mode 100644
index 000000000..7add32240
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7CG/2.0/board.xml
@@ -0,0 +1,1071 @@
+
+
+
+
+ BRK1900 Board File Image
+
+
+
+ 2.0
+
+ 2.0
+ ECM1900-7CG W/ BRK1900
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+ 1-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+ 4-lane GT interface over QSFP1
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 100 MHz default. Clock output 3 on Si5341B. See BRK1900 documentation for more information on the programmable clock generator.
+
+
+
+
+
+ 100 MHz default. Clock output 4 on Si5341B. See BRK1900 documentation for more information on the programmable clock generator.
+
+
+
+
+
+ 4 GiB DDR4 Memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ QSFP1 Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+ QSFP2 Connector
+
+
+
+
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+
+
diff --git a/boards/OpalKelly/BRK1900-7CG/2.0/changelog.txt b/boards/OpalKelly/BRK1900-7CG/2.0/changelog.txt
new file mode 100644
index 000000000..d5a0ae676
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7CG/2.0/changelog.txt
@@ -0,0 +1,23 @@
+######### ECM1900-7CG W/ BRK1900 change log ############
+
+2.0
+- Added support for PS DisplayPort to the ZYNQ
+ preset for Rev B of the BRK1900. Note that Rev A
+ BRK1900s do not include PS DisplayPort. This
+ board file will still work with Rev A, but you
+ won't be able to use the DisplayPort. It will be
+ enabled in the preset, but you can ignore it or
+ disable it if necessary.
+
+- Added a default pulldown to MIO pin 44, which
+ is connected to the active low OEb signal for the
+ Si5341 clock generator on the ECM1900.
+
+- Add TXR4 Port G.
+
+- Add QSFP1 and QSFP2.
+
+- Add Si5341B clock output 3 and 4.
+
+1.0
+- ECM1900-7CG W/ BRK1900 initial board support
diff --git a/boards/OpalKelly/BRK1900-7CG/2.0/part0_pins.xml b/boards/OpalKelly/BRK1900-7CG/2.0/part0_pins.xml
new file mode 100644
index 000000000..41fef9206
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7CG/2.0/part0_pins.xml
@@ -0,0 +1,409 @@
+
+
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+
diff --git a/boards/OpalKelly/BRK1900-7CG/2.0/preset.xml b/boards/OpalKelly/BRK1900-7CG/2.0/preset.xml
new file mode 100644
index 000000000..39f0c0676
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7CG/2.0/preset.xml
@@ -0,0 +1,610 @@
+
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+
diff --git a/boards/OpalKelly/BRK1900-7CG/2.0/xitem.json b/boards/OpalKelly/BRK1900-7CG/2.0/xitem.json
new file mode 100644
index 000000000..faa452d6c
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7CG/2.0/xitem.json
@@ -0,0 +1,37 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "BRK1900-7CG",
+ "display": "ECM1900-7CG W/ BRK1900",
+ "revision": "2.0",
+ "description": "ECM1900-7CG W/ BRK1900",
+ "company": "opalkelly.com",
+ "company_display": "Opal Kelly",
+ "author": "Opal Kelly",
+ "contributors": [
+ {
+ "group": "Opal Kelly",
+ "url": "https://opalkelly.com/"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://opalkelly.com/products/ecm1900/",
+ "logo": "BRK1900-Top.png",
+ "search-keywords": [
+ "BRK1900",
+ "ECM1900",
+ "opalkelly.com",
+ "Opal Kelly",
+ "FrontPanel",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/OpalKelly/BRK1900-7EG/2.0/BRK1900-Top.png b/boards/OpalKelly/BRK1900-7EG/2.0/BRK1900-Top.png
new file mode 100644
index 000000000..f0386fb09
Binary files /dev/null and b/boards/OpalKelly/BRK1900-7EG/2.0/BRK1900-Top.png differ
diff --git a/boards/OpalKelly/BRK1900-7EG/2.0/board.xml b/boards/OpalKelly/BRK1900-7EG/2.0/board.xml
new file mode 100644
index 000000000..f4218320e
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EG/2.0/board.xml
@@ -0,0 +1,1071 @@
+
+
+
+
+ BRK1900 Board File Image
+
+
+
+ 2.0
+
+ 2.0
+ ECM1900-7EG W/ BRK1900
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 100 MHz default. Clock output 3 on Si5341B. See BRK1900 documentation for more information on the programmable clock generator.
+
+
+
+
+
+ 100 MHz default. Clock output 4 on Si5341B. See BRK1900 documentation for more information on the programmable clock generator.
+
+
+
+
+
+ 4 GiB DDR4 Memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ QSFP1 Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ QSFP2 Connector
+
+
+
+
+
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+
+
diff --git a/boards/OpalKelly/BRK1900-7EG/2.0/changelog.txt b/boards/OpalKelly/BRK1900-7EG/2.0/changelog.txt
new file mode 100644
index 000000000..b4f65a39b
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EG/2.0/changelog.txt
@@ -0,0 +1,23 @@
+######### ECM1900-7EG W/ BRK1900 change log ############
+
+2.0
+- Added support for PS DisplayPort to the ZYNQ
+ preset for Rev B of the BRK1900. Note that Rev A
+ BRK1900s do not include PS DisplayPort. This
+ board file will still work with Rev A, but you
+ won't be able to use the DisplayPort. It will be
+ enabled in the preset, but you can ignore it or
+ disable it if necessary.
+
+- Added a default pulldown to MIO pin 44, which
+ is connected to the active low OEb signal for the
+ Si5341 clock generator on the ECM1900.
+
+- Add TXR4 Port G.
+
+- Add QSFP1 and QSFP2.
+
+- Add Si5341B clock output 3 and 4.
+
+1.0
+- ECM1900-7EG W/ BRK1900 initial board support
diff --git a/boards/OpalKelly/BRK1900-7EG/2.0/part0_pins.xml b/boards/OpalKelly/BRK1900-7EG/2.0/part0_pins.xml
new file mode 100644
index 000000000..bca093641
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EG/2.0/part0_pins.xml
@@ -0,0 +1,409 @@
+
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+
diff --git a/boards/OpalKelly/BRK1900-7EG/2.0/preset.xml b/boards/OpalKelly/BRK1900-7EG/2.0/preset.xml
new file mode 100644
index 000000000..39f0c0676
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EG/2.0/preset.xml
@@ -0,0 +1,610 @@
+
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+
diff --git a/boards/OpalKelly/BRK1900-7EG/2.0/xitem.json b/boards/OpalKelly/BRK1900-7EG/2.0/xitem.json
new file mode 100644
index 000000000..260169ec9
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EG/2.0/xitem.json
@@ -0,0 +1,37 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "BRK1900-7EG",
+ "display": "ECM1900-7EG W/ BRK1900",
+ "revision": "2.0",
+ "description": "ECM1900-7EG W/ BRK1900",
+ "company": "opalkelly.com",
+ "company_display": "Opal Kelly",
+ "author": "Opal Kelly",
+ "contributors": [
+ {
+ "group": "Opal Kelly",
+ "url": "https://opalkelly.com/"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://opalkelly.com/products/ecm1900/",
+ "logo": "BRK1900-Top.png",
+ "search-keywords": [
+ "BRK1900",
+ "ECM1900",
+ "opalkelly.com",
+ "Opal Kelly",
+ "FrontPanel",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/OpalKelly/BRK1900-7EV/2.0/BRK1900-Top.png b/boards/OpalKelly/BRK1900-7EV/2.0/BRK1900-Top.png
new file mode 100644
index 000000000..f0386fb09
Binary files /dev/null and b/boards/OpalKelly/BRK1900-7EV/2.0/BRK1900-Top.png differ
diff --git a/boards/OpalKelly/BRK1900-7EV/2.0/board.xml b/boards/OpalKelly/BRK1900-7EV/2.0/board.xml
new file mode 100644
index 000000000..6b6a415d0
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EV/2.0/board.xml
@@ -0,0 +1,1071 @@
+
+
+
+
+ BRK1900 Board File Image
+
+
+
+ 2.0
+
+ 2.0
+ ECM1900-7EV W/ BRK1900
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 100 MHz default. Clock output 3 on Si5341B. See BRK1900 documentation for more information on the programmable clock generator.
+
+
+
+
+
+ 100 MHz default. Clock output 4 on Si5341B. See BRK1900 documentation for more information on the programmable clock generator.
+
+
+
+
+
+ 4 GiB DDR4 Memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ QSFP1 Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ QSFP2 Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/OpalKelly/BRK1900-7EV/2.0/changelog.txt b/boards/OpalKelly/BRK1900-7EV/2.0/changelog.txt
new file mode 100644
index 000000000..62218f2f7
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EV/2.0/changelog.txt
@@ -0,0 +1,23 @@
+######### ECM1900-7EV W/ BRK1900 change log ############
+
+2.0
+- Added support for PS DisplayPort to the ZYNQ
+ preset for Rev B of the BRK1900. Note that Rev A
+ BRK1900s do not include PS DisplayPort. This
+ board file will still work with Rev A, but you
+ won't be able to use the DisplayPort. It will be
+ enabled in the preset, but you can ignore it or
+ disable it if necessary.
+
+- Added a default pulldown to MIO pin 44, which
+ is connected to the active low OEb signal for the
+ Si5341 clock generator on the ECM1900.
+
+- Add TXR4 Port G.
+
+- Add QSFP1 and QSFP2.
+
+- Add Si5341B clock output 3 and 4.
+
+1.0
+- ECM1900-7EV W/ BRK1900 initial board support
diff --git a/boards/OpalKelly/BRK1900-7EV/2.0/part0_pins.xml b/boards/OpalKelly/BRK1900-7EV/2.0/part0_pins.xml
new file mode 100644
index 000000000..5b1b6275a
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EV/2.0/part0_pins.xml
@@ -0,0 +1,409 @@
+
+
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diff --git a/boards/OpalKelly/BRK1900-7EV/2.0/preset.xml b/boards/OpalKelly/BRK1900-7EV/2.0/preset.xml
new file mode 100644
index 000000000..39f0c0676
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EV/2.0/preset.xml
@@ -0,0 +1,610 @@
+
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+
+
+
diff --git a/boards/OpalKelly/BRK1900-7EV/2.0/xitem.json b/boards/OpalKelly/BRK1900-7EV/2.0/xitem.json
new file mode 100644
index 000000000..4ede6f1f5
--- /dev/null
+++ b/boards/OpalKelly/BRK1900-7EV/2.0/xitem.json
@@ -0,0 +1,37 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "BRK1900-7EV",
+ "display": "ECM1900-7EV W/ BRK1900",
+ "revision": "2.0",
+ "description": "ECM1900-7EV W/ BRK1900",
+ "company": "opalkelly.com",
+ "company_display": "Opal Kelly",
+ "author": "Opal Kelly",
+ "contributors": [
+ {
+ "group": "Opal Kelly",
+ "url": "https://opalkelly.com/"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://opalkelly.com/products/ecm1900/",
+ "logo": "BRK1900-Top.png",
+ "search-keywords": [
+ "BRK1900",
+ "ECM1900",
+ "opalkelly.com",
+ "Opal Kelly",
+ "FrontPanel",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/OpalKelly/XEM8305-AU15P-1E/1.0/XEM8305-Top.png b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/XEM8305-Top.png
new file mode 100644
index 000000000..9318c000b
Binary files /dev/null and b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/XEM8305-Top.png differ
diff --git a/boards/OpalKelly/XEM8305-AU15P-1E/1.0/board.xml b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/board.xml
new file mode 100644
index 000000000..b4ffe1cdd
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/board.xml
@@ -0,0 +1,289 @@
+
+
+
+
+ XEM8305 Board File Image
+
+
+
+ RevA
+
+ 1.0
+ XEM8305-AU15P-1E Integration Platform
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GiB DDR4 Memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 6 onboard LEDs. This component requires the use of the Opal Kelly LEDs Vivado IP Core version 1.0.5, which is included in the Opal Kelly Vivado IP Cores' Distribution starting from version 1.0.6. Ensure that you have downloaded at least version 1.0.6 of the Vivado IP Cores’ Distribution, available on the Opal Kelly downloads page. For more information see: https://docs.opalkelly.com/fpsdk/frontpanel-hdl/vivado-ip-core/getting-started/add-ip-cores-distribution-to-vivado/
+
+
+ This clock can be used as a general purpose Fabric Clock.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ This component requires the use of the Opal Kelly FrontPanel Subsystem Vivado IP Core version 1.0.6, which is included in the Opal Kelly Vivado IP Cores' Distribution starting from version 1.0.6. Ensure that you have downloaded at least version 1.0.6 of the Vivado IP Cores’ Distribution, available on the Opal Kelly downloads page. For more information see: https://docs.opalkelly.com/fpsdk/frontpanel-hdl/vivado-ip-core/getting-started/add-ip-cores-distribution-to-vivado/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8305-AU15P-1E/1.0/changelog.txt b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/changelog.txt
new file mode 100644
index 000000000..aa9dfc204
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### XEM8305-AU15P-1E Change log ##############
+
+1.0
+Initial creation (LEDs, DDR4, Diff Clks, FrontPanel)
diff --git a/boards/OpalKelly/XEM8305-AU15P-1E/1.0/part0_pins.xml b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/part0_pins.xml
new file mode 100644
index 000000000..3b3d49a85
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/part0_pins.xml
@@ -0,0 +1,103 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8305-AU15P-1E/1.0/preset.xml b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/preset.xml
new file mode 100644
index 000000000..45be33bda
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/preset.xml
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8305-AU15P-1E/1.0/xitem.json b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/xitem.json
new file mode 100644
index 000000000..16ec9fedf
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-1E/1.0/xitem.json
@@ -0,0 +1,37 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "XEM8305-AU15P-1E",
+ "display": "XEM8305-AU15P-1E Integration Platform",
+ "revision": "1.0",
+ "description": "XEM8305-AU15P-1E Integration Platform",
+ "company": "opalkelly.com",
+ "company_display": "Opal Kelly",
+ "author": "Opal Kelly",
+ "contributors": [
+ {
+ "group": "Opal Kelly",
+ "url": "https://opalkelly.com/"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://opalkelly.com/products/XEM8305/",
+ "logo": "XEM8305-Top.png",
+ "search-keywords": [
+ "XEM8305-AU15P-1E",
+ "opalkelly.com",
+ "board",
+ "AU15P",
+ "Opal Kelly",
+ "FrontPanel",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/OpalKelly/XEM8305-AU15P-2E/1.0/XEM8305-Top.png b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/XEM8305-Top.png
new file mode 100644
index 000000000..9318c000b
Binary files /dev/null and b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/XEM8305-Top.png differ
diff --git a/boards/OpalKelly/XEM8305-AU15P-2E/1.0/board.xml b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/board.xml
new file mode 100644
index 000000000..4a2f6f04d
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/board.xml
@@ -0,0 +1,289 @@
+
+
+
+
+ XEM8305 Board File Image
+
+
+
+ RevA
+
+ 1.0
+ XEM8305-AU15P-2E Integration Platform
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GiB DDR4 Memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 6 onboard LEDs. This component requires the use of the Opal Kelly LEDs Vivado IP Core version 1.0.5, which is included in the Opal Kelly Vivado IP Cores' Distribution starting from version 1.0.6. Ensure that you have downloaded at least version 1.0.6 of the Vivado IP Cores’ Distribution, available on the Opal Kelly downloads page. For more information see: https://docs.opalkelly.com/fpsdk/frontpanel-hdl/vivado-ip-core/getting-started/add-ip-cores-distribution-to-vivado/
+
+
+ This clock can be used as a general purpose Fabric Clock.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ This component requires the use of the Opal Kelly FrontPanel Subsystem Vivado IP Core version 1.0.6, which is included in the Opal Kelly Vivado IP Cores' Distribution starting from version 1.0.6. Ensure that you have downloaded at least version 1.0.6 of the Vivado IP Cores’ Distribution, available on the Opal Kelly downloads page. For more information see: https://docs.opalkelly.com/fpsdk/frontpanel-hdl/vivado-ip-core/getting-started/add-ip-cores-distribution-to-vivado/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8305-AU15P-2E/1.0/changelog.txt b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/changelog.txt
new file mode 100644
index 000000000..9f21d04be
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### XEM8305-AU15P-2E Change log ##############
+
+1.0
+Initial creation (LEDs, DDR4, Diff Clks, FrontPanel)
diff --git a/boards/OpalKelly/XEM8305-AU15P-2E/1.0/part0_pins.xml b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/part0_pins.xml
new file mode 100644
index 000000000..97a8eec53
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/part0_pins.xml
@@ -0,0 +1,103 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8305-AU15P-2E/1.0/preset.xml b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/preset.xml
new file mode 100644
index 000000000..1f0511440
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/preset.xml
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8305-AU15P-2E/1.0/xitem.json b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/xitem.json
new file mode 100644
index 000000000..7ea6be507
--- /dev/null
+++ b/boards/OpalKelly/XEM8305-AU15P-2E/1.0/xitem.json
@@ -0,0 +1,37 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "XEM8305-AU15P-2E",
+ "display": "XEM8305-AU15P-2E Integration Platform",
+ "revision": "1.0",
+ "description": "XEM8305-AU15P-2E Integration Platform",
+ "company": "opalkelly.com",
+ "company_display": "Opal Kelly",
+ "author": "Opal Kelly",
+ "contributors": [
+ {
+ "group": "Opal Kelly",
+ "url": "https://opalkelly.com/"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://opalkelly.com/products/XEM8305/",
+ "logo": "XEM8305-Top.png",
+ "search-keywords": [
+ "XEM8305-AU15P-2E",
+ "opalkelly.com",
+ "board",
+ "AU15P",
+ "Opal Kelly",
+ "FrontPanel",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/OpalKelly/XEM8350-KU115/1.0/XEM8350-Top.jpg b/boards/OpalKelly/XEM8350-KU115/1.0/XEM8350-Top.jpg
new file mode 100644
index 000000000..f74ee86b3
Binary files /dev/null and b/boards/OpalKelly/XEM8350-KU115/1.0/XEM8350-Top.jpg differ
diff --git a/boards/OpalKelly/XEM8350-KU115/1.0/board.xml b/boards/OpalKelly/XEM8350-KU115/1.0/board.xml
new file mode 100644
index 000000000..985af4c4f
--- /dev/null
+++ b/boards/OpalKelly/XEM8350-KU115/1.0/board.xml
@@ -0,0 +1,568 @@
+
+
+
+
+ XEM8350-KU115 Board File Image
+
+
+
+ RevD
+
+ 1.0
+ XEM8350-KU115 Integration Module
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
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+
+
+
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+
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+
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+
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+
+
+
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+
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+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 36 Gibit DDR4 Memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 onboard LEDs. This component MUST be used with the Opal Kelly LEDs IP that is provided through our downloads page at https://pins.opalkelly.com/downloads. Add IPs to the project through Settings->IP->Repository
+
+
+ I2C interface to configure the Si5338 programmable oscillator.
+
+
+ CLK0 on the Si5338B programmable oscillator. Factory programmed to output 100MHz by default. Connected to MGTREFCLK0 on transceiver bank 127.
+
+
+
+
+
+ CLK0 on the Si5338B programmable oscillator. Factory programmed to output 100MHz by default. Connected to MGTREFCLK0 on transceiver bank 225.
+
+
+
+
+
+ CLK2 on the Si5338B programmable oscillator. Factory programmed to output 152.3MHz by default. This reference frequency is used to realize the max supported memory speed of DDR4-2133.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CLK3 on the Si5338B programmable oscillator. Factory programmed to output 200MHz by default.
+
+
+
+
+
+ This component MUST be used with the Opal Kelly FrontPanel Subsystem IP that is provided through our downloads page at https://pins.opalkelly.com/downloads. Add IPs to the project through Settings->IP->Repository
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8350-KU115/1.0/changelog.txt b/boards/OpalKelly/XEM8350-KU115/1.0/changelog.txt
new file mode 100644
index 000000000..92dd4a91c
--- /dev/null
+++ b/boards/OpalKelly/XEM8350-KU115/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### XEM8350-KU115 Change log ##############
+
+1.0
+Initial creation (DDR4, Flash, LEDs, Si5338, FrontPanel)
diff --git a/boards/OpalKelly/XEM8350-KU115/1.0/part0_pins.xml b/boards/OpalKelly/XEM8350-KU115/1.0/part0_pins.xml
new file mode 100644
index 000000000..feeece236
--- /dev/null
+++ b/boards/OpalKelly/XEM8350-KU115/1.0/part0_pins.xml
@@ -0,0 +1,231 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
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+
+
+
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+
+
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+
+
+
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+
+
+
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+
+
+
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+
+
+
+
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+
+
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+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8350-KU115/1.0/preset.xml b/boards/OpalKelly/XEM8350-KU115/1.0/preset.xml
new file mode 100644
index 000000000..a2c70e14e
--- /dev/null
+++ b/boards/OpalKelly/XEM8350-KU115/1.0/preset.xml
@@ -0,0 +1,40 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8350-KU115/1.0/xitem.json b/boards/OpalKelly/XEM8350-KU115/1.0/xitem.json
new file mode 100644
index 000000000..639973ba5
--- /dev/null
+++ b/boards/OpalKelly/XEM8350-KU115/1.0/xitem.json
@@ -0,0 +1,37 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "XEM8350-KU115",
+ "display": "XEM8350-KU115 Integration Platform",
+ "revision": "1.0",
+ "description": "XEM8350-KU115 Integration Platform",
+ "company": "opalkelly.com",
+ "company_display": "Opal Kelly",
+ "author": "Opal Kelly",
+ "contributors": [
+ {
+ "group": "Opal Kelly",
+ "url": "https://opalkelly.com/"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://opalkelly.com/products/xem8350/",
+ "logo": "XEM8350-Top.jpg",
+ "search-keywords": [
+ "XEM8350-KU115",
+ "opalkelly.com",
+ "board",
+ "KU115",
+ "Opal Kelly",
+ "FrontPanel",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/OpalKelly/XEM8370-KU11P/1.0/XEM8370-Top.jpg b/boards/OpalKelly/XEM8370-KU11P/1.0/XEM8370-Top.jpg
new file mode 100644
index 000000000..f5a6197bf
Binary files /dev/null and b/boards/OpalKelly/XEM8370-KU11P/1.0/XEM8370-Top.jpg differ
diff --git a/boards/OpalKelly/XEM8370-KU11P/1.0/board.xml b/boards/OpalKelly/XEM8370-KU11P/1.0/board.xml
new file mode 100644
index 000000000..5014782ab
--- /dev/null
+++ b/boards/OpalKelly/XEM8370-KU11P/1.0/board.xml
@@ -0,0 +1,313 @@
+
+
+
+
+ XEM8370-KU11P Board File Image
+
+
+
+ RevA
+
+ 1.0
+ XEM8370-KU11P Integration Platform
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4 GiB DDR4 Memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 onboard LEDs. This component requires the use of the Opal Kelly LEDs Vivado IP Core version 1.0.4, which is included in the Opal Kelly Vivado IP Cores' Distribution starting from version 1.0.5. Ensure that you have downloaded at least version 1.0.5 of the Vivado IP Cores’ Distribution, available on the Opal Kelly downloads page. For more information see: https://docs.opalkelly.com/fpsdk/frontpanel-hdl/vivado-ip-core/getting-started/add-ip-cores-distribution-to-vivado/
+
+
+ This clock can be used as a general purpose Fabric Clock.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ This component requires the use of the Opal Kelly FrontPanel Subsystem Vivado IP Core version 1.0.5, which is included in the Opal Kelly Vivado IP Cores' Distribution starting from version 1.0.5. Ensure that you have downloaded at least version 1.0.5 of the Vivado IP Cores’ Distribution, available on the Opal Kelly downloads page. For more information see: https://docs.opalkelly.com/fpsdk/frontpanel-hdl/vivado-ip-core/getting-started/add-ip-cores-distribution-to-vivado/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/OpalKelly/XEM8370-KU11P/1.0/changelog.txt b/boards/OpalKelly/XEM8370-KU11P/1.0/changelog.txt
new file mode 100644
index 000000000..c73c65d9a
--- /dev/null
+++ b/boards/OpalKelly/XEM8370-KU11P/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### XEM8370-KU11P Change log ##############
+
+1.0
+Initial creation (LEDs, DDR4, Diff Clks, Flash, FrontPanel)
diff --git a/boards/OpalKelly/XEM8370-KU11P/1.0/part0_pins.xml b/boards/OpalKelly/XEM8370-KU11P/1.0/part0_pins.xml
new file mode 100644
index 000000000..bb7208194
--- /dev/null
+++ b/boards/OpalKelly/XEM8370-KU11P/1.0/part0_pins.xml
@@ -0,0 +1,127 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
diff --git a/boards/OpalKelly/XEM8370-KU11P/1.0/preset.xml b/boards/OpalKelly/XEM8370-KU11P/1.0/preset.xml
new file mode 100644
index 000000000..98b0f891b
--- /dev/null
+++ b/boards/OpalKelly/XEM8370-KU11P/1.0/preset.xml
@@ -0,0 +1,26 @@
+
+
+
+
+
+
+
+
+
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+
diff --git a/boards/OpalKelly/XEM8370-KU11P/1.0/xitem.json b/boards/OpalKelly/XEM8370-KU11P/1.0/xitem.json
new file mode 100644
index 000000000..d48a9a947
--- /dev/null
+++ b/boards/OpalKelly/XEM8370-KU11P/1.0/xitem.json
@@ -0,0 +1,37 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "XEM8370-KU11P",
+ "display": "XEM8370-KU11P Integration Platform",
+ "revision": "1.0",
+ "description": "XEM8370-KU11P Integration Platform",
+ "company": "opalkelly.com",
+ "company_display": "Opal Kelly",
+ "author": "Opal Kelly",
+ "contributors": [
+ {
+ "group": "Opal Kelly",
+ "url": "https://opalkelly.com/"
+ }
+ ],
+ "category": "Single Part",
+ "website": "https://opalkelly.com/products/XEM8370/",
+ "logo": "XEM8370-Top.jpg",
+ "search-keywords": [
+ "XEM8370-KU11P",
+ "opalkelly.com",
+ "board",
+ "KU11P",
+ "Opal Kelly",
+ "FrontPanel",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/README.md b/boards/Xilinx/README.md
new file mode 100644
index 000000000..55bc0b79c
--- /dev/null
+++ b/boards/Xilinx/README.md
@@ -0,0 +1,7 @@
+# XilinxBoardStore
+Welcome to the Xilinx Board Store Git Enterprise Repository
+
+----------
+
+> *Only add Xilinx boards in this directory. For adding boards of another vendor, create a new directory with vendor's company name under boards directory and add the boards in that directory.*
+
diff --git a/boards/Xilinx/ac701/1.4/LICENSE b/boards/Xilinx/ac701/1.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/ac701/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/ac701/1.4/ac701_board.jpg b/boards/Xilinx/ac701/1.4/ac701_board.jpg
new file mode 100644
index 000000000..bcc6babdf
Binary files /dev/null and b/boards/Xilinx/ac701/1.4/ac701_board.jpg differ
diff --git a/boards/Xilinx/ac701/1.4/board.xml b/boards/Xilinx/ac701/1.4/board.xml
new file mode 100644
index 000000000..7db3c9bdb
--- /dev/null
+++ b/boards/Xilinx/ac701/1.4/board.xml
@@ -0,0 +1,1124 @@
+
+
+
+
+
+
+
+ AC701 Board File Image
+
+
+
+ 1.1
+
+ 1.4
+ Artix-7 AC701 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+ DDR3 board interface, it can use MIG IP for connection.
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
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+
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+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
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+
+
+
+
+
+
+ 1 GB DDR3 memory SODIMM
+
+
+
+
+
+
+ DIP Switches 3 to 0
+
+
+ I2C
+
+
+ A 2-line by 16-character display
+
+
+ LEDs, 3 to 0, Active High
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sfp
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma in lvds mode
+
+
+
+
+
+
+
+
+
+
+
+
+ MDIO_IO
+
+
+ PHY RESET OUT
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ Edge Drive Jog Encoder Rotary Switch, INCB, PUSH, INCA, Active High
+
+
+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
+
+
+ Small Form-factor Pluggable connector
+
+
+ SFP MGT clock 0
+
+
+ SFP MGT clock 1
+
+
+ SFP SGMII
+
+
+ SMA LVDS
+
+
+ SMA SFP
+
+
+ SMA SGMII
+
+
+ 256 MB of nonvolatile storage that can be used for configuration or data storage
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/ac701/1.4/changelog.txt b/boards/Xilinx/ac701/1.4/changelog.txt
new file mode 100644
index 000000000..1319a41b5
--- /dev/null
+++ b/boards/Xilinx/ac701/1.4/changelog.txt
@@ -0,0 +1,5 @@
+######### AC701 Change log ##############
+
+1.4
+Added FMC support
+
diff --git a/boards/Xilinx/ac701/1.4/mig.prj b/boards/Xilinx/ac701/1.4/mig.prj
new file mode 100644
index 000000000..1385b0bce
--- /dev/null
+++ b/boards/Xilinx/ac701/1.4/mig.prj
@@ -0,0 +1,202 @@
+
+
+
+ design_1_mig_7series_0_0
+ 1
+ 1
+ OFF
+ 1024
+ ON
+ Enabled
+ xc7a200t-fbg676/-2
+ 2.1
+ Differential
+ Use System Clock
+ ACTIVE HIGH
+ FALSE
+ 0
+ 50 Ohms
+ 0
+
+ DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6
+ 2500
+ 1.8V
+ 4:1
+ 200
+ 1
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ FALSE
+
+ 14
+ 10
+ 3
+ 1.5V
+ 1073741824
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 6
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Enable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 5
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 30
+ 512
+ 1
+ 0
+
+
+
+
diff --git a/boards/Xilinx/ac701/1.4/part0_pins.xml b/boards/Xilinx/ac701/1.4/part0_pins.xml
new file mode 100644
index 000000000..aa57577d6
--- /dev/null
+++ b/boards/Xilinx/ac701/1.4/part0_pins.xml
@@ -0,0 +1,241 @@
+
+
+
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+
+
diff --git a/boards/Xilinx/ac701/1.4/preset.xml b/boards/Xilinx/ac701/1.4/preset.xml
new file mode 100644
index 000000000..4f2bb1937
--- /dev/null
+++ b/boards/Xilinx/ac701/1.4/preset.xml
@@ -0,0 +1,480 @@
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
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+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/ac701/1.4/xitem.json b/boards/Xilinx/ac701/1.4/xitem.json
new file mode 100644
index 000000000..49b4dfba5
--- /dev/null
+++ b/boards/Xilinx/ac701/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "ac701",
+ "display": "Artix-7 AC701 Evaluation Platform",
+ "revision": "1.4",
+ "description": "Artix-7 AC701 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "ac701_board.jpg",
+ "website": "http://www.xilinx.com/ac701",
+ "search-keywords": [
+ "ac701",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/emb-plus-vpr-4616/1.0/LICENSE b/boards/Xilinx/emb-plus-vpr-4616/1.0/LICENSE
new file mode 100644
index 000000000..5258ee4bc
--- /dev/null
+++ b/boards/Xilinx/emb-plus-vpr-4616/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2024, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/emb-plus-vpr-4616/1.0/README.md b/boards/Xilinx/emb-plus-vpr-4616/1.0/README.md
new file mode 100644
index 000000000..987f22249
--- /dev/null
+++ b/boards/Xilinx/emb-plus-vpr-4616/1.0/README.md
@@ -0,0 +1,4 @@
+Validate that the xcve2802-vsvh1760-2LP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/emb-plus-vpr-4616/1.0/board.xml b/boards/Xilinx/emb-plus-vpr-4616/1.0/board.xml
new file mode 100644
index 000000000..c3956da5d
--- /dev/null
+++ b/boards/Xilinx/emb-plus-vpr-4616/1.0/board.xml
@@ -0,0 +1,883 @@
+
+
+
+
+
+
+
+ Embedded+ Sapphire VPR-4616"
+
+
+
+
+ Rev 1.0
+
+
+ 1.0
+
+ Embedded+ Sapphire VPR-4616
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVE2302 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PCIE on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+ PCIE REFCLK on Bank 103"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/emb-plus-vpr-4616/1.0/changelog.txt b/boards/Xilinx/emb-plus-vpr-4616/1.0/changelog.txt
new file mode 100644
index 000000000..ee6e18113
--- /dev/null
+++ b/boards/Xilinx/emb-plus-vpr-4616/1.0/changelog.txt
@@ -0,0 +1,5 @@
+######### emb-plus-vpr-4616 change log ##############
+1.0 - 2024.1
+Initial support for Embedded+ Sapphire VPR-4616 board
+
+
diff --git a/boards/Xilinx/emb-plus-vpr-4616/1.0/part0_pins.xml b/boards/Xilinx/emb-plus-vpr-4616/1.0/part0_pins.xml
new file mode 100644
index 000000000..f46384552
--- /dev/null
+++ b/boards/Xilinx/emb-plus-vpr-4616/1.0/part0_pins.xml
@@ -0,0 +1,195 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/Xilinx/emb-plus-vpr-4616/1.0/preset.xml b/boards/Xilinx/emb-plus-vpr-4616/1.0/preset.xml
new file mode 100644
index 000000000..53e62a108
--- /dev/null
+++ b/boards/Xilinx/emb-plus-vpr-4616/1.0/preset.xml
@@ -0,0 +1,341 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/emb-plus-vpr-4616/1.0/xitem.json b/boards/Xilinx/emb-plus-vpr-4616/1.0/xitem.json
new file mode 100644
index 000000000..4e6f45c13
--- /dev/null
+++ b/boards/Xilinx/emb-plus-vpr-4616/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "emb-plus-vpr-4616",
+ "display": "Embedded+ Sapphire VPR-4616",
+ "revision": "1.0",
+ "description": "Embedded+ Sapphire VPR-4616",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "skemidi",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/emb-plus-vpr-4616",
+ "search-keywords": [
+ "emb-plus-vpr-4616",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/k24c/1.0/LICENSE b/boards/Xilinx/k24c/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/k24c/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k24c/1.0/board.xml b/boards/Xilinx/k24c/1.0/board.xml
new file mode 100644
index 000000000..3e077fab9
--- /dev/null
+++ b/boards/Xilinx/k24c/1.0/board.xml
@@ -0,0 +1,484 @@
+
+
+
+
+
+
+
+
+ Kria K24C Production SOM Image
+
+
+
+
+ Rev_A01
+
+
+ 1.0
+
+ Kria K24C SOM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/k24c/1.0/changelog.txt b/boards/Xilinx/k24c/1.0/changelog.txt
new file mode 100644
index 000000000..ca167bea1
--- /dev/null
+++ b/boards/Xilinx/k24c/1.0/changelog.txt
@@ -0,0 +1,3 @@
+######### K24C SOM changelog ############
+1.0 (2023.1_kria_update1)
+Initial release
\ No newline at end of file
diff --git a/boards/Xilinx/k24c/1.0/k24_board.png b/boards/Xilinx/k24c/1.0/k24_board.png
new file mode 100644
index 000000000..cc24011b3
Binary files /dev/null and b/boards/Xilinx/k24c/1.0/k24_board.png differ
diff --git a/boards/Xilinx/k24c/1.0/part0_pins.xml b/boards/Xilinx/k24c/1.0/part0_pins.xml
new file mode 100644
index 000000000..6837884a7
--- /dev/null
+++ b/boards/Xilinx/k24c/1.0/part0_pins.xml
@@ -0,0 +1,108 @@
+
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\ No newline at end of file
diff --git a/boards/Xilinx/k24c/1.0/preset.xml b/boards/Xilinx/k24c/1.0/preset.xml
new file mode 100644
index 000000000..6482d3e28
--- /dev/null
+++ b/boards/Xilinx/k24c/1.0/preset.xml
@@ -0,0 +1,420 @@
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diff --git a/boards/Xilinx/k24c/1.0/xitem.json b/boards/Xilinx/k24c/1.0/xitem.json
new file mode 100644
index 000000000..460612812
--- /dev/null
+++ b/boards/Xilinx/k24c/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k24c",
+ "display": "Kria K24C SOM",
+ "revision": "1.0",
+ "description": "Kria K24C SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "ashishd",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "k24_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/k24i/1.0/LICENSE b/boards/Xilinx/k24i/1.0/LICENSE
new file mode 100644
index 000000000..7410fef0d
--- /dev/null
+++ b/boards/Xilinx/k24i/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k24i/1.0/board.xml b/boards/Xilinx/k24i/1.0/board.xml
new file mode 100644
index 000000000..32ce39c2d
--- /dev/null
+++ b/boards/Xilinx/k24i/1.0/board.xml
@@ -0,0 +1,484 @@
+
+
+
+
+
+
+
+
+ Kria K24C Production SOM Image
+
+
+
+
+ Rev_A01
+
+
+ 1.0
+
+ Kria K24I SOM
+
+
+
+
+
+
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+ FPGA part on the board
+
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+
diff --git a/boards/Xilinx/k24i/1.0/changelog.txt b/boards/Xilinx/k24i/1.0/changelog.txt
new file mode 100644
index 000000000..3afd2de54
--- /dev/null
+++ b/boards/Xilinx/k24i/1.0/changelog.txt
@@ -0,0 +1,3 @@
+######### K24I SOM changelog ############
+1.0 (2023.1_kria_update1)
+Initial release
\ No newline at end of file
diff --git a/boards/Xilinx/k24i/1.0/k24_board.png b/boards/Xilinx/k24i/1.0/k24_board.png
new file mode 100644
index 000000000..cc24011b3
Binary files /dev/null and b/boards/Xilinx/k24i/1.0/k24_board.png differ
diff --git a/boards/Xilinx/k24i/1.0/part0_pins.xml b/boards/Xilinx/k24i/1.0/part0_pins.xml
new file mode 100644
index 000000000..db2f0047d
--- /dev/null
+++ b/boards/Xilinx/k24i/1.0/part0_pins.xml
@@ -0,0 +1,108 @@
+
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+
+
\ No newline at end of file
diff --git a/boards/Xilinx/k24i/1.0/preset.xml b/boards/Xilinx/k24i/1.0/preset.xml
new file mode 100644
index 000000000..8edad6923
--- /dev/null
+++ b/boards/Xilinx/k24i/1.0/preset.xml
@@ -0,0 +1,422 @@
+
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diff --git a/boards/Xilinx/k24i/1.0/xitem.json b/boards/Xilinx/k24i/1.0/xitem.json
new file mode 100644
index 000000000..8ac9082fe
--- /dev/null
+++ b/boards/Xilinx/k24i/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k24i",
+ "display": "Kria K24I SOM",
+ "revision": "1.0",
+ "description": "Kria K24I SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "ashishd",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "k24_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/k26c/1.2/LICENSE b/boards/Xilinx/k26c/1.2/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/k26c/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k26c/1.2/board.xml b/boards/Xilinx/k26c/1.2/board.xml
new file mode 100644
index 000000000..4682c07f1
--- /dev/null
+++ b/boards/Xilinx/k26c/1.2/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria K26C Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.2
+
+ Kria K26C SOM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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diff --git a/boards/Xilinx/k26c/1.2/changelog.txt b/boards/Xilinx/k26c/1.2/changelog.txt
new file mode 100644
index 000000000..1b197288f
--- /dev/null
+++ b/boards/Xilinx/k26c/1.2/changelog.txt
@@ -0,0 +1,10 @@
+######### Vision SOM changelog ############
+1.2
+Added second connector (SOM240_2)
+
+1.1
+Initial release for public (2020.2.2_web)
+Same version went into 2021.1
+
+1.0
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/k26c/1.2/k26_board.PNG b/boards/Xilinx/k26c/1.2/k26_board.PNG
new file mode 100644
index 000000000..c701ac435
Binary files /dev/null and b/boards/Xilinx/k26c/1.2/k26_board.PNG differ
diff --git a/boards/Xilinx/k26c/1.2/part0_pins.xml b/boards/Xilinx/k26c/1.2/part0_pins.xml
new file mode 100644
index 000000000..c7d1288bf
--- /dev/null
+++ b/boards/Xilinx/k26c/1.2/part0_pins.xml
@@ -0,0 +1,252 @@
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\ No newline at end of file
diff --git a/boards/Xilinx/k26c/1.2/preset.xml b/boards/Xilinx/k26c/1.2/preset.xml
new file mode 100644
index 000000000..c9ab48876
--- /dev/null
+++ b/boards/Xilinx/k26c/1.2/preset.xml
@@ -0,0 +1,362 @@
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diff --git a/boards/Xilinx/k26c/1.2/xitem.json b/boards/Xilinx/k26c/1.2/xitem.json
new file mode 100644
index 000000000..2620992f7
--- /dev/null
+++ b/boards/Xilinx/k26c/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k26c",
+ "display": "Kria K26C SOM",
+ "revision": "1.2",
+ "description": "Kria K26C SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "k26c_board.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/k26c/1.3/LICENSE b/boards/Xilinx/k26c/1.3/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/k26c/1.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k26c/1.3/board.xml b/boards/Xilinx/k26c/1.3/board.xml
new file mode 100644
index 000000000..a9076d6a4
--- /dev/null
+++ b/boards/Xilinx/k26c/1.3/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria K26C Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.3
+
+ Kria K26C SOM
+
+
+
+
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+ FPGA part on the board
+
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diff --git a/boards/Xilinx/k26c/1.3/changelog.txt b/boards/Xilinx/k26c/1.3/changelog.txt
new file mode 100644
index 000000000..f85f0a521
--- /dev/null
+++ b/boards/Xilinx/k26c/1.3/changelog.txt
@@ -0,0 +1,12 @@
+######### Vision SOM changelog ############
+1.3(2021.2)
+IO Trace length delays added
+
+1.2(2021.1)
+Added second connector (SOM240_2)
+
+1.1
+Initial release for public (2020.2.2_web)
+
+1.0
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/k26c/1.3/k26_board.PNG b/boards/Xilinx/k26c/1.3/k26_board.PNG
new file mode 100644
index 000000000..c701ac435
Binary files /dev/null and b/boards/Xilinx/k26c/1.3/k26_board.PNG differ
diff --git a/boards/Xilinx/k26c/1.3/part0_pins.xml b/boards/Xilinx/k26c/1.3/part0_pins.xml
new file mode 100644
index 000000000..75bc02d01
--- /dev/null
+++ b/boards/Xilinx/k26c/1.3/part0_pins.xml
@@ -0,0 +1,231 @@
+
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\ No newline at end of file
diff --git a/boards/Xilinx/k26c/1.3/preset.xml b/boards/Xilinx/k26c/1.3/preset.xml
new file mode 100644
index 000000000..c9ab48876
--- /dev/null
+++ b/boards/Xilinx/k26c/1.3/preset.xml
@@ -0,0 +1,362 @@
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diff --git a/boards/Xilinx/k26c/1.3/xitem.json b/boards/Xilinx/k26c/1.3/xitem.json
new file mode 100644
index 000000000..c1987b8c7
--- /dev/null
+++ b/boards/Xilinx/k26c/1.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k26c",
+ "display": "Kria K26C SOM",
+ "revision": "1.3",
+ "description": "Kria K26C SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "k26c_board.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/k26c/1.4/K26c_board.png b/boards/Xilinx/k26c/1.4/K26c_board.png
new file mode 100644
index 000000000..8a678b730
Binary files /dev/null and b/boards/Xilinx/k26c/1.4/K26c_board.png differ
diff --git a/boards/Xilinx/k26c/1.4/LICENSE b/boards/Xilinx/k26c/1.4/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/k26c/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k26c/1.4/board.xml b/boards/Xilinx/k26c/1.4/board.xml
new file mode 100644
index 000000000..4cf02eb57
--- /dev/null
+++ b/boards/Xilinx/k26c/1.4/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria K26C Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.4
+
+ Kria K26C SOM
+
+
+
+
+
+
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+ FPGA part on the board
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diff --git a/boards/Xilinx/k26c/1.4/changelog.txt b/boards/Xilinx/k26c/1.4/changelog.txt
new file mode 100644
index 000000000..4054c6e28
--- /dev/null
+++ b/boards/Xilinx/k26c/1.4/changelog.txt
@@ -0,0 +1,15 @@
+######### Vision SOM changelog ############
+1.4(2022.2)
+Display port enabled, SD,eMMC is be mapped to MIO13-22, GPIO1, and MIO32, MIO33, MIO34(PMU GIOs) Disabled.
+
+1.3(2021.2)
+IO Trace length delays added
+
+1.2(2021.1)
+Added second connector (SOM240_2)
+
+1.1
+Initial release for public (2020.2.2_web)
+
+1.0
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/k26c/1.4/part0_pins.xml b/boards/Xilinx/k26c/1.4/part0_pins.xml
new file mode 100644
index 000000000..75bc02d01
--- /dev/null
+++ b/boards/Xilinx/k26c/1.4/part0_pins.xml
@@ -0,0 +1,231 @@
+
+
+
+
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+
\ No newline at end of file
diff --git a/boards/Xilinx/k26c/1.4/preset.xml b/boards/Xilinx/k26c/1.4/preset.xml
new file mode 100644
index 000000000..f510d227d
--- /dev/null
+++ b/boards/Xilinx/k26c/1.4/preset.xml
@@ -0,0 +1,372 @@
+
+
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diff --git a/boards/Xilinx/k26c/1.4/xitem.json b/boards/Xilinx/k26c/1.4/xitem.json
new file mode 100644
index 000000000..8857fc19a
--- /dev/null
+++ b/boards/Xilinx/k26c/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k26c",
+ "display": "Kria K26C SOM",
+ "revision": "1.4",
+ "description": "Kria K26C SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "K26c_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/k26i/1.2/LICENSE b/boards/Xilinx/k26i/1.2/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/k26i/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k26i/1.2/board.xml b/boards/Xilinx/k26i/1.2/board.xml
new file mode 100644
index 000000000..1b56b8097
--- /dev/null
+++ b/boards/Xilinx/k26i/1.2/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria K26I Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.2
+
+ Kria K26I SOM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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diff --git a/boards/Xilinx/k26i/1.2/changelog.txt b/boards/Xilinx/k26i/1.2/changelog.txt
new file mode 100644
index 000000000..1b197288f
--- /dev/null
+++ b/boards/Xilinx/k26i/1.2/changelog.txt
@@ -0,0 +1,10 @@
+######### Vision SOM changelog ############
+1.2
+Added second connector (SOM240_2)
+
+1.1
+Initial release for public (2020.2.2_web)
+Same version went into 2021.1
+
+1.0
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/k26i/1.2/k26_board.PNG b/boards/Xilinx/k26i/1.2/k26_board.PNG
new file mode 100644
index 000000000..c701ac435
Binary files /dev/null and b/boards/Xilinx/k26i/1.2/k26_board.PNG differ
diff --git a/boards/Xilinx/k26i/1.2/part0_pins.xml b/boards/Xilinx/k26i/1.2/part0_pins.xml
new file mode 100644
index 000000000..fc7d17a84
--- /dev/null
+++ b/boards/Xilinx/k26i/1.2/part0_pins.xml
@@ -0,0 +1,252 @@
+
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\ No newline at end of file
diff --git a/boards/Xilinx/k26i/1.2/preset.xml b/boards/Xilinx/k26i/1.2/preset.xml
new file mode 100644
index 000000000..c9ab48876
--- /dev/null
+++ b/boards/Xilinx/k26i/1.2/preset.xml
@@ -0,0 +1,362 @@
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diff --git a/boards/Xilinx/k26i/1.2/xitem.json b/boards/Xilinx/k26i/1.2/xitem.json
new file mode 100644
index 000000000..2565bbbef
--- /dev/null
+++ b/boards/Xilinx/k26i/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k26i",
+ "display": "Kria K26i SOM",
+ "revision": "1.2",
+ "description": "Kria K26I SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "k26i_board.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/k26i/1.3/LICENSE b/boards/Xilinx/k26i/1.3/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/k26i/1.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k26i/1.3/board.xml b/boards/Xilinx/k26i/1.3/board.xml
new file mode 100644
index 000000000..36e092c25
--- /dev/null
+++ b/boards/Xilinx/k26i/1.3/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria K26I Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.3
+
+ Kria K26I SOM
+
+
+
+
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+ FPGA part on the board
+
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diff --git a/boards/Xilinx/k26i/1.3/changelog.txt b/boards/Xilinx/k26i/1.3/changelog.txt
new file mode 100644
index 000000000..847b3e61f
--- /dev/null
+++ b/boards/Xilinx/k26i/1.3/changelog.txt
@@ -0,0 +1,13 @@
+######### Vision SOM changelog ############
+1.3(2021.2)
+IO Trace length delays added
+
+1.2(2021.1)
+Added second connector (SOM240_2)
+
+1.1
+Initial release for public (2020.2.2_web)
+Same version went into 2021.1
+
+1.0
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/k26i/1.3/k26_board.PNG b/boards/Xilinx/k26i/1.3/k26_board.PNG
new file mode 100644
index 000000000..c701ac435
Binary files /dev/null and b/boards/Xilinx/k26i/1.3/k26_board.PNG differ
diff --git a/boards/Xilinx/k26i/1.3/part0_pins.xml b/boards/Xilinx/k26i/1.3/part0_pins.xml
new file mode 100644
index 000000000..c06e61ea5
--- /dev/null
+++ b/boards/Xilinx/k26i/1.3/part0_pins.xml
@@ -0,0 +1,231 @@
+
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\ No newline at end of file
diff --git a/boards/Xilinx/k26i/1.3/preset.xml b/boards/Xilinx/k26i/1.3/preset.xml
new file mode 100644
index 000000000..c9ab48876
--- /dev/null
+++ b/boards/Xilinx/k26i/1.3/preset.xml
@@ -0,0 +1,362 @@
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diff --git a/boards/Xilinx/k26i/1.3/xitem.json b/boards/Xilinx/k26i/1.3/xitem.json
new file mode 100644
index 000000000..5e0b7bae0
--- /dev/null
+++ b/boards/Xilinx/k26i/1.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k26i",
+ "display": "Kria K26i SOM",
+ "revision": "1.3",
+ "description": "Kria K26I SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "k26i_board.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/k26i/1.4/K26i_board.png b/boards/Xilinx/k26i/1.4/K26i_board.png
new file mode 100644
index 000000000..8a678b730
Binary files /dev/null and b/boards/Xilinx/k26i/1.4/K26i_board.png differ
diff --git a/boards/Xilinx/k26i/1.4/LICENSE b/boards/Xilinx/k26i/1.4/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/k26i/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/k26i/1.4/board.xml b/boards/Xilinx/k26i/1.4/board.xml
new file mode 100644
index 000000000..74274a96e
--- /dev/null
+++ b/boards/Xilinx/k26i/1.4/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria K26I Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.4
+
+ Kria K26I SOM
+
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+ FPGA part on the board
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diff --git a/boards/Xilinx/k26i/1.4/changelog.txt b/boards/Xilinx/k26i/1.4/changelog.txt
new file mode 100644
index 000000000..3945a6d59
--- /dev/null
+++ b/boards/Xilinx/k26i/1.4/changelog.txt
@@ -0,0 +1,16 @@
+######### Vision SOM changelog ############
+1.4(2022.2)
+Display port enabled, SD,eMMC is be mapped to MIO13-22, GPIO1, and MIO32, MIO33, MIO34(PMU GIOs) Disabled.
+
+1.3(2021.2)
+IO Trace length delays added
+
+1.2(2021.1)
+Added second connector (SOM240_2)
+
+1.1
+Initial release for public (2020.2.2_web)
+Same version went into 2021.1
+
+1.0
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/k26i/1.4/part0_pins.xml b/boards/Xilinx/k26i/1.4/part0_pins.xml
new file mode 100644
index 000000000..c06e61ea5
--- /dev/null
+++ b/boards/Xilinx/k26i/1.4/part0_pins.xml
@@ -0,0 +1,231 @@
+
+
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\ No newline at end of file
diff --git a/boards/Xilinx/k26i/1.4/preset.xml b/boards/Xilinx/k26i/1.4/preset.xml
new file mode 100644
index 000000000..176bf51bb
--- /dev/null
+++ b/boards/Xilinx/k26i/1.4/preset.xml
@@ -0,0 +1,372 @@
+
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diff --git a/boards/Xilinx/k26i/1.4/xitem.json b/boards/Xilinx/k26i/1.4/xitem.json
new file mode 100644
index 000000000..da3654cba
--- /dev/null
+++ b/boards/Xilinx/k26i/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "k26i",
+ "display": "Kria K26i SOM",
+ "revision": "1.4",
+ "description": "Kria K26I SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "K26i_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kc705/1.6/LICENSE b/boards/Xilinx/kc705/1.6/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/kc705/1.6/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kc705/1.6/board.xml b/boards/Xilinx/kc705/1.6/board.xml
new file mode 100644
index 000000000..0910b5c0a
--- /dev/null
+++ b/boards/Xilinx/kc705/1.6/board.xml
@@ -0,0 +1,2040 @@
+
+
+
+
+
+
+
+ KC705 Board File Image
+
+
+
+ 1.1
+
+ 1.6
+ Kintex-7 KC705 Evaluation Platform
+
+
+
+
+
+
+ Impacts connection between flash_qspi and flash_bpi.If value=true, flash_qspi will be enabled
+
+
+ Impacts connection between flash_qspi and flash_bpi.If value=true, flash_bpi will be enabled
+
+
+ value=true will configure component phy to work in MII or GMII mode or RGMII mode based on J30 and J64
+
+
+ value=true will configure component phy to work in SGMII mode.
+
+
+ value=true will configure component phy to work in MII or GMII mode.
+
+
+ value=true will configure component phy to work in SGMII mode.
+
+
+ value=true will configure component phy either to work RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+ DDR3 board interface, it can use MIG IP for connection.
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in GMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+ true
+ false
+ false
+
+
+
+
+ Primary interface to communicate with ethernet phy in MII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+ true
+ false
+ false
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+ false
+ false
+ true
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+ false
+ true
+ false
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GB DDR3 memory SODIMM
+
+
+
+
+
+
+ PHY on the board
+
+
+ To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 true} {J64 false}
+
+
+
+
+
+
+
+
+
+
+ To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 true} {J64 false}
+
+
+
+
+
+
+
+
+
+
+ To enable this mode jumpers need to be {J29_P2_P3 true} {J30_P2_P3 true} {J64 false}
+
+
+
+
+
+
+
+
+
+
+
+ To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 false} {J30_P2_P3 false} {J64 true}
+
+
+
+
+
+
+
+
+
+
+
+
+ DIP Switches 3 to 0
+
+
+ Edge Drive Jog Encoder Rotary Switch, INCB, PUSH, INCA, Active High
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ Ethernet 125 MHz SGMII GTX Clock
+
+
+
+
+
+ PHY outside the board connected through sfp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma in lvds mode
+
+
+
+
+
+
+
+
+
+
+
+
+ SMA MGT CLOCK
+
+
+
+
+
+ 128 MB of nonvolatile storage that can be used for configuration or software storage
+
+
+ To enable this mode jumpers need to be {SW13_M0 false} {SW13_M1 true}
+
+
+
+
+
+
+
+
+
+
+ 128 MB of nonvolatile storage that can be used for configuration or data storage
+
+
+ To enable this mode jumpers need to be {SW13_M0 true} {SW13_M1 false}
+
+
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ A 2-line by 16-character display
+
+
+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.6/changelog.txt b/boards/Xilinx/kc705/1.6/changelog.txt
new file mode 100644
index 000000000..f4185b2f5
--- /dev/null
+++ b/boards/Xilinx/kc705/1.6/changelog.txt
@@ -0,0 +1,7 @@
+######### KC705 Change log ##############
+1.6
+Updated mig.prj to fix mrCasLatency and mr2CasLatency
+
+1.5
+Added FMC support
+
diff --git a/boards/Xilinx/kc705/1.6/kc705_board.jpeg b/boards/Xilinx/kc705/1.6/kc705_board.jpeg
new file mode 100644
index 000000000..ce15e5d7f
Binary files /dev/null and b/boards/Xilinx/kc705/1.6/kc705_board.jpeg differ
diff --git a/boards/Xilinx/kc705/1.6/mig.prj b/boards/Xilinx/kc705/1.6/mig.prj
new file mode 100644
index 000000000..49d6b0292
--- /dev/null
+++ b/boards/Xilinx/kc705/1.6/mig.prj
@@ -0,0 +1,222 @@
+
+
+
+ design_1_mig_7series_0_0
+
+ 1
+
+ 1
+
+ OFF
+
+ 1024
+
+ ON
+
+ Enabled
+
+ xc7k325t-ffg900/-2
+
+ 4.2
+
+ Differential
+
+ Use System Clock
+
+ ACTIVE HIGH
+
+ FALSE
+
+ 0
+
+ 50 Ohms
+
+ 1
+
+
+ DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6
+ 1250
+ 1.8V
+ 4:1
+ 200
+ 1
+ 800
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ 4
+ FALSE
+
+ 14
+ 10
+ 3
+ 1.5V
+ 1073741824
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Enable
+ RZQ/6
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 1
+ 1
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.6/part0_pins.xml b/boards/Xilinx/kc705/1.6/part0_pins.xml
new file mode 100644
index 000000000..07211e44c
--- /dev/null
+++ b/boards/Xilinx/kc705/1.6/part0_pins.xml
@@ -0,0 +1,428 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
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+
+
+
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+
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+
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+
+
+
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+
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+
+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.6/preset.xml b/boards/Xilinx/kc705/1.6/preset.xml
new file mode 100644
index 000000000..50188eb10
--- /dev/null
+++ b/boards/Xilinx/kc705/1.6/preset.xml
@@ -0,0 +1,543 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
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+
+
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+
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+
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+
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+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
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+
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+
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+
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+
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+
+
+
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+
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+
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+
+
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+
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+
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+
+
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+
+
+
+
+
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+
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+
+
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+
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+
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+
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+
+
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+
+
+
+
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+
+
+
+
+
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+
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+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.6/xitem.json b/boards/Xilinx/kc705/1.6/xitem.json
new file mode 100644
index 000000000..83e848cf3
--- /dev/null
+++ b/boards/Xilinx/kc705/1.6/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kc705",
+ "display": "Kintex-7 KC705 Evaluation Platform",
+ "revision": "1.6",
+ "description": "Kintex-7 KC705 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "kc705_board.jpeg",
+ "website": "http://www.xilinx.com/kc705",
+ "search-keywords": [
+ "kc705",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kc705/1.7/LICENSE b/boards/Xilinx/kc705/1.7/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kc705/1.7/board.xml b/boards/Xilinx/kc705/1.7/board.xml
new file mode 100644
index 000000000..e28d9a2dd
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/board.xml
@@ -0,0 +1,2069 @@
+
+
+
+
+
+
+
+ KC705 Board File Image
+
+
+
+ 1.1
+
+ 1.7
+ Kintex-7 KC705 Evaluation Platform
+
+
+
+
+
+
+ Impacts connection between flash_qspi and flash_bpi.If value=true, flash_qspi will be enabled
+
+
+ Impacts connection between flash_qspi and flash_bpi.If value=true, flash_bpi will be enabled
+
+
+ value=true will configure component phy to work in MII or GMII mode or RGMII mode based on J30 and J64
+
+
+ value=true will configure component phy to work in SGMII mode.
+
+
+ value=true will configure component phy to work in MII or GMII mode.
+
+
+ value=true will configure component phy to work in SGMII mode.
+
+
+ value=true will configure component phy either to work RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+ DDR3 1G board interface, it can use MIG IP for connection.
+
+
+
+
+
+
+ DDR3 2G board interface, it can use MIG IP for connection.
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in GMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+ true
+ false
+ false
+
+
+
+
+ Primary interface to communicate with ethernet phy in MII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+ true
+ false
+ false
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+ false
+ false
+ true
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+ false
+ true
+ false
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
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+
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+
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+
+
+ true
+ false
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GB DDR3 memory SODIMM MT8JTF12864HZ-1G6G1(old) / 2 GB DDR3 memory SODIMMMT4KTF25664HZ-1G9P1(new)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY on the board
+
+
+ To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 true} {J64 false}
+
+
+
+
+
+
+
+
+
+
+ To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 true} {J64 false}
+
+
+
+
+
+
+
+
+
+
+ To enable this mode jumpers need to be {J29_P2_P3 true} {J30_P2_P3 true} {J64 false}
+
+
+
+
+
+
+
+
+
+
+
+ To enable this mode jumpers need to be {J29_P1_P2 true} {J30_P1_P2 false} {J30_P2_P3 false} {J64 true}
+
+
+
+
+
+
+
+
+
+
+
+
+ DIP Switches 3 to 0
+
+
+ Edge Drive Jog Encoder Rotary Switch, INCB, PUSH, INCA, Active High
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ Ethernet 125 MHz SGMII GTX Clock
+
+
+
+
+
+ PHY outside the board connected through sfp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma in lvds mode
+
+
+
+
+
+
+
+
+
+
+
+
+ SMA MGT CLOCK
+
+
+
+
+
+ 128 MB of nonvolatile storage that can be used for configuration or software storage
+
+
+ To enable this mode jumpers need to be {SW13_M0 false} {SW13_M1 true}
+
+
+
+
+
+
+
+
+
+
+ 128 MB of nonvolatile storage that can be used for configuration or data storage
+
+
+ To enable this mode jumpers need to be {SW13_M0 true} {SW13_M1 false}
+
+
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ A 2-line by 16-character display
+
+
+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.7/changelog.txt b/boards/Xilinx/kc705/1.7/changelog.txt
new file mode 100644
index 000000000..d69b15e07
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/changelog.txt
@@ -0,0 +1,10 @@
+######### KC705 Change log ##############
+1.7 (2024.1)
+Added new ddr3 dimm support (SODIMMMT4KTF25664HZ-1G9P1 - 2G)
+
+1.6
+Updated mig.prj to fix mrCasLatency and mr2CasLatency
+
+1.5
+Added FMC support
+
diff --git a/boards/Xilinx/kc705/1.7/kc705_board.jpeg b/boards/Xilinx/kc705/1.7/kc705_board.jpeg
new file mode 100644
index 000000000..ce15e5d7f
Binary files /dev/null and b/boards/Xilinx/kc705/1.7/kc705_board.jpeg differ
diff --git a/boards/Xilinx/kc705/1.7/mig.prj b/boards/Xilinx/kc705/1.7/mig.prj
new file mode 100644
index 000000000..49d6b0292
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/mig.prj
@@ -0,0 +1,222 @@
+
+
+
+ design_1_mig_7series_0_0
+
+ 1
+
+ 1
+
+ OFF
+
+ 1024
+
+ ON
+
+ Enabled
+
+ xc7k325t-ffg900/-2
+
+ 4.2
+
+ Differential
+
+ Use System Clock
+
+ ACTIVE HIGH
+
+ FALSE
+
+ 0
+
+ 50 Ohms
+
+ 1
+
+
+ DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6
+ 1250
+ 1.8V
+ 4:1
+ 200
+ 1
+ 800
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ 4
+ FALSE
+
+ 14
+ 10
+ 3
+ 1.5V
+ 1073741824
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Enable
+ RZQ/6
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 1
+ 1
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.7/mig_2g.prj b/boards/Xilinx/kc705/1.7/mig_2g.prj
new file mode 100644
index 000000000..8d74cebb7
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/mig_2g.prj
@@ -0,0 +1,228 @@
+
+
+
+
+
+
+
+ design_1_mig_7series_0_0
+
+ 1
+
+ 1
+
+ OFF
+
+ 1024
+
+ ON
+
+ Enabled
+
+ xc7k325t-ffg900/-2
+
+ 4.2
+
+ Differential
+
+ Use System Clock
+
+ ACTIVE HIGH
+
+ FALSE
+
+ 0
+
+ 50 Ohms
+
+ 1
+
+
+ DDR3_SDRAM/SODIMMs/MT4KTF25664HZ-1G9
+ 1250
+ 1.8V
+ 4:1
+ 200
+ 1
+ 800
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ 4
+ FALSE
+
+ 15
+ 10
+ 3
+ 1.5V
+ 2147483648
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Enable
+ RZQ/6
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 31
+ 512
+ 1
+ 1
+
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.7/part0_pins.xml b/boards/Xilinx/kc705/1.7/part0_pins.xml
new file mode 100644
index 000000000..07211e44c
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/part0_pins.xml
@@ -0,0 +1,428 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kc705/1.7/preset.xml b/boards/Xilinx/kc705/1.7/preset.xml
new file mode 100644
index 000000000..73135974b
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/preset.xml
@@ -0,0 +1,552 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
+
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+
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+
+
+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
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diff --git a/boards/Xilinx/kc705/1.7/xitem.json b/boards/Xilinx/kc705/1.7/xitem.json
new file mode 100644
index 000000000..0144273a0
--- /dev/null
+++ b/boards/Xilinx/kc705/1.7/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kc705",
+ "display": "Kintex-7 KC705 Evaluation Platform",
+ "revision": "1.7",
+ "description": "Kintex-7 KC705 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "kc705_board.jpeg",
+ "website": "http://www.xilinx.com/kc705",
+ "search-keywords": [
+ "kc705",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kcu105/1.6/LICENSE b/boards/Xilinx/kcu105/1.6/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.6/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kcu105/1.6/board.xml b/boards/Xilinx/kcu105/1.6/board.xml
new file mode 100644
index 000000000..d2fb438e4
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.6/board.xml
@@ -0,0 +1,2045 @@
+
+
+
+
+
+
+ KCU105 Board File Image
+
+
+
+ 1.0
+
+ 1.6
+ Kintex-UltraScale KCU105 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+ Kintex-UltraScale FPGA part on the board
+
+
+ DDR4 board interface, it can use MIG IP for connection.
+
+
+
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+ 4-position user DIP Switch
+
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+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
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+
+
+
+
+
+
+ System Monitor Interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+ Edge Drive Jog Encoder Rotary Switch, INCB, PUSH, INCA, Active High
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller UART or using IIC interface in the Kintex fabric
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ PHY RESET OUT
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+ MGT Clock from SI570
+
+
+
+
+
+ SMA MGT Clock
+
+
+
+
+
+ Reference Clock from SI5328
+
+
+
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+ PHY outside the board connected through sma
+
+
+
+
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+ PCI Express
+
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+
diff --git a/boards/Xilinx/kcu105/1.6/changelog.txt b/boards/Xilinx/kcu105/1.6/changelog.txt
new file mode 100644
index 000000000..7f2a56c12
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.6/changelog.txt
@@ -0,0 +1,15 @@
+######### KCU105 Change log ##############
+1.6
+Added GT location for XDMA IP
+
+1.5
+Enabling System monitor board support
+
+1.4
+Fixed DDR4 clock IOSTANDARDS
+
+1.3
+Avoiding upper case IO attributes(slew, output-impedance etc)
+
+1.2
+Added FMC support
diff --git a/boards/Xilinx/kcu105/1.6/kcu105_board.jpeg b/boards/Xilinx/kcu105/1.6/kcu105_board.jpeg
new file mode 100644
index 000000000..824336d04
Binary files /dev/null and b/boards/Xilinx/kcu105/1.6/kcu105_board.jpeg differ
diff --git a/boards/Xilinx/kcu105/1.6/part0_pins.xml b/boards/Xilinx/kcu105/1.6/part0_pins.xml
new file mode 100644
index 000000000..5ce2c42fd
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.6/part0_pins.xml
@@ -0,0 +1,512 @@
+
+
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diff --git a/boards/Xilinx/kcu105/1.6/preset.xml b/boards/Xilinx/kcu105/1.6/preset.xml
new file mode 100644
index 000000000..8ac60381a
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.6/preset.xml
@@ -0,0 +1,485 @@
+
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diff --git a/boards/Xilinx/kcu105/1.6/xitem.json b/boards/Xilinx/kcu105/1.6/xitem.json
new file mode 100644
index 000000000..9e8b92772
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.6/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kcu105",
+ "display": "Kintex-UltraScale KCU105 Evaluation Platform",
+ "revision": "1.6",
+ "description": "Kintex-UltraScale KCU105 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "kcu105_board.jpeg",
+ "website": "www.xilinx.com/kcu105",
+ "search-keywords": [
+ "kcu105",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kcu105/1.7/LICENSE b/boards/Xilinx/kcu105/1.7/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.7/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kcu105/1.7/board.xml b/boards/Xilinx/kcu105/1.7/board.xml
new file mode 100644
index 000000000..343e63e2a
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.7/board.xml
@@ -0,0 +1,2354 @@
+
+
+
+
+
+
+ KCU105 Board File Image
+
+
+
+ 1.0
+ 1.1
+
+ 1.7
+ Kintex-UltraScale KCU105 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ Kintex-UltraScale FPGA part on the board
+
+
+
+ DDR4 board interface, it can use MIG IP for connection.
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use MIG IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
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+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
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+
+
+
+
+
+
+ System Monitor Interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+ Edge Drive Jog Encoder Rotary Switch, INCB, PUSH, INCA, Active High
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller UART or using IIC interface in the Kintex fabric
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ PHY RESET OUT
+
+
+ 256 of nonvolatile storage that can be used for configuration or data storage
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+ MGT Clock from SI570
+
+
+
+
+
+ SMA MGT Clock
+
+
+
+
+
+ Reference Clock from SI5328
+
+
+
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
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+ PHY outside the board connected through sma
+
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+ PCI Express
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diff --git a/boards/Xilinx/kcu105/1.7/changelog.txt b/boards/Xilinx/kcu105/1.7/changelog.txt
new file mode 100644
index 000000000..ccf7e791f
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.7/changelog.txt
@@ -0,0 +1,19 @@
+######### KCU105 Change log ##############
+1.7
+Added new DDR4 Memory part MT40A256M16LY-062E support ,Qspi Enabled
+Adding tag 'revision' so that this board file will be compatible with Board Rev 1.1
+
+1.6
+Added GT location for XDMA IP
+
+1.5
+Enabling System monitor board support
+
+1.4
+Fixed DDR4 clock IOSTANDARDS
+
+1.3
+Avoiding upper case IO attributes(slew, output-impedance etc)
+
+1.2
+Added FMC support
diff --git a/boards/Xilinx/kcu105/1.7/kcu105_board.jpeg b/boards/Xilinx/kcu105/1.7/kcu105_board.jpeg
new file mode 100644
index 000000000..824336d04
Binary files /dev/null and b/boards/Xilinx/kcu105/1.7/kcu105_board.jpeg differ
diff --git a/boards/Xilinx/kcu105/1.7/part0_pins.xml b/boards/Xilinx/kcu105/1.7/part0_pins.xml
new file mode 100644
index 000000000..5c6ef849d
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.7/part0_pins.xml
@@ -0,0 +1,517 @@
+
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diff --git a/boards/Xilinx/kcu105/1.7/preset.xml b/boards/Xilinx/kcu105/1.7/preset.xml
new file mode 100644
index 000000000..cdbbfa857
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.7/preset.xml
@@ -0,0 +1,510 @@
+
+
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+
diff --git a/boards/Xilinx/kcu105/1.7/xitem.json b/boards/Xilinx/kcu105/1.7/xitem.json
new file mode 100644
index 000000000..03257ea30
--- /dev/null
+++ b/boards/Xilinx/kcu105/1.7/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kcu105",
+ "display": "Kintex-UltraScale KCU105 Evaluation Platform",
+ "revision": "1.7",
+ "description": "Kintex-UltraScale KCU105 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "kcu105_board.jpeg",
+ "website": "www.xilinx.com/kcu105",
+ "search-keywords": [
+ "kcu105",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kcu116/1.4/LICENSE b/boards/Xilinx/kcu116/1.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kcu116/1.4/board.xml b/boards/Xilinx/kcu116/1.4/board.xml
new file mode 100644
index 000000000..a886ca500
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.4/board.xml
@@ -0,0 +1,1205 @@
+
+
+
+
+
+
+ KCU116 Board File Image
+
+
+
+ 1.0
+
+ 1.4
+ Kintex UltraScale+ KCU116 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ Kintex-UltraScale+ FPGA part on the board
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ 4Gb DDR4 SDRAM memory C1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ USer SMA clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ I2C
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+ PHY RESET OUT
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
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+
diff --git a/boards/Xilinx/kcu116/1.4/changelog.txt b/boards/Xilinx/kcu116/1.4/changelog.txt
new file mode 100644
index 000000000..5963f86ae
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.4/changelog.txt
@@ -0,0 +1,19 @@
+######### KCU116 change log ############
+1.4
+Added GT locations for XDMA IP
+Updated IOSTANDARD constraints for sysclk_125_p/n from LVDS to LVDS_25
+Enabled support for pcie4_uscale_plus IP
+Removed 125 Mhz system clock since correponding pins were part of HD IO bank
+
+1.3
+Enabled FMC Support in 2017.4
+
+1.2
+Avoiding upper case attributes
+
+1.1
+Enabled SGMII over LVDS support
+
+1.0
+KCU116 production board support
+
diff --git a/boards/Xilinx/kcu116/1.4/kcu116_board.jpeg b/boards/Xilinx/kcu116/1.4/kcu116_board.jpeg
new file mode 100644
index 000000000..1ee8f6451
Binary files /dev/null and b/boards/Xilinx/kcu116/1.4/kcu116_board.jpeg differ
diff --git a/boards/Xilinx/kcu116/1.4/part0_pins.xml b/boards/Xilinx/kcu116/1.4/part0_pins.xml
new file mode 100644
index 000000000..c73e2b5cc
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.4/part0_pins.xml
@@ -0,0 +1,301 @@
+
+
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diff --git a/boards/Xilinx/kcu116/1.4/preset.xml b/boards/Xilinx/kcu116/1.4/preset.xml
new file mode 100644
index 000000000..efbdce2fc
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.4/preset.xml
@@ -0,0 +1,402 @@
+
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diff --git a/boards/Xilinx/kcu116/1.4/xitem.json b/boards/Xilinx/kcu116/1.4/xitem.json
new file mode 100644
index 000000000..a68408e56
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kcu116",
+ "display": "Kintex UltraScale+ KCU116 Evaluation Platform",
+ "revision": "1.4",
+ "description": "Kintex UltraScale+ KCU116 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "kcu116_board.jpeg",
+ "website": "www.xilinx.com/kcu116",
+ "search-keywords": [
+ "kcu116",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kcu116/1.5/LICENSE b/boards/Xilinx/kcu116/1.5/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.5/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kcu116/1.5/board.xml b/boards/Xilinx/kcu116/1.5/board.xml
new file mode 100644
index 000000000..58e24726d
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.5/board.xml
@@ -0,0 +1,1353 @@
+
+
+
+
+
+
+ KCU116 Board File Image
+
+
+
+ 1.0
+
+ 1.5
+ Kintex UltraScale+ KCU116 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Kintex-UltraScale+ FPGA part on the board
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4Gb DDR4 SDRAM memory C1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ USer SMA clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ I2C
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY RESET OUT
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
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+
diff --git a/boards/Xilinx/kcu116/1.5/changelog.txt b/boards/Xilinx/kcu116/1.5/changelog.txt
new file mode 100644
index 000000000..daf36284f
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.5/changelog.txt
@@ -0,0 +1,21 @@
+######### KCU116 change log ############
+1.5
+Added new DDR4 Memory part MT40A256M16LY-062E support
+1.4
+Added GT locations for XDMA IP
+Updated IOSTANDARD constraints for sysclk_125_p/n from LVDS to LVDS_25
+Enabled support for pcie4_uscale_plus IP
+Removed 125 Mhz system clock since correponding pins were part of HD IO bank
+
+1.3
+Enabled FMC Support in 2017.4
+
+1.2
+Avoiding upper case attributes
+
+1.1
+Enabled SGMII over LVDS support
+
+1.0
+KCU116 production board support
+
diff --git a/boards/Xilinx/kcu116/1.5/kcu116_board.jpeg b/boards/Xilinx/kcu116/1.5/kcu116_board.jpeg
new file mode 100644
index 000000000..1ee8f6451
Binary files /dev/null and b/boards/Xilinx/kcu116/1.5/kcu116_board.jpeg differ
diff --git a/boards/Xilinx/kcu116/1.5/part0_pins.xml b/boards/Xilinx/kcu116/1.5/part0_pins.xml
new file mode 100644
index 000000000..c73e2b5cc
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.5/part0_pins.xml
@@ -0,0 +1,301 @@
+
+
+
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diff --git a/boards/Xilinx/kcu116/1.5/preset.xml b/boards/Xilinx/kcu116/1.5/preset.xml
new file mode 100644
index 000000000..081f27ca4
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.5/preset.xml
@@ -0,0 +1,415 @@
+
+
+
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+
diff --git a/boards/Xilinx/kcu116/1.5/xitem.json b/boards/Xilinx/kcu116/1.5/xitem.json
new file mode 100644
index 000000000..25361cce1
--- /dev/null
+++ b/boards/Xilinx/kcu116/1.5/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kcu116",
+ "display": "Kintex UltraScale+ KCU116 Evaluation Platform",
+ "revision": "1.5",
+ "description": "Kintex UltraScale+ KCU116 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "kcu116_board.jpeg",
+ "website": "www.xilinx.com/kcu116",
+ "search-keywords": [
+ "kcu116",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kcu1500/1.2/LICENSE b/boards/Xilinx/kcu1500/1.2/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/kcu1500/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kcu1500/1.2/board.xml b/boards/Xilinx/kcu1500/1.2/board.xml
new file mode 100644
index 000000000..aeeac853f
--- /dev/null
+++ b/boards/Xilinx/kcu1500/1.2/board.xml
@@ -0,0 +1,1648 @@
+
+
+
+
+
+
+ Xilinx Developer Board for Acceleration with Kintex UltraScale KU115
+
+
+
+
+ 1.0
+
+
+ 1.2
+
+ Kintex UltraScale KCU1500 Acceleration Development Board
+
+
+
+
+
+
+
+
+
+
+
+ Kintex UltraScale KU115 FPGA
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
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+ System Monitor Interface
+
+
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+
+
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+
+
+
+ I2C
+
+
+
+ CPU Reset Push Button, Active Low
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Dip Switches 3 to 0
+
+
+
+
+ 4GB DDR4 SDRAM memory C0
+
+
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+ 4GB DDR4 SDRAM memory C1
+
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+ 4GB DDR4 SDRAM memory C2
+
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+
+ 4GB DDR4 SDRAM memory C3
+
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+ PCI Express
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+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
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diff --git a/boards/Xilinx/kcu1500/1.2/changelog.txt b/boards/Xilinx/kcu1500/1.2/changelog.txt
new file mode 100644
index 000000000..caef26d5b
--- /dev/null
+++ b/boards/Xilinx/kcu1500/1.2/changelog.txt
@@ -0,0 +1,17 @@
+######### KCU1500 change log ##############
+1.2
+Added GT location for XDMA IP
+
+2018.3 Updates
+Enabled System monitor board support
+
+2018.1 Updates
+DDR4 controller size parameter modified
+SLR parameter added for DDR4 components
+
+1.1
+Avoiding upper case attributes
+
+1.0
+KCU1500 initial board support
+
diff --git a/boards/Xilinx/kcu1500/1.2/kcu1500_board.png b/boards/Xilinx/kcu1500/1.2/kcu1500_board.png
new file mode 100644
index 000000000..1d7005953
Binary files /dev/null and b/boards/Xilinx/kcu1500/1.2/kcu1500_board.png differ
diff --git a/boards/Xilinx/kcu1500/1.2/part0_pins.xml b/boards/Xilinx/kcu1500/1.2/part0_pins.xml
new file mode 100644
index 000000000..a763d417b
--- /dev/null
+++ b/boards/Xilinx/kcu1500/1.2/part0_pins.xml
@@ -0,0 +1,602 @@
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diff --git a/boards/Xilinx/kcu1500/1.2/preset.xml b/boards/Xilinx/kcu1500/1.2/preset.xml
new file mode 100644
index 000000000..4511b30ec
--- /dev/null
+++ b/boards/Xilinx/kcu1500/1.2/preset.xml
@@ -0,0 +1,365 @@
+
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diff --git a/boards/Xilinx/kcu1500/1.2/xitem.json b/boards/Xilinx/kcu1500/1.2/xitem.json
new file mode 100644
index 000000000..a62c72297
--- /dev/null
+++ b/boards/Xilinx/kcu1500/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kcu1500",
+ "display": "Kintex UltraScale KCU1500 Acceleration Development Board",
+ "revision": "1.2",
+ "description": "Kintex UltraScale KCU1500 Acceleration Development Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "kcu1500_board.png",
+ "website": "https://www.xilinx.com/products/boards-and-kits/dk-u1-kcu1500-g.html",
+ "search-keywords": [
+ "KCU1500",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kd240_carrier/1.0/LICENSE b/boards/Xilinx/kd240_carrier/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kd240_carrier/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kd240_carrier/1.0/board.xml b/boards/Xilinx/kd240_carrier/1.0/board.xml
new file mode 100644
index 000000000..f138a38b9
--- /dev/null
+++ b/boards/Xilinx/kd240_carrier/1.0/board.xml
@@ -0,0 +1,1409 @@
+
+
+
+
+ 1.0
+
+ Drives Starter Kit Carrier
+
+
+ Rev_A1
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+ Primary interface to communicate with Ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
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+
+
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+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as RGMII.
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Quadrature Encoder
+
+
+
+ Motor Control
+
+
+
+ Brake Control
+
+
+
+ Temperature Sensor gpio
+
+
+
+ Motor ADC gpio
+
+
+
+
+
+ LEDs 1 to 0
+
+
+
+
+
+ LEDs 1 to 0
+
+
+
+ LEDs 1 to 0
+
+
+
+ I2C channel for One 64kb EEPROM
+
+
+
+ Torque Sensor Connector
+
+
+
+ DC Link Voltage and Current ADCs
+
+
+
+
+ PL RGMII1 on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL RGMII1 on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PMOD Connector
+
+
+
+
+
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+
diff --git a/boards/Xilinx/kd240_carrier/1.0/changelog.txt b/boards/Xilinx/kd240_carrier/1.0/changelog.txt
new file mode 100644
index 000000000..2fe0c1dbf
--- /dev/null
+++ b/boards/Xilinx/kd240_carrier/1.0/changelog.txt
@@ -0,0 +1,3 @@
+######### KD240 Starter Kit Carrier card changelog ############
+1.0 (2023.1_kria_update1)
+Initial release
diff --git a/boards/Xilinx/kd240_carrier/1.0/preset.xml b/boards/Xilinx/kd240_carrier/1.0/preset.xml
new file mode 100644
index 000000000..4aac27a23
--- /dev/null
+++ b/boards/Xilinx/kd240_carrier/1.0/preset.xml
@@ -0,0 +1,308 @@
+
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+
+
diff --git a/boards/Xilinx/kd240_carrier/1.0/xitem.json b/boards/Xilinx/kd240_carrier/1.0/xitem.json
new file mode 100644
index 000000000..d8549165d
--- /dev/null
+++ b/boards/Xilinx/kd240_carrier/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kd240_carrier",
+ "display": "Drives Starter Kit carrier card",
+ "revision": "1.0",
+ "description": "Drives Starter Kit carrier card",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "dsom_kit.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kd240_som/1.0/LICENSE b/boards/Xilinx/kd240_som/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kd240_som/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kd240_som/1.0/board.xml b/boards/Xilinx/kd240_som/1.0/board.xml
new file mode 100644
index 000000000..12baebe3a
--- /dev/null
+++ b/boards/Xilinx/kd240_som/1.0/board.xml
@@ -0,0 +1,483 @@
+
+
+
+
+
+
+
+ Kria KD240 Drives Starter Kit Board Image
+
+
+
+
+ Rev_A01
+
+
+ 1.0
+
+ Kria KD240 Drives Starter Kit SOM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kd240_som/1.0/changelog.txt b/boards/Xilinx/kd240_som/1.0/changelog.txt
new file mode 100644
index 000000000..bc79ef6b3
--- /dev/null
+++ b/boards/Xilinx/kd240_som/1.0/changelog.txt
@@ -0,0 +1,3 @@
+######### KD240 SOM changelog ############
+1.0 (2023.1_kria_update1)
+Initial release
\ No newline at end of file
diff --git a/boards/Xilinx/kd240_som/1.0/kd240_board.png b/boards/Xilinx/kd240_som/1.0/kd240_board.png
new file mode 100644
index 000000000..7461001c8
Binary files /dev/null and b/boards/Xilinx/kd240_som/1.0/kd240_board.png differ
diff --git a/boards/Xilinx/kd240_som/1.0/part0_pins.xml b/boards/Xilinx/kd240_som/1.0/part0_pins.xml
new file mode 100644
index 000000000..9f5495d0c
--- /dev/null
+++ b/boards/Xilinx/kd240_som/1.0/part0_pins.xml
@@ -0,0 +1,103 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/Xilinx/kd240_som/1.0/preset.xml b/boards/Xilinx/kd240_som/1.0/preset.xml
new file mode 100644
index 000000000..6311fab53
--- /dev/null
+++ b/boards/Xilinx/kd240_som/1.0/preset.xml
@@ -0,0 +1,413 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kd240_som/1.0/xitem.json b/boards/Xilinx/kd240_som/1.0/xitem.json
new file mode 100644
index 000000000..da3c3fa03
--- /dev/null
+++ b/boards/Xilinx/kd240_som/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kd240_som",
+ "display": "Kria KD240 Drives Starter Kit SOM",
+ "revision": "1.0",
+ "description": "Kria KD240 Drives Starter Kit SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "skmeidi",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "kd240_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kr260_carrier/1.0/LICENSE b/boards/Xilinx/kr260_carrier/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kr260_carrier/1.0/board.xml b/boards/Xilinx/kr260_carrier/1.0/board.xml
new file mode 100644
index 000000000..e3cd38f0a
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.0/board.xml
@@ -0,0 +1,2200 @@
+
+
+
+
+ 1.0
+
+ Robotics Starter Kit Carrier
+
+
+ Rev A02
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as RGMII.
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ PL RGMII2 on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL RGMII3 on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PMOD Connector PMOD1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PMOD Connector PMOD2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3.3V LVCMOS Si5332 programmable oscillator used as clock on the board
+
+
+
+ LEDs 2 to 0
+
+
+
+ 3.3V LVCMOS Si5332 programmable oscillator used as clock on the board
+
+
+
+ LEDs 2 to 0
+
+
+
+ LEDs 1 to 0
+
+
+
+ LEDs 1 to 0
+
+
+
+
+
+
+
+ PMOD Connector PMOD3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PMOD Connector PMOD4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ I2C channel for MSP430 and Switch
+
+
+
+ I2C channel for MSP430 and Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
diff --git a/boards/Xilinx/kr260_carrier/1.0/changelog.txt b/boards/Xilinx/kr260_carrier/1.0/changelog.txt
new file mode 100644
index 000000000..b5746c780
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.0/changelog.txt
@@ -0,0 +1,3 @@
+######### Robotics Carrier card changelog ############
+1.0 (2022.1)
+Initial release
diff --git a/boards/Xilinx/kr260_carrier/1.0/preset.xml b/boards/Xilinx/kr260_carrier/1.0/preset.xml
new file mode 100644
index 000000000..ed417ef9f
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.0/preset.xml
@@ -0,0 +1,349 @@
+
+
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+
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+
diff --git a/boards/Xilinx/kr260_carrier/1.0/xitem.json b/boards/Xilinx/kr260_carrier/1.0/xitem.json
new file mode 100644
index 000000000..db0fcbe31
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kr260",
+ "display": "Robotics Starter Kit carrier card",
+ "revision": "1.0",
+ "description": "Robotics Starter Kit carrier card",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "rsom_kit.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kr260_carrier/1.1/LICENSE b/boards/Xilinx/kr260_carrier/1.1/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kr260_carrier/1.1/board.xml b/boards/Xilinx/kr260_carrier/1.1/board.xml
new file mode 100644
index 000000000..da70b41c9
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.1/board.xml
@@ -0,0 +1,1880 @@
+
+
+
+
+ 1.1
+
+ Robotics Starter Kit Carrier
+
+
+ Rev A02
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as RGMII.
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL RGMII2 on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL RGMII3 on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PMOD Connector PMOD1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PMOD Connector PMOD2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3.3V LVCMOS Si5332 programmable oscillator used as clock on the board
+
+
+
+ LEDs 2 to 0
+
+
+
+ 3.3V LVCMOS Si5332 programmable oscillator used as clock on the board
+
+
+
+ LEDs 2 to 0
+
+
+
+ LEDs 1 to 0
+
+
+
+ LEDs 1 to 0
+
+
+
+
+
+
+
+ PMOD Connector PMOD3
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PMOD Connector PMOD4
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ I2C channel for MSP430 and Switch
+
+
+
+ I2C channel for MSP430 and Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kr260_carrier/1.1/changelog.txt b/boards/Xilinx/kr260_carrier/1.1/changelog.txt
new file mode 100644
index 000000000..b1b040b3b
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.1/changelog.txt
@@ -0,0 +1,8 @@
+######### Robotics Carrier card changelog ############
+1.1(2024.1)
+Updated PMOD GPIO interfaces and added pmod_gpio_preset.
+
+1.0 (2022.1)
+Initial release
+
+
diff --git a/boards/Xilinx/kr260_carrier/1.1/preset.xml b/boards/Xilinx/kr260_carrier/1.1/preset.xml
new file mode 100644
index 000000000..6f85374a0
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.1/preset.xml
@@ -0,0 +1,361 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
diff --git a/boards/Xilinx/kr260_carrier/1.1/xitem.json b/boards/Xilinx/kr260_carrier/1.1/xitem.json
new file mode 100644
index 000000000..605cc30a0
--- /dev/null
+++ b/boards/Xilinx/kr260_carrier/1.1/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kr260",
+ "display": "Robotics Starter Kit carrier card",
+ "revision": "1.1",
+ "description": "Robotics Starter Kit carrier card",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "rsom_kit.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kr260_som/1.0/LICENSE b/boards/Xilinx/kr260_som/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kr260_som/1.0/board.xml b/boards/Xilinx/kr260_som/1.0/board.xml
new file mode 100644
index 000000000..12d400442
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.0/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria KR260 Robotics Board File Image
+
+
+
+
+ Rev_B01
+
+
+ 1.0
+
+ Kria KR260 Robotics Starter Kit SOM
+
+
+
+
+
+
+
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+ FPGA part on the board
+
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diff --git a/boards/Xilinx/kr260_som/1.0/changelog.txt b/boards/Xilinx/kr260_som/1.0/changelog.txt
new file mode 100644
index 000000000..9e0417492
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.0/changelog.txt
@@ -0,0 +1,3 @@
+######### Vision SOM changelog ############
+1.0 (2022.1)
+Initial release
\ No newline at end of file
diff --git a/boards/Xilinx/kr260_som/1.0/kr260_board.png b/boards/Xilinx/kr260_som/1.0/kr260_board.png
new file mode 100644
index 000000000..01f2d64d9
Binary files /dev/null and b/boards/Xilinx/kr260_som/1.0/kr260_board.png differ
diff --git a/boards/Xilinx/kr260_som/1.0/part0_pins.xml b/boards/Xilinx/kr260_som/1.0/part0_pins.xml
new file mode 100644
index 000000000..75bc02d01
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.0/part0_pins.xml
@@ -0,0 +1,231 @@
+
+
+
+
+
+
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+
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+
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+
+
\ No newline at end of file
diff --git a/boards/Xilinx/kr260_som/1.0/preset.xml b/boards/Xilinx/kr260_som/1.0/preset.xml
new file mode 100644
index 000000000..8e9bb2319
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.0/preset.xml
@@ -0,0 +1,394 @@
+
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+
diff --git a/boards/Xilinx/kr260_som/1.0/xitem.json b/boards/Xilinx/kr260_som/1.0/xitem.json
new file mode 100644
index 000000000..bb9013e3b
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kr260_som",
+ "display": "Kria KR260 Robotics Starter Kit SOM",
+ "revision": "1.0",
+ "description": "Kria KR260 Robotics Starter Kit SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "kr260_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kr260_som/1.1/LICENSE b/boards/Xilinx/kr260_som/1.1/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kr260_som/1.1/board.xml b/boards/Xilinx/kr260_som/1.1/board.xml
new file mode 100644
index 000000000..b08e11959
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.1/board.xml
@@ -0,0 +1,870 @@
+
+
+
+
+
+
+
+
+ Kria KR260 Robotics Board File Image
+
+
+
+
+ Rev_B01
+
+
+ 1.1
+
+ Kria KR260 Robotics Starter Kit SOM
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+ FPGA part on the board
+
+
+
+
+
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diff --git a/boards/Xilinx/kr260_som/1.1/changelog.txt b/boards/Xilinx/kr260_som/1.1/changelog.txt
new file mode 100644
index 000000000..1126a3bbe
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.1/changelog.txt
@@ -0,0 +1,6 @@
+######### Vision SOM changelog ############
+1.1(2022.2)
+PMU GIOs (MIO32, MIO33, MIO34) Disabled
+
+1.0 (2022.1)
+Initial release
\ No newline at end of file
diff --git a/boards/Xilinx/kr260_som/1.1/kr260_board.png b/boards/Xilinx/kr260_som/1.1/kr260_board.png
new file mode 100644
index 000000000..01f2d64d9
Binary files /dev/null and b/boards/Xilinx/kr260_som/1.1/kr260_board.png differ
diff --git a/boards/Xilinx/kr260_som/1.1/part0_pins.xml b/boards/Xilinx/kr260_som/1.1/part0_pins.xml
new file mode 100644
index 000000000..75bc02d01
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.1/part0_pins.xml
@@ -0,0 +1,231 @@
+
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\ No newline at end of file
diff --git a/boards/Xilinx/kr260_som/1.1/preset.xml b/boards/Xilinx/kr260_som/1.1/preset.xml
new file mode 100644
index 000000000..80e0b58db
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.1/preset.xml
@@ -0,0 +1,394 @@
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diff --git a/boards/Xilinx/kr260_som/1.1/xitem.json b/boards/Xilinx/kr260_som/1.1/xitem.json
new file mode 100644
index 000000000..8b0ee966f
--- /dev/null
+++ b/boards/Xilinx/kr260_som/1.1/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kr260_som",
+ "display": "Kria KR260 Robotics Starter Kit SOM",
+ "revision": "1.1",
+ "description": "Kria KR260 Robotics Starter Kit SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "kr260_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kv260_carrier/1.2/LICENSE b/boards/Xilinx/kv260_carrier/1.2/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kv260_carrier/1.2/board.xml b/boards/Xilinx/kv260_carrier/1.2/board.xml
new file mode 100644
index 000000000..940d7c194
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.2/board.xml
@@ -0,0 +1,597 @@
+
+
+
+
+
+ 1.2
+
+ Vision AI Starter Kit carrier card
+
+
+ Rev A
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+ AXI IIC connected to HDA IIC SWITCH on AI Vision Starter Kit carrier card
+
+
+
+ MIPI CSI-2 Rx Subsystem to connect to RASPBERRY PI CONNECTOR on AI Vision Starter Kit carrier card
+
+
+
+ MIPI CSI-2 Rx Subsystem to connect to IAS direct IAS1 connector on AI Vision Starter Kit.
+
+
+
+ MIPI CSI-2 Rx Subsystem to connect to AP1302 ISP and IAS0 connector on AI Vision Starter Kit.
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/kv260_carrier/1.2/changelog.txt b/boards/Xilinx/kv260_carrier/1.2/changelog.txt
new file mode 100644
index 000000000..ea931e79e
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.2/changelog.txt
@@ -0,0 +1,10 @@
+######### Vision SOM changelog ############
+1.2(2021.2)
+Updated naming from som240 to kv260_carrier.
+1.1 is deprecated as there is name change.
+
+1.1(2021.1)
+Initial release for public
+
+1.0(2020.2.2_web)
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/kv260_carrier/1.2/preset.xml b/boards/Xilinx/kv260_carrier/1.2/preset.xml
new file mode 100644
index 000000000..38e0b33a7
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.2/preset.xml
@@ -0,0 +1,213 @@
+
+
+
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+
diff --git a/boards/Xilinx/kv260_carrier/1.2/xitem.json b/boards/Xilinx/kv260_carrier/1.2/xitem.json
new file mode 100644
index 000000000..202d68489
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kv260_carrier",
+ "display": "Vision AI Starter Kit carrier card",
+ "revision": "1.2",
+ "description": "Vision AI Starter Kit carrier card",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "vsom_kit.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kv260_carrier/1.3/LICENSE b/boards/Xilinx/kv260_carrier/1.3/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kv260_carrier/1.3/board.xml b/boards/Xilinx/kv260_carrier/1.3/board.xml
new file mode 100644
index 000000000..d846c5ca7
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.3/board.xml
@@ -0,0 +1,597 @@
+
+
+
+
+
+ 1.3
+
+ Vision AI Starter Kit carrier card
+
+
+ Rev_B01
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ AXI IIC connected to HDA IIC SWITCH on AI Vision Starter Kit carrier card
+
+
+
+ MIPI CSI-2 Rx Subsystem to connect to RASPBERRY PI CONNECTOR on AI Vision Starter Kit carrier card
+
+
+
+ MIPI CSI-2 Rx Subsystem to connect to IAS direct IAS1 connector on AI Vision Starter Kit.
+
+
+
+ MIPI CSI-2 Rx Subsystem to connect to AP1302 ISP and IAS0 connector on AI Vision Starter Kit.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/boards/Xilinx/kv260_carrier/1.3/changelog.txt b/boards/Xilinx/kv260_carrier/1.3/changelog.txt
new file mode 100644
index 000000000..42b98205c
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.3/changelog.txt
@@ -0,0 +1,13 @@
+######### Vision SOM changelog ############
+1.3(2022.1)
+Updated clock hierarchy
+
+1.2(2021.2)
+Updated naming from som240 to kv260_carrier.
+1.1 is deprecated as there is name change.
+
+1.1(2021.1)
+Initial release for public
+
+1.0(2020.2.2_web)
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/kv260_carrier/1.3/preset.xml b/boards/Xilinx/kv260_carrier/1.3/preset.xml
new file mode 100644
index 000000000..a997cc709
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.3/preset.xml
@@ -0,0 +1,234 @@
+
+
+
+
+
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+
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+
diff --git a/boards/Xilinx/kv260_carrier/1.3/xitem.json b/boards/Xilinx/kv260_carrier/1.3/xitem.json
new file mode 100644
index 000000000..3d294f7d0
--- /dev/null
+++ b/boards/Xilinx/kv260_carrier/1.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kv260_carrier",
+ "display": "Vision AI Starter Kit carrier card",
+ "revision": "1.3",
+ "description": "Vision AI Starter Kit carrier card",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "vsom_kit.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kv260_som/1.2/LICENSE b/boards/Xilinx/kv260_som/1.2/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kv260_som/1.2/board.xml b/boards/Xilinx/kv260_som/1.2/board.xml
new file mode 100644
index 000000000..6eeee2490
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.2/board.xml
@@ -0,0 +1,374 @@
+
+
+
+
+
+
+
+
+ Kria KV260 Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.2
+
+ Kria KV260 Vision AI starter Kit
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kv260_som/1.2/changelog.txt b/boards/Xilinx/kv260_som/1.2/changelog.txt
new file mode 100644
index 000000000..b633f1d23
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.2/changelog.txt
@@ -0,0 +1,10 @@
+######### Vision SOM changelog ############
+1.2(2021.2)
+Updated naming from kv260 to kv260_som.
+1.1 is deprecated as there is name change.
+
+1.1(2021.1)
+Initial release for public
+
+1.0(2020.2.2_web)
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/kv260_som/1.2/part0_pins.xml b/boards/Xilinx/kv260_som/1.2/part0_pins.xml
new file mode 100644
index 000000000..ca178c68f
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.2/part0_pins.xml
@@ -0,0 +1,67 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/Xilinx/kv260_som/1.2/preset_s4.xml b/boards/Xilinx/kv260_som/1.2/preset_s4.xml
new file mode 100644
index 000000000..1f9a40c13
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.2/preset_s4.xml
@@ -0,0 +1,361 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
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+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
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+
+
+
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+
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+
+
+
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+
+
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+
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+
+
diff --git a/boards/Xilinx/kv260_som/1.2/vsom_kit.jpg b/boards/Xilinx/kv260_som/1.2/vsom_kit.jpg
new file mode 100644
index 000000000..191de8072
Binary files /dev/null and b/boards/Xilinx/kv260_som/1.2/vsom_kit.jpg differ
diff --git a/boards/Xilinx/kv260_som/1.2/xitem.json b/boards/Xilinx/kv260_som/1.2/xitem.json
new file mode 100644
index 000000000..90afee81e
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kv260_som",
+ "display": "Kria KV260 Vision AI Starter Kit SOM",
+ "revision": "1.2",
+ "description": "Kria KV260 Vision AI Starter Kit SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "vsom_kit.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kv260_som/1.3/LICENSE b/boards/Xilinx/kv260_som/1.3/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kv260_som/1.3/board.xml b/boards/Xilinx/kv260_som/1.3/board.xml
new file mode 100644
index 000000000..ed7756441
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.3/board.xml
@@ -0,0 +1,374 @@
+
+
+
+
+
+
+
+
+ Kria KV260 Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.3
+
+ Kria KV260 Vision AI starter Kit SOM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/kv260_som/1.3/changelog.txt b/boards/Xilinx/kv260_som/1.3/changelog.txt
new file mode 100644
index 000000000..79ea284d3
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.3/changelog.txt
@@ -0,0 +1,13 @@
+######### Vision SOM changelog ############
+1.3(2022.1)
+Updated clock hierarchy
+
+1.2(2021.2)
+Updated naming from kv260 to kv260_som.
+1.1 is deprecated as there is name change.
+
+1.1(2021.1)
+Initial release for public
+
+1.0(2020.2.2_web)
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/kv260_som/1.3/part0_pins.xml b/boards/Xilinx/kv260_som/1.3/part0_pins.xml
new file mode 100644
index 000000000..ca178c68f
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.3/part0_pins.xml
@@ -0,0 +1,67 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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\ No newline at end of file
diff --git a/boards/Xilinx/kv260_som/1.3/preset_s4.xml b/boards/Xilinx/kv260_som/1.3/preset_s4.xml
new file mode 100644
index 000000000..a47eefe27
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.3/preset_s4.xml
@@ -0,0 +1,340 @@
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diff --git a/boards/Xilinx/kv260_som/1.3/vsom_kit.jpg b/boards/Xilinx/kv260_som/1.3/vsom_kit.jpg
new file mode 100644
index 000000000..191de8072
Binary files /dev/null and b/boards/Xilinx/kv260_som/1.3/vsom_kit.jpg differ
diff --git a/boards/Xilinx/kv260_som/1.3/xitem.json b/boards/Xilinx/kv260_som/1.3/xitem.json
new file mode 100644
index 000000000..a39f575d3
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kv260_som",
+ "display": "Kria KV260 Vision AI Starter Kit SOM",
+ "revision": "1.3",
+ "description": "Kria KV260 Vision AI Starter Kit SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "vsom_kit.jpeg",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/kv260_som/1.4/LICENSE b/boards/Xilinx/kv260_som/1.4/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/kv260_som/1.4/board.xml b/boards/Xilinx/kv260_som/1.4/board.xml
new file mode 100644
index 000000000..0455d7834
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.4/board.xml
@@ -0,0 +1,374 @@
+
+
+
+
+
+
+
+
+ Kria KV260 Vision AI starter Kit
+
+
+
+
+ Rev_B01
+
+
+ 1.4
+
+ Kria KV260 Vision AI starter Kit SOM
+
+
+
+
+
+
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+
+
+ FPGA part on the board
+
+
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+
diff --git a/boards/Xilinx/kv260_som/1.4/changelog.txt b/boards/Xilinx/kv260_som/1.4/changelog.txt
new file mode 100644
index 000000000..0e3f0530b
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.4/changelog.txt
@@ -0,0 +1,16 @@
+######### Vision SOM changelog ############
+1.4(2022.2)
+PMU GIOs (MIO32, MIO33, MIO34) Disabled.
+
+1.3(2022.1)
+Updated clock hierarchy
+
+1.2(2021.2)
+Updated naming from kv260 to kv260_som.
+1.1 is deprecated as there is name change.
+
+1.1(2021.1)
+Initial release for public
+
+1.0(2020.2.2_web)
+Initial release with lounge
\ No newline at end of file
diff --git a/boards/Xilinx/kv260_som/1.4/kv260_board.png b/boards/Xilinx/kv260_som/1.4/kv260_board.png
new file mode 100644
index 000000000..2d72edbb7
Binary files /dev/null and b/boards/Xilinx/kv260_som/1.4/kv260_board.png differ
diff --git a/boards/Xilinx/kv260_som/1.4/part0_pins.xml b/boards/Xilinx/kv260_som/1.4/part0_pins.xml
new file mode 100644
index 000000000..ca178c68f
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.4/part0_pins.xml
@@ -0,0 +1,67 @@
+
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+
+
\ No newline at end of file
diff --git a/boards/Xilinx/kv260_som/1.4/preset_s4.xml b/boards/Xilinx/kv260_som/1.4/preset_s4.xml
new file mode 100644
index 000000000..b0f00a250
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.4/preset_s4.xml
@@ -0,0 +1,340 @@
+
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diff --git a/boards/Xilinx/kv260_som/1.4/xitem.json b/boards/Xilinx/kv260_som/1.4/xitem.json
new file mode 100644
index 000000000..ab6f3db97
--- /dev/null
+++ b/boards/Xilinx/kv260_som/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "kv260_som",
+ "display": "Kria KV260 Vision AI Starter Kit SOM",
+ "revision": "1.4",
+ "description": "Kria KV260 Vision AI Starter Kit SOM",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "System On Modules(SOM)",
+ "logo": "kv260_board.png",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "SOM",
+ "xilinx.com",
+ "board",
+ "System On Modules(SOM)"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/li-imx274-mipi-versal/1.0/LICENSE b/boards/Xilinx/li-imx274-mipi-versal/1.0/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi-versal/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/li-imx274-mipi-versal/1.0/board.xml b/boards/Xilinx/li-imx274-mipi-versal/1.0/board.xml
new file mode 100755
index 000000000..3944b1b28
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi-versal/1.0/board.xml
@@ -0,0 +1,693 @@
+
+
+
+
+
+
+ 1.0
+
+
+ 1.0
+
+ To connect LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only with MIPI CSI-2 Rx Subsystem, MIPI DSI Tx Subsystem and other control blocks like IIC,GPIO
+
+
+
+
+ MIPI CSI-2 Rx Subsystem to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ MIPI DSI Tx Subsystem to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+
+
+
+
+
+ AXI IIC(camera IIC/CCI) to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+
+ Camera control signals through AXI GPIO to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+
+ Display control signals through AXI GPIO to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/li-imx274-mipi-versal/1.0/preset.xml b/boards/Xilinx/li-imx274-mipi-versal/1.0/preset.xml
new file mode 100755
index 000000000..b18f82d66
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi-versal/1.0/preset.xml
@@ -0,0 +1,249 @@
+
+
+
+
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diff --git a/boards/Xilinx/li-imx274-mipi-versal/1.0/xitem.json b/boards/Xilinx/li-imx274-mipi-versal/1.0/xitem.json
new file mode 100755
index 000000000..5ef42cdc8
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi-versal/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "LI-IMX274MIPI-FMC-Versal",
+ "display": "LI-IMX274MIPI-FMC Versal",
+ "revision": "1.0",
+ "description": "LI-IMX274MIPI-FMC Versal",
+ "company": "Leopardimaging",
+ "company_display": "Leopardimaging",
+ "author": "KondalRao",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "FMCs & Accessories",
+ "logo": "",
+ "website": "https://leopardimaging.com/product/li-imx274mipi-fmc/",
+ "search-keywords": [
+ "FMC",
+ "xilinx.com",
+ "board",
+ "LI-IMX274MIPI-FMC-Versal"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/li-imx274-mipi/1.0/LICENSE b/boards/Xilinx/li-imx274-mipi/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/li-imx274-mipi/1.0/board.xml b/boards/Xilinx/li-imx274-mipi/1.0/board.xml
new file mode 100644
index 000000000..20f075878
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi/1.0/board.xml
@@ -0,0 +1,654 @@
+
+
+
+
+ 1.0
+
+ 1.0
+ To connect LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only with MIPI CSI-2 Rx Subsystem, MIPI DSI Tx Subsystem and other control blocks like IIC,GPIO
+
+
+ MIPI CSI-2 Rx Subsystem to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ MIPI DSI Tx Subsystem to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+ AXI IIC(camera IIC/CCI) to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+ Camera control signals through AXI GPIO to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+ Display control signals through AXI GPIO to connect to LI-IMX274MIPI-FMC V1.0 FMC placed on ZCU102 HPC0 FMC Slot only
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/li-imx274-mipi/1.0/preset.xml b/boards/Xilinx/li-imx274-mipi/1.0/preset.xml
new file mode 100644
index 000000000..3b305aeff
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi/1.0/preset.xml
@@ -0,0 +1,238 @@
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
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+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
diff --git a/boards/Xilinx/li-imx274-mipi/1.0/xitem.json b/boards/Xilinx/li-imx274-mipi/1.0/xitem.json
new file mode 100644
index 000000000..e5a6e1f08
--- /dev/null
+++ b/boards/Xilinx/li-imx274-mipi/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "LI-IMX274MIPI-FMC",
+ "display": "LI-IMX274MIPI-FMC V1.0",
+ "revision": "1.0",
+ "description": "LI-IMX274MIPI-FMC V1.0",
+ "company": "Leopardimaging",
+ "company_display": "Leopardimaging",
+ "author": "KondalRao",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "FMCs & Accessories",
+ "logo": "",
+ "website": "https://www.leopardimaging.com/product/csi-2-mipi-modules-i-pex/li-imx274mipi-fmc/",
+ "search-keywords": [
+ "FMC",
+ "xilinx.com",
+ "board",
+ "LI-IMX274MIPI-FMC"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/sp701/1.0/LICENSE b/boards/Xilinx/sp701/1.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/sp701/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/sp701/1.0/board.xml b/boards/Xilinx/sp701/1.0/board.xml
new file mode 100644
index 000000000..d85dd4911
--- /dev/null
+++ b/boards/Xilinx/sp701/1.0/board.xml
@@ -0,0 +1,636 @@
+
+
+
+
+
+
+ SP701 Board File Image
+
+
+
+ 1.0
+
+ 1.0
+ Spartan-7 SP701 Evaluation Platform
+
+
+
+
+ FPGA part on the board
+
+
+
+ DDR3 board interface, it can use MIG IP for connection.
+
+
+
+
+
+
+
+ 16-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GB DDR3 memory SODIMM
+
+
+
+
+
+
+
+ DIP Switches 15 to 0
+
+
+
+ LEDs 7 to 0
+
+
+
+
+ Ethernet 1 PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Ethernet 2 PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ethernet_1 MDIO
+
+
+
+ ethernet_2 MDIO
+
+
+
+ ethernet_1 PHY RESET OUT
+
+
+
+ ethernet_2 PHY RESET OUT
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
+
+
+
+ 256 MB of nonvolatile storage that can be used for configuration or data storage
+
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ I2C channel for MSP430 and Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/sp701/1.0/changelog.txt b/boards/Xilinx/sp701/1.0/changelog.txt
new file mode 100644
index 000000000..08540191b
--- /dev/null
+++ b/boards/Xilinx/sp701/1.0/changelog.txt
@@ -0,0 +1,5 @@
+######### SP701 Change log ##############
+
+1.0
+SP701 Initial Vivado Board Support(2018.3 web)
+
diff --git a/boards/Xilinx/sp701/1.0/mig.prj b/boards/Xilinx/sp701/1.0/mig.prj
new file mode 100644
index 000000000..5ee5ca125
--- /dev/null
+++ b/boards/Xilinx/sp701/1.0/mig.prj
@@ -0,0 +1,159 @@
+
+
+
+
+
+
+
+ design_1_mig_7series_0_1
+
+ 1
+
+ 1
+
+ OFF
+
+ 1024
+
+ ON
+
+ Enabled
+
+ xc7s100-fgga676/-2
+
+ 4.2
+
+ Differential
+
+ Use System Clock
+
+ ACTIVE LOW
+
+ FALSE
+
+ 1
+
+ 50 Ohms
+
+ 0
+
+
+ DDR3_SDRAM/Components/MT41K256M16XX-107
+ 2500
+ 1.8V
+ 4:1
+ 200
+ 1
+ 800
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 16
+ 1
+ 1
+ Disabled
+ Normal
+ 4
+ FALSE
+
+ 15
+ 10
+ 3
+ 1.35V
+ 536870912
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 6
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Disable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 5
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 29
+ 64
+ 4
+ 0
+
+
+
+
+
diff --git a/boards/Xilinx/sp701/1.0/part0_pins.xml b/boards/Xilinx/sp701/1.0/part0_pins.xml
new file mode 100644
index 000000000..76782d18f
--- /dev/null
+++ b/boards/Xilinx/sp701/1.0/part0_pins.xml
@@ -0,0 +1,99 @@
+
+
+
+
+
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+
+
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+
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diff --git a/boards/Xilinx/sp701/1.0/preset.xml b/boards/Xilinx/sp701/1.0/preset.xml
new file mode 100644
index 000000000..4dce88d85
--- /dev/null
+++ b/boards/Xilinx/sp701/1.0/preset.xml
@@ -0,0 +1,447 @@
+
+
+
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diff --git a/boards/Xilinx/sp701/1.0/sp701_board.jpg b/boards/Xilinx/sp701/1.0/sp701_board.jpg
new file mode 100644
index 000000000..99512639a
Binary files /dev/null and b/boards/Xilinx/sp701/1.0/sp701_board.jpg differ
diff --git a/boards/Xilinx/sp701/1.0/xitem.json b/boards/Xilinx/sp701/1.0/xitem.json
new file mode 100644
index 000000000..fef5c2a54
--- /dev/null
+++ b/boards/Xilinx/sp701/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "sp701",
+ "display": "Spartan-7 SP701 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Spartan-7 SP701 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "sp701_board.jpg",
+ "website": "http://www.xilinx.com/sp701",
+ "search-keywords": [
+ "SP701",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/sp701/1.1/LICENSE b/boards/Xilinx/sp701/1.1/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/sp701/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/sp701/1.1/board.xml b/boards/Xilinx/sp701/1.1/board.xml
new file mode 100644
index 000000000..aa6cc27c1
--- /dev/null
+++ b/boards/Xilinx/sp701/1.1/board.xml
@@ -0,0 +1,1435 @@
+
+
+
+
+
+
+ SP701 Board File Image
+
+
+
+ 1.0
+
+ 1.1
+ Spartan-7 SP701 Evaluation Platform
+
+
+
+
+ FPGA part on the board
+
+
+
+ DDR3 board interface, it can use MIG IP for connection.
+
+
+
+
+
+
+
+ 16-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in RGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
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+
+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GB DDR3 memory SODIMM
+
+
+
+
+
+
+
+ DIP Switches 15 to 0
+
+
+
+ LEDs 7 to 0
+
+
+
+
+ Ethernet 1 PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Ethernet 2 PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ ethernet_1 MDIO
+
+
+
+ ethernet_2 MDIO
+
+
+
+ ethernet_1 PHY RESET OUT
+
+
+
+ ethernet_2 PHY RESET OUT
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
+
+
+
+ 256 MB of nonvolatile storage that can be used for configuration or data storage
+
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ I2C channel for MSP430 and Switch
+
+
+
+ Pmod Connector PMOD1
+
+
+
+ Pmod Connector PMOD2
+
+
+
+ Pmod Connector PMOD3
+
+
+
+ Pmod Connector PMOD4
+
+
+
+ Pmod Connector PMOD5
+
+
+
+ Pmod Connector PMOD6
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/sp701/1.1/changelog.txt b/boards/Xilinx/sp701/1.1/changelog.txt
new file mode 100644
index 000000000..647a4e015
--- /dev/null
+++ b/boards/Xilinx/sp701/1.1/changelog.txt
@@ -0,0 +1,7 @@
+######### SP701 Change log ##############
+1.1
+Enabled Pmod Support(2021.1)
+
+1.0
+SP701 Initial Vivado Board Support(2018.3 web)
+
diff --git a/boards/Xilinx/sp701/1.1/mig.prj b/boards/Xilinx/sp701/1.1/mig.prj
new file mode 100644
index 000000000..5ee5ca125
--- /dev/null
+++ b/boards/Xilinx/sp701/1.1/mig.prj
@@ -0,0 +1,159 @@
+
+
+
+
+
+
+
+ design_1_mig_7series_0_1
+
+ 1
+
+ 1
+
+ OFF
+
+ 1024
+
+ ON
+
+ Enabled
+
+ xc7s100-fgga676/-2
+
+ 4.2
+
+ Differential
+
+ Use System Clock
+
+ ACTIVE LOW
+
+ FALSE
+
+ 1
+
+ 50 Ohms
+
+ 0
+
+
+ DDR3_SDRAM/Components/MT41K256M16XX-107
+ 2500
+ 1.8V
+ 4:1
+ 200
+ 1
+ 800
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 16
+ 1
+ 1
+ Disabled
+ Normal
+ 4
+ FALSE
+
+ 15
+ 10
+ 3
+ 1.35V
+ 536870912
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 6
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Disable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 5
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 29
+ 64
+ 4
+ 0
+
+
+
+
+
diff --git a/boards/Xilinx/sp701/1.1/part0_pins.xml b/boards/Xilinx/sp701/1.1/part0_pins.xml
new file mode 100644
index 000000000..50c29c172
--- /dev/null
+++ b/boards/Xilinx/sp701/1.1/part0_pins.xml
@@ -0,0 +1,153 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/sp701/1.1/preset.xml b/boards/Xilinx/sp701/1.1/preset.xml
new file mode 100644
index 000000000..4dce88d85
--- /dev/null
+++ b/boards/Xilinx/sp701/1.1/preset.xml
@@ -0,0 +1,447 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/sp701/1.1/sp701_board.jpg b/boards/Xilinx/sp701/1.1/sp701_board.jpg
new file mode 100644
index 000000000..99512639a
Binary files /dev/null and b/boards/Xilinx/sp701/1.1/sp701_board.jpg differ
diff --git a/boards/Xilinx/sp701/1.1/xitem.json b/boards/Xilinx/sp701/1.1/xitem.json
new file mode 100644
index 000000000..eccea54b8
--- /dev/null
+++ b/boards/Xilinx/sp701/1.1/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "sp701",
+ "display": "Spartan-7 SP701 Evaluation Platform",
+ "revision": "1.1",
+ "description": "Spartan-7 SP701 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "sp701_board.jpg",
+ "website": "http://www.xilinx.com/sp701",
+ "search-keywords": [
+ "SP701",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vc707/1.4/LICENSE b/boards/Xilinx/vc707/1.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vc707/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vc707/1.4/board.xml b/boards/Xilinx/vc707/1.4/board.xml
new file mode 100644
index 000000000..a8a6afa65
--- /dev/null
+++ b/boards/Xilinx/vc707/1.4/board.xml
@@ -0,0 +1,885 @@
+
+
+
+
+
+
+ VC707 Board File Image
+
+
+
+ 1.1
+
+ 1.4
+ Virtex-7 VC707 Evaluation Platform
+
+
+ FPGA part on the board
+
+
+ DDR3 board interface, it can use MIG IP for connection.
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as MII,GMII,1000BaseX.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GB DDR3 memory SODIMM
+
+
+
+
+
+
+ DIP Switches 7 to 0
+
+
+ I2C
+
+
+ LCD character display and connector
+
+
+ LEDs, 7 to 0, Active High
+
+
+ 1 GB BPI parallel NOR flash memory
+
+
+ PHY RESET OUT
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ CPU Reset Push Button, Active High
+
+
+ Edge Drive Jog Encoder Rotary Switch, INCB, PUSH, INCA, Active High
+
+
+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sfp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma in lvds mode
+
+
+
+
+
+
+
+
+
+
+
+
+ SGMII MGT Clock, 125 MHz
+
+
+ SMA MGT Clock, 125 MHz
+
+
+
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vc707/1.4/changelog.txt b/boards/Xilinx/vc707/1.4/changelog.txt
new file mode 100644
index 000000000..a535be50a
--- /dev/null
+++ b/boards/Xilinx/vc707/1.4/changelog.txt
@@ -0,0 +1,7 @@
+######### VC707 Change log ##############
+1.4
+Updated mig.prj to fix mrCasLatency and mr2CasLatency
+
+
+
+
diff --git a/boards/Xilinx/vc707/1.4/mig.prj b/boards/Xilinx/vc707/1.4/mig.prj
new file mode 100644
index 000000000..84e34002c
--- /dev/null
+++ b/boards/Xilinx/vc707/1.4/mig.prj
@@ -0,0 +1,223 @@
+
+
+
+ design_1_mig_7series_1_0
+
+ 1
+
+ 1
+
+ OFF
+
+ 1024
+
+ ON
+
+ Enabled
+
+ xc7vx485t-ffg1761/-2
+
+ 4.2
+
+ Differential
+
+ Use System Clock
+
+ ACTIVE HIGH
+
+ FALSE
+
+ 1
+
+ 50 Ohms
+
+ 0
+
+
+ DDR3_SDRAM/sodimms/MT8JTF12864HZ-1G6
+ 1250
+ 1.8V
+ 4:1
+ 200
+ 1
+ 800
+ 8.000
+ 16
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ 4
+ FALSE
+
+ 14
+ 10
+ 3
+ 1.5V
+ 1073741824
+ ROW_BANK_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/6
+ Disable
+ Enable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 1
+ 1
+
+
+
+
diff --git a/boards/Xilinx/vc707/1.4/part0_pins.xml b/boards/Xilinx/vc707/1.4/part0_pins.xml
new file mode 100644
index 000000000..582da3bde
--- /dev/null
+++ b/boards/Xilinx/vc707/1.4/part0_pins.xml
@@ -0,0 +1,123 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vc707/1.4/preset.xml b/boards/Xilinx/vc707/1.4/preset.xml
new file mode 100644
index 000000000..92a6aa1eb
--- /dev/null
+++ b/boards/Xilinx/vc707/1.4/preset.xml
@@ -0,0 +1,472 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vc707/1.4/vc707_board.jpg b/boards/Xilinx/vc707/1.4/vc707_board.jpg
new file mode 100644
index 000000000..d1e2f39f6
Binary files /dev/null and b/boards/Xilinx/vc707/1.4/vc707_board.jpg differ
diff --git a/boards/Xilinx/vc707/1.4/xitem.json b/boards/Xilinx/vc707/1.4/xitem.json
new file mode 100644
index 000000000..72fea3964
--- /dev/null
+++ b/boards/Xilinx/vc707/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vc707",
+ "display": "Virtex-7 VC707 Evaluation Platform",
+ "revision": "1.4",
+ "description": "Virtex-7 VC707 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vc707_board.jpg",
+ "website": "http://www.xilinx.com/vc707",
+ "search-keywords": [
+ "vc707",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vc709/1.8/LICENSE b/boards/Xilinx/vc709/1.8/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vc709/1.8/board.xml b/boards/Xilinx/vc709/1.8/board.xml
new file mode 100644
index 000000000..c6a36c3e2
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/board.xml
@@ -0,0 +1,1228 @@
+
+
+
+
+
+
+ VC709 Board File Image
+
+
+
+ 1.0
+
+ 1.8
+ Virtex-7 VC709 Evaluation Platform
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two DDR3 SODIMM memories (4 GB each)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DIP Switches 7 to 0
+
+
+ I2C
+
+
+ LEDs, 7 to 0, Active High
+
+
+ 128 MB of nonvolatile storage that can be used for configuration or software storage
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ CPU Reset Push Button, Active High
+
+
+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Small Form-factor Pluggable connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SFP MGT Clock 125 MHz
+
+
+ SMA MGT Clock 125 MHz
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+ 2.5V LVDS differential 233 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vc709/1.8/mig_j1.prj b/boards/Xilinx/vc709/1.8/mig_j1.prj
new file mode 100644
index 000000000..4fa83137f
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/mig_j1.prj
@@ -0,0 +1,206 @@
+
+
+
+ design_1_mig_7series_1_0
+ 1
+ 1
+ OFF
+ 1024
+ ON
+ Enabled
+ xc7vx690t-ffg1761/-2
+ 2.0
+ Differential
+ Use System Clock
+ ACTIVE HIGH
+ FALSE
+ 0
+ 50 Ohms
+ 1
+
+ DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9
+ 1250
+ 2.0V
+ 4:1
+ 200
+ 1
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ FALSE
+
+ 16
+ 10
+ 3
+ 1.5V
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/6
+ Disable
+ Enable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 1
+ 0
+
+
+
+
diff --git a/boards/Xilinx/vc709/1.8/mig_j1_j3.prj b/boards/Xilinx/vc709/1.8/mig_j1_j3.prj
new file mode 100644
index 000000000..4018f3281
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/mig_j1_j3.prj
@@ -0,0 +1,386 @@
+
+
+
+ design_2_mig_7series_0_1
+ 1
+ 1
+ Disable
+ 1024
+ ON
+ Enabled
+ xc7vx690t-ffg1761/-2
+ 2.3
+ Differential
+ Use System Clock
+ ACTIVE HIGH
+ FALSE
+ 0
+ 50 Ohms
+ 1
+
+ DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9
+ 1250
+ 2.0V
+ 4:1
+ 200
+ 1
+ 800
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ FALSE
+
+ 16
+ 10
+ 3
+ 1.5V
+ 4294967296
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/6
+ Disable
+ Enable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 1
+ 0
+
+
+
+
+
+ DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9
+ 1320
+ 2.0V
+ 4:1
+ 233.1
+ 0
+ 757
+ 7.625
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ FALSE
+
+ 16
+ 10
+ 3
+ 1.5V
+ 4294967296
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/6
+ Disable
+ Enable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 1
+ 0
+
+
+
+
diff --git a/boards/Xilinx/vc709/1.8/mig_j3.prj b/boards/Xilinx/vc709/1.8/mig_j3.prj
new file mode 100644
index 000000000..a889f48c1
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/mig_j3.prj
@@ -0,0 +1,208 @@
+
+
+
+ design_3_mig_7series_0_0
+ 1
+ 1
+ OFF
+ 1024
+ ON
+ Enabled
+ xc7vx690t-ffg1761/-2
+ 2.3
+ Differential
+ Differential
+ ACTIVE HIGH
+ FALSE
+ 0
+ 50 Ohms
+ 1
+
+ DDR3_SDRAM/SODIMMs/MT8KTF51264HZ-1G9
+ 1320
+ 2.0V
+ 4:1
+ 233.1
+ 1
+ 757
+ 7.625
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ FALSE
+
+ 16
+ 10
+ 3
+ 1.5V
+ 4294967296
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 11
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/6
+ Disable
+ Enable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 8
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 1
+ 0
+
+
+
+
diff --git a/boards/Xilinx/vc709/1.8/part0_pins.xml b/boards/Xilinx/vc709/1.8/part0_pins.xml
new file mode 100644
index 000000000..5e5c4857d
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/part0_pins.xml
@@ -0,0 +1,149 @@
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vc709/1.8/preset.xml b/boards/Xilinx/vc709/1.8/preset.xml
new file mode 100644
index 000000000..7ea9d0a3b
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/preset.xml
@@ -0,0 +1,376 @@
+
+
+
+
+
+
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+
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+
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+
+
diff --git a/boards/Xilinx/vc709/1.8/vc709_board.jpg b/boards/Xilinx/vc709/1.8/vc709_board.jpg
new file mode 100644
index 000000000..4a5f13daf
Binary files /dev/null and b/boards/Xilinx/vc709/1.8/vc709_board.jpg differ
diff --git a/boards/Xilinx/vc709/1.8/xitem.json b/boards/Xilinx/vc709/1.8/xitem.json
new file mode 100644
index 000000000..0924d6204
--- /dev/null
+++ b/boards/Xilinx/vc709/1.8/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vc709",
+ "display": "Virtex-7 VC709 Evaluation Platform",
+ "revision": "1.8",
+ "description": "Virtex-7 VC709 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vc709_board.jpg",
+ "website": "http://www.xilinx.com/vc709",
+ "search-keywords": [
+ "vc709",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190/production/2.2/LICENSE b/boards/Xilinx/vck190/production/2.2/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vck190/production/2.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190/production/2.2/board.xml b/boards/Xilinx/vck190/production/2.2/board.xml
new file mode 100755
index 000000000..11dc6556c
--- /dev/null
+++ b/boards/Xilinx/vck190/production/2.2/board.xml
@@ -0,0 +1,1530 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 2.2
+
+ Versal VCK190 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
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+
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+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
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+
+
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+
+
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+
+
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+
+
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+
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+
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+
+
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+
+
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+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
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+
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+
+
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+
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+
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+
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+
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+
+
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+
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+
+
+
+
+
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+
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+
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+
+
+
+
+
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+
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+
+
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+
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+
+
+
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+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vck190/production/2.2/changelog.txt b/boards/Xilinx/vck190/production/2.2/changelog.txt
new file mode 100755
index 000000000..3b59daa54
--- /dev/null
+++ b/boards/Xilinx/vck190/production/2.2/changelog.txt
@@ -0,0 +1,21 @@
+######### VCK190 change log ##############
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VCK190 Initial board support
+
diff --git a/boards/Xilinx/vck190/production/2.2/part0_pins.xml b/boards/Xilinx/vck190/production/2.2/part0_pins.xml
new file mode 100755
index 000000000..139673bf1
--- /dev/null
+++ b/boards/Xilinx/vck190/production/2.2/part0_pins.xml
@@ -0,0 +1,526 @@
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vck190/production/2.2/preset.xml b/boards/Xilinx/vck190/production/2.2/preset.xml
new file mode 100755
index 000000000..7c3b499b2
--- /dev/null
+++ b/boards/Xilinx/vck190/production/2.2/preset.xml
@@ -0,0 +1,162 @@
+
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diff --git a/boards/Xilinx/vck190/production/2.2/readme.txt b/boards/Xilinx/vck190/production/2.2/readme.txt
new file mode 100755
index 000000000..213767596
--- /dev/null
+++ b/boards/Xilinx/vck190/production/2.2/readme.txt
@@ -0,0 +1,4 @@
+Validate that the xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190/production/2.2/vck190_image.jpg b/boards/Xilinx/vck190/production/2.2/vck190_image.jpg
new file mode 100755
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190/production/2.2/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190/production/2.2/xitem.json b/boards/Xilinx/vck190/production/2.2/xitem.json
new file mode 100755
index 000000000..1f97c5de9
--- /dev/null
+++ b/boards/Xilinx/vck190/production/2.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190",
+ "display": "Versal VCK190 Evaluation Platform",
+ "revision": "2.2",
+ "description": "Versal VCK190 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190/production/3.0/LICENSE b/boards/Xilinx/vck190/production/3.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190/production/3.0/board.xml b/boards/Xilinx/vck190/production/3.0/board.xml
new file mode 100644
index 000000000..e977835d9
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.0/board.xml
@@ -0,0 +1,2195 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 3.0
+
+ Versal VCK190 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+ bank105_gty2_axi_eth
+
+
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+ bank105_gty3_axi_eth
+
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+
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+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
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+
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+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
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+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/boards/Xilinx/vck190/production/3.0/changelog.txt b/boards/Xilinx/vck190/production/3.0/changelog.txt
new file mode 100644
index 000000000..7460b35d4
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.0/changelog.txt
@@ -0,0 +1,29 @@
+######### VCK190 change log ##############
+3.0 - 2022.1
+Added OSPI and eMMC Boot Mode presets to Board Interface
+Added Board Flow Support For Versal GTs
+IPs : xxv_ethernet, l_ethernet and axi_ethernet
+Modified cips 3.0 preset for better readability
+Enabled Inter Processor Interrupts
+Enabled PS I2C on PMC_MIO 46 and 47
+
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VCK190 Initial board support
+
diff --git a/boards/Xilinx/vck190/production/3.0/part0_pins.xml b/boards/Xilinx/vck190/production/3.0/part0_pins.xml
new file mode 100644
index 000000000..d077f1926
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.0/part0_pins.xml
@@ -0,0 +1,541 @@
+
+
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diff --git a/boards/Xilinx/vck190/production/3.0/preset.xml b/boards/Xilinx/vck190/production/3.0/preset.xml
new file mode 100755
index 000000000..e77015e0c
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.0/preset.xml
@@ -0,0 +1,714 @@
+
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+
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+
+
+
+
+
+ Â Â Â Â Â
+ Â Â Â Â Â Â Â Â Â
+
+
+ Â Â Â Â Â
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
diff --git a/boards/Xilinx/vck190/production/3.0/readme.txt b/boards/Xilinx/vck190/production/3.0/readme.txt
new file mode 100644
index 000000000..3abf09aaa
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.0/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190/production/3.0/vck190_image.jpg b/boards/Xilinx/vck190/production/3.0/vck190_image.jpg
new file mode 100644
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190/production/3.0/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190/production/3.0/xitem.json b/boards/Xilinx/vck190/production/3.0/xitem.json
new file mode 100644
index 000000000..47bd29f03
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190",
+ "display": "Versal VCK190 Evaluation Platform",
+ "revision": "3.0",
+ "description": "Versal VCK190 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190/production/3.1/LICENSE b/boards/Xilinx/vck190/production/3.1/LICENSE
new file mode 100755
index 000000000..bbb038fb7
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190/production/3.1/board.xml b/boards/Xilinx/vck190/production/3.1/board.xml
new file mode 100755
index 000000000..88dfbced4
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.1/board.xml
@@ -0,0 +1,3429 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 3.1
+
+ Versal VCK190 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
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+
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+ bank105_gty2_axi_eth
+
+
+
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+
+
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+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single lane GT interface for PCIe X1
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Eight lane GT interface for PCIe X8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
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+
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+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+ PCIE X1 on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+
+
+ PCIE on Bank103 GT01
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+
+ PCIE on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+
+
+ PCIE X8 on Bank103 and Bank 104 GT
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+ PCIE RX on Bank104 GTY0
+
+
+ PCIE TX on Bank104 GTY0
+
+
+ PCIE RX on Bank104 GTY1
+
+
+ PCIE TX on Bank104 GTY1
+
+
+
+ PCIE RX on Bank104 GTY2
+
+
+ PCIE TX on Bank104 GTY2
+
+
+ PCIE RX on Bank104 GTY3
+
+
+ PCIE TX on Bank104 GTY3
+
+
+
+ PCIE REFCLK on Bank 103"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vck190/production/3.1/changelog.txt b/boards/Xilinx/vck190/production/3.1/changelog.txt
new file mode 100755
index 000000000..d2f09ff1c
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.1/changelog.txt
@@ -0,0 +1,32 @@
+######### VCK190 change log ##############
+3.1 - 2022.1_web
+Added board flow support for PCIe interface (X1,X2,X4 and X8 mode)
+
+3.0 - 2022.1
+Added OSPI and eMMC Boot Mode presets to Board Interface
+Added Board Flow Support For Versal GTs
+IPs : xxv_ethernet, l_ethernet and axi_ethernet
+Modified cips 3.0 preset for better readability
+Enabled Inter Processor Interrupts
+Enabled PS I2C on PMC_MIO 46 and 47
+
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VCK190 Initial board support
+
diff --git a/boards/Xilinx/vck190/production/3.1/part0_pins.xml b/boards/Xilinx/vck190/production/3.1/part0_pins.xml
new file mode 100755
index 000000000..a330c7c33
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.1/part0_pins.xml
@@ -0,0 +1,545 @@
+
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diff --git a/boards/Xilinx/vck190/production/3.1/preset.xml b/boards/Xilinx/vck190/production/3.1/preset.xml
new file mode 100755
index 000000000..7af8ca8ae
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.1/preset.xml
@@ -0,0 +1,784 @@
+
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+
+
+ Â Â Â Â Â
+ Â Â Â Â Â Â Â Â Â
+
+
+ Â Â Â Â Â
+
+
+
+
+
+
+
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+
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diff --git a/boards/Xilinx/vck190/production/3.1/readme.txt b/boards/Xilinx/vck190/production/3.1/readme.txt
new file mode 100755
index 000000000..3abf09aaa
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.1/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190/production/3.1/vck190_image.jpg b/boards/Xilinx/vck190/production/3.1/vck190_image.jpg
new file mode 100755
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190/production/3.1/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190/production/3.1/xitem.json b/boards/Xilinx/vck190/production/3.1/xitem.json
new file mode 100755
index 000000000..43ac5bb14
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190",
+ "display": "Versal VCK190 Evaluation Platform",
+ "revision": "3.1",
+ "description": "Versal VCK190 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190/production/3.2/LICENSE b/boards/Xilinx/vck190/production/3.2/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190/production/3.2/board.xml b/boards/Xilinx/vck190/production/3.2/board.xml
new file mode 100755
index 000000000..eb18ae228
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.2/board.xml
@@ -0,0 +1,3429 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 3.2
+
+ Versal VCK190 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ bank105_gty2_axi_eth
+
+
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+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
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+
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+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ Single lane GT interface for PCIe X1
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Eight lane GT interface for PCIe X8
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+ PCIE X1 on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+
+
+ PCIE on Bank103 GT01
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+
+ PCIE on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+
+
+ PCIE X8 on Bank103 and Bank 104 GT
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+ PCIE RX on Bank104 GTY0
+
+
+ PCIE TX on Bank104 GTY0
+
+
+ PCIE RX on Bank104 GTY1
+
+
+ PCIE TX on Bank104 GTY1
+
+
+
+ PCIE RX on Bank104 GTY2
+
+
+ PCIE TX on Bank104 GTY2
+
+
+ PCIE RX on Bank104 GTY3
+
+
+ PCIE TX on Bank104 GTY3
+
+
+
+ PCIE REFCLK on Bank 103"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vck190/production/3.2/changelog.txt b/boards/Xilinx/vck190/production/3.2/changelog.txt
new file mode 100755
index 000000000..aca3ec160
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.2/changelog.txt
@@ -0,0 +1,36 @@
+######### VCK190 change log ##############
+3.2 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+3.1 - 2022.1_web
+Added board flow support for PCIe interface (X1,X2,X4 and X8 mode)
+Adding MIO12 to CIPS OSPI preset - 2023.1
+
+3.0 - 2022.1
+Added OSPI and eMMC Boot Mode presets to Board Interface
+Added Board Flow Support For Versal GTs
+IPs : xxv_ethernet, l_ethernet and axi_ethernet
+Modified cips 3.0 preset for better readability
+Enabled Inter Processor Interrupts
+Enabled PS I2C on PMC_MIO 46 and 47
+
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VCK190 Initial board support
+
diff --git a/boards/Xilinx/vck190/production/3.2/part0_pins.xml b/boards/Xilinx/vck190/production/3.2/part0_pins.xml
new file mode 100755
index 000000000..69c88acea
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.2/part0_pins.xml
@@ -0,0 +1,545 @@
+
+
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+
diff --git a/boards/Xilinx/vck190/production/3.2/preset.xml b/boards/Xilinx/vck190/production/3.2/preset.xml
new file mode 100755
index 000000000..6f0950515
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.2/preset.xml
@@ -0,0 +1,816 @@
+
+
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+
+
+
+
+
+ Â Â Â Â Â
+ Â Â Â Â Â Â Â Â Â
+
+
+ Â Â Â Â Â
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vck190/production/3.2/readme.txt b/boards/Xilinx/vck190/production/3.2/readme.txt
new file mode 100755
index 000000000..3abf09aaa
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.2/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190/production/3.2/vck190_image.jpg b/boards/Xilinx/vck190/production/3.2/vck190_image.jpg
new file mode 100755
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190/production/3.2/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190/production/3.2/xitem.json b/boards/Xilinx/vck190/production/3.2/xitem.json
new file mode 100755
index 000000000..c6c2f2c30
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190",
+ "display": "Versal VCK190 Evaluation Platform",
+ "revision": "3.2",
+ "description": "Versal VCK190 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190/production/3.3/LICENSE b/boards/Xilinx/vck190/production/3.3/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190/production/3.3/board.xml b/boards/Xilinx/vck190/production/3.3/board.xml
new file mode 100644
index 000000000..c520e6315
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.3/board.xml
@@ -0,0 +1,3429 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 3.3
+
+ Versal VCK190 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty2_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single lane GT interface for PCIe X1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
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+
+
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+
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+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Eight lane GT interface for PCIe X8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
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+
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+
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+
+
+
+
+
+
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+
+
+
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+
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+
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+
+
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+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+ PCIE X1 on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+
+
+ PCIE on Bank103 GT01
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+
+ PCIE on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+
+
+ PCIE X8 on Bank103 and Bank 104 GT
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+ PCIE RX on Bank104 GTY0
+
+
+ PCIE TX on Bank104 GTY0
+
+
+ PCIE RX on Bank104 GTY1
+
+
+ PCIE TX on Bank104 GTY1
+
+
+
+ PCIE RX on Bank104 GTY2
+
+
+ PCIE TX on Bank104 GTY2
+
+
+ PCIE RX on Bank104 GTY3
+
+
+ PCIE TX on Bank104 GTY3
+
+
+
+ PCIE REFCLK on Bank 103"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vck190/production/3.3/changelog.txt b/boards/Xilinx/vck190/production/3.3/changelog.txt
new file mode 100644
index 000000000..cde8cdeb6
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.3/changelog.txt
@@ -0,0 +1,39 @@
+######### VCK190 change log ##############
+3.3 - 2024.1
+Updated CAN_FD configuration
+
+3.2 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+3.1 - 2022.1_web
+Added board flow support for PCIe interface (X1,X2,X4 and X8 mode)
+Adding MIO12 to CIPS OSPI preset - 2023.1
+
+3.0 - 2022.1
+Added OSPI and eMMC Boot Mode presets to Board Interface
+Added Board Flow Support For Versal GTs
+IPs : xxv_ethernet, l_ethernet and axi_ethernet
+Modified cips 3.0 preset for better readability
+Enabled Inter Processor Interrupts
+Enabled PS I2C on PMC_MIO 46 and 47
+
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VCK190 Initial board support
+
diff --git a/boards/Xilinx/vck190/production/3.3/part0_pins.xml b/boards/Xilinx/vck190/production/3.3/part0_pins.xml
new file mode 100644
index 000000000..69c88acea
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.3/part0_pins.xml
@@ -0,0 +1,545 @@
+
+
+
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diff --git a/boards/Xilinx/vck190/production/3.3/preset.xml b/boards/Xilinx/vck190/production/3.3/preset.xml
new file mode 100644
index 000000000..d6a350e9b
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.3/preset.xml
@@ -0,0 +1,820 @@
+
+
+
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+
+ Â Â Â Â Â
+ Â Â Â Â Â Â Â Â Â
+
+
+ Â Â Â Â Â
+
+
+
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+
+
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diff --git a/boards/Xilinx/vck190/production/3.3/readme.txt b/boards/Xilinx/vck190/production/3.3/readme.txt
new file mode 100644
index 000000000..3abf09aaa
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.3/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190/production/3.3/vck190_image.jpg b/boards/Xilinx/vck190/production/3.3/vck190_image.jpg
new file mode 100644
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190/production/3.3/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190/production/3.3/xitem.json b/boards/Xilinx/vck190/production/3.3/xitem.json
new file mode 100644
index 000000000..93f4479a0
--- /dev/null
+++ b/boards/Xilinx/vck190/production/3.3/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190",
+ "display": "Versal VCK190 Evaluation Platform",
+ "revision": "3.3",
+ "description": "Versal VCK190 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190_newl/production/1.0/LICENSE b/boards/Xilinx/vck190_newl/production/1.0/LICENSE
new file mode 100644
index 000000000..bbb038fb7
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190_newl/production/1.0/board.xml b/boards/Xilinx/vck190_newl/production/1.0/board.xml
new file mode 100755
index 000000000..cfab34b24
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.0/board.xml
@@ -0,0 +1,2195 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform with New SD Level Shifter"
+
+
+
+
+ Rev B03
+
+
+ 1.0
+
+ Versal VCK190 Evaluation Platform with New SD Level Shifter
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
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+
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+
+
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+
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
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+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty2_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vck190_newl/production/1.0/changelog.txt b/boards/Xilinx/vck190_newl/production/1.0/changelog.txt
new file mode 100755
index 000000000..815604a6a
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### VCK190 SD Level Shifter change log ##############
+1.0 - 2022.1
+VCK190 Board Files having support for new SD level shifter
+
diff --git a/boards/Xilinx/vck190_newl/production/1.0/part0_pins.xml b/boards/Xilinx/vck190_newl/production/1.0/part0_pins.xml
new file mode 100755
index 000000000..1abb051a4
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.0/part0_pins.xml
@@ -0,0 +1,541 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vck190_newl/production/1.0/preset.xml b/boards/Xilinx/vck190_newl/production/1.0/preset.xml
new file mode 100755
index 000000000..4bf2604bb
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.0/preset.xml
@@ -0,0 +1,715 @@
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+ Â Â Â Â Â
+
+ Â Â Â Â Â Â Â Â Â
+
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+ Â Â Â Â Â
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diff --git a/boards/Xilinx/vck190_newl/production/1.0/readme.txt b/boards/Xilinx/vck190_newl/production/1.0/readme.txt
new file mode 100755
index 000000000..3abf09aaa
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.0/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190_newl/production/1.0/vck190_image.jpg b/boards/Xilinx/vck190_newl/production/1.0/vck190_image.jpg
new file mode 100755
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190_newl/production/1.0/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190_newl/production/1.0/xitem.json b/boards/Xilinx/vck190_newl/production/1.0/xitem.json
new file mode 100755
index 000000000..e27383bc5
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190_newl",
+ "display": "Versal VCK190 Evaluation Platform with New SD Level Shifter",
+ "revision": "1.0",
+ "description": "Versal VCK190 Evaluation Platform with New SD Level Shifter",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190_newl",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190_newl/production/1.1/LICENSE b/boards/Xilinx/vck190_newl/production/1.1/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190_newl/production/1.1/board.xml b/boards/Xilinx/vck190_newl/production/1.1/board.xml
new file mode 100755
index 000000000..54293ff41
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.1/board.xml
@@ -0,0 +1,2195 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform with New SD Level Shifter"
+
+
+
+
+ Rev B03
+
+
+ 1.1
+
+ Versal VCK190 Evaluation Platform with New SD Level Shifter
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
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+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
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+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+ bank105_gty2_axi_eth
+
+
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+
+
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+ bank105_gty3_axi_eth
+
+
+
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+
+
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+
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+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
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+
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+ Four lane GT interface over qsfp1_connector
+
+
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+
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+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
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+
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+
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+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/boards/Xilinx/vck190_newl/production/1.1/changelog.txt b/boards/Xilinx/vck190_newl/production/1.1/changelog.txt
new file mode 100755
index 000000000..042b0355f
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.1/changelog.txt
@@ -0,0 +1,8 @@
+######### VCK190 SD Level Shifter change log ##############
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0 - 2022.1
+VCK190 Board Files having support for new SD level shifter
+Added MIO12 for OSPI preset - 2023.1
+
diff --git a/boards/Xilinx/vck190_newl/production/1.1/part0_pins.xml b/boards/Xilinx/vck190_newl/production/1.1/part0_pins.xml
new file mode 100755
index 000000000..d077f1926
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.1/part0_pins.xml
@@ -0,0 +1,541 @@
+
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diff --git a/boards/Xilinx/vck190_newl/production/1.1/preset.xml b/boards/Xilinx/vck190_newl/production/1.1/preset.xml
new file mode 100755
index 000000000..dbc34c3d0
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.1/preset.xml
@@ -0,0 +1,746 @@
+
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+
+
+ Â Â Â Â Â
+
+ Â Â Â Â Â Â Â Â Â
+
+
+
+ Â Â Â Â Â
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/boards/Xilinx/vck190_newl/production/1.1/readme.txt b/boards/Xilinx/vck190_newl/production/1.1/readme.txt
new file mode 100755
index 000000000..3abf09aaa
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.1/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190_newl/production/1.1/vck190_image.jpg b/boards/Xilinx/vck190_newl/production/1.1/vck190_image.jpg
new file mode 100755
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190_newl/production/1.1/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190_newl/production/1.1/xitem.json b/boards/Xilinx/vck190_newl/production/1.1/xitem.json
new file mode 100755
index 000000000..cab45d5f5
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190_newl",
+ "display": "Versal VCK190 Evaluation Platform with New SD Level Shifter",
+ "revision": "1.1",
+ "description": "Versal VCK190 Evaluation Platform with New SD Level Shifter",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190_newl",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vck190_newl/production/1.2/LICENSE b/boards/Xilinx/vck190_newl/production/1.2/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vck190_newl/production/1.2/board.xml b/boards/Xilinx/vck190_newl/production/1.2/board.xml
new file mode 100644
index 000000000..abba2f2a3
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.2/board.xml
@@ -0,0 +1,3429 @@
+
+
+
+
+
+
+
+ Versal VCK190 Evaluation Platform with New SD Level Shifter"
+
+
+
+
+ Rev B03
+
+
+ 1.2
+
+ Versal VCK190 Evaluation Platform with New SD Level Shifter
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvc1902 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+ bank105_gty2_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ Single lane GT interface for PCIe X1
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+ Eight lane GT interface for PCIe X8
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+ PCIE X1 on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+
+
+ PCIE on Bank103 GT01
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+
+ PCIE on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+
+
+ PCIE X8 on Bank103 and Bank 104 GT
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+ PCIE RX on Bank104 GTY0
+
+
+ PCIE TX on Bank104 GTY0
+
+
+ PCIE RX on Bank104 GTY1
+
+
+ PCIE TX on Bank104 GTY1
+
+
+
+ PCIE RX on Bank104 GTY2
+
+
+ PCIE TX on Bank104 GTY2
+
+
+ PCIE RX on Bank104 GTY3
+
+
+ PCIE TX on Bank104 GTY3
+
+
+
+ PCIE REFCLK on Bank 103"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vck190_newl/production/1.2/changelog.txt b/boards/Xilinx/vck190_newl/production/1.2/changelog.txt
new file mode 100644
index 000000000..1b4abafbf
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.2/changelog.txt
@@ -0,0 +1,15 @@
+######### VCK190 SD Level Shifter change log ##############
+1.2 - 2024.2
+Corrected the SD1_DATA_TRANSFER_MODE format
+
+1.2 - 2024.1
+Updated CAN_FD configuration
+Added board flow support for PCIe interface (X1,X2,X4 and X8 mode)
+
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0 - 2022.1
+VCK190 Board Files having support for new SD level shifter
+Added MIO12 for OSPI preset - 2023.1
+
diff --git a/boards/Xilinx/vck190_newl/production/1.2/part0_pins.xml b/boards/Xilinx/vck190_newl/production/1.2/part0_pins.xml
new file mode 100644
index 000000000..02a33ffd2
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.2/part0_pins.xml
@@ -0,0 +1,545 @@
+
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diff --git a/boards/Xilinx/vck190_newl/production/1.2/preset.xml b/boards/Xilinx/vck190_newl/production/1.2/preset.xml
new file mode 100644
index 000000000..459ac2598
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.2/preset.xml
@@ -0,0 +1,820 @@
+
+
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+ Â Â Â Â Â
+
+ Â Â Â Â Â Â Â Â Â
+
+
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+ Â Â Â Â Â
+
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diff --git a/boards/Xilinx/vck190_newl/production/1.2/readme.txt b/boards/Xilinx/vck190_newl/production/1.2/readme.txt
new file mode 100644
index 000000000..3abf09aaa
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.2/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvc1902-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vck190_newl/production/1.2/vck190_image.jpg b/boards/Xilinx/vck190_newl/production/1.2/vck190_image.jpg
new file mode 100644
index 000000000..33ca34a69
Binary files /dev/null and b/boards/Xilinx/vck190_newl/production/1.2/vck190_image.jpg differ
diff --git a/boards/Xilinx/vck190_newl/production/1.2/xitem.json b/boards/Xilinx/vck190_newl/production/1.2/xitem.json
new file mode 100644
index 000000000..c5356901f
--- /dev/null
+++ b/boards/Xilinx/vck190_newl/production/1.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vck190_newl",
+ "display": "Versal VCK190 Evaluation Platform with New SD Level Shifter",
+ "revision": "1.2",
+ "description": "Versal VCK190 Evaluation Platform with New SD Level Shifter",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "skemidi",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vck190",
+ "search-keywords": [
+ "vck190_newl",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu108/1.6/LICENSE b/boards/Xilinx/vcu108/1.6/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.6/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu108/1.6/board.xml b/boards/Xilinx/vcu108/1.6/board.xml
new file mode 100644
index 000000000..dd27e8ed3
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.6/board.xml
@@ -0,0 +1,2922 @@
+
+
+
+
+
+
+ VCU108 Board File Image
+
+
+
+ 1.0
+
+ 1.6
+ Virtex-UltraScale VCU108 Evaluation Platform
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+ Virtex-UltraScale FPGA part on the board
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
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+
+
+
+ DDR4 board interface C2, it can use DDR4 IP for connection.
+
+
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+
+
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+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single lane BullsEye interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dual lane BullsEye interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane BullsEye interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane BullsEye interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane BullsEye interface for 40G speed in l_ethernet
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane BullsEye interface for 50G speed in l_ethernet
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP for l_ethernet IP @40G speed
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP for l_ethernet I @50G speedP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over CFP2 for l_ethernet IP @40G speed
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over CFP2 for l_ethernet IP @50G speed
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ System Monitor Interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB DDR4 SDRAM memory C1
+
+
+
+
+
+
+ 4GB DDR4 SDRAM memory C1
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller UART or using IIC interface in the Kintex fabric
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY RESET OUT
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
+ Bulls Eye Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+ QSFP Connector
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diff --git a/boards/Xilinx/vcu108/1.6/changelog.txt b/boards/Xilinx/vcu108/1.6/changelog.txt
new file mode 100644
index 000000000..a9e0181f3
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.6/changelog.txt
@@ -0,0 +1,16 @@
+######### VCU108 change log ##############
+1.6
+Added GT location for XDMA IP
+Enabled support for interlaken IP (QSFP interface)
+
+1.5
+Enabled Sysmon board support
+
+1.4
+Enabled FMC support
+
+1.3
+No upper case attributes
+
+
+
diff --git a/boards/Xilinx/vcu108/1.6/part0_pins.xml b/boards/Xilinx/vcu108/1.6/part0_pins.xml
new file mode 100644
index 000000000..374a011cf
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.6/part0_pins.xml
@@ -0,0 +1,651 @@
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diff --git a/boards/Xilinx/vcu108/1.6/preset.xml b/boards/Xilinx/vcu108/1.6/preset.xml
new file mode 100644
index 000000000..a49b1ba9c
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.6/preset.xml
@@ -0,0 +1,691 @@
+
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diff --git a/boards/Xilinx/vcu108/1.6/vcu108_board.jpeg b/boards/Xilinx/vcu108/1.6/vcu108_board.jpeg
new file mode 100644
index 000000000..11f20fd3b
Binary files /dev/null and b/boards/Xilinx/vcu108/1.6/vcu108_board.jpeg differ
diff --git a/boards/Xilinx/vcu108/1.6/xitem.json b/boards/Xilinx/vcu108/1.6/xitem.json
new file mode 100644
index 000000000..da3407971
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.6/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu108",
+ "display": "Virtex-UltraScale VCU108 Evaluation Platform",
+ "revision": "1.6",
+ "description": "Virtex-UltraScale VCU108 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vcu108_board.jpeg",
+ "website": "www.xilinx.com/vcu108",
+ "search-keywords": [
+ "vcu108",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu108/1.7/LICENSE b/boards/Xilinx/vcu108/1.7/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.7/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu108/1.7/board.xml b/boards/Xilinx/vcu108/1.7/board.xml
new file mode 100644
index 000000000..f36f21c22
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.7/board.xml
@@ -0,0 +1,3313 @@
+
+
+
+
+
+
+ VCU108 Board File Image
+
+
+
+ 1.0
+
+ 1.7
+ Virtex-UltraScale VCU108 Evaluation Platform
+
+
+
+
+
+
+
+
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+
+
+
+ Virtex-UltraScale FPGA part on the board
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
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+ DDR4 board interface, it can use DDR4 IP for connection.
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+
+ DDR4 board interface C2, it can use DDR4 IP for connection.
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+ DDR4 board interface C2, it can use DDR4 IP for connection.
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+ 4-position user DIP Switch
+
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+
+
+
+
+
+ Single lane BullsEye interface
+
+
+
+
+
+
+
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+
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+
+
+
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+
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+
+
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+
+
+ Dual lane BullsEye interface
+
+
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+
+
+
+
+
+
+
+ 3-lane BullsEye interface
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane BullsEye interface
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+ 4-lane BullsEye interface for 40G speed in l_ethernet
+
+
+
+
+
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+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+ 4-lane BullsEye interface for 50G speed in l_ethernet
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP for l_ethernet IP @40G speed
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP for l_ethernet I @50G speedP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over CFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over CFP2 for l_ethernet IP @40G speed
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over CFP2 for l_ethernet IP @50G speed
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ System Monitor Interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB DDR4 SDRAM memory C1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB DDR4 SDRAM memory C2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller UART or using IIC interface in the Kintex fabric
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY RESET OUT
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
+ Bulls Eye Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ QSFP Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CFP2 Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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diff --git a/boards/Xilinx/vcu108/1.7/changelog.txt b/boards/Xilinx/vcu108/1.7/changelog.txt
new file mode 100644
index 000000000..80652beaf
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.7/changelog.txt
@@ -0,0 +1,18 @@
+######### VCU108 change log ##############
+1.7
+Added New DDR4 Memory Part MT40A256M16LY-062E support
+1.6
+Added GT location for XDMA IP
+Enabled support for interlaken IP (QSFP interface)
+
+1.5
+Enabled Sysmon board support
+
+1.4
+Enabled FMC support
+
+1.3
+No upper case attributes
+
+
+
diff --git a/boards/Xilinx/vcu108/1.7/part0_pins.xml b/boards/Xilinx/vcu108/1.7/part0_pins.xml
new file mode 100644
index 000000000..374a011cf
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.7/part0_pins.xml
@@ -0,0 +1,651 @@
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diff --git a/boards/Xilinx/vcu108/1.7/preset.xml b/boards/Xilinx/vcu108/1.7/preset.xml
new file mode 100644
index 000000000..2b7134332
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.7/preset.xml
@@ -0,0 +1,704 @@
+
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diff --git a/boards/Xilinx/vcu108/1.7/vcu108_board.jpeg b/boards/Xilinx/vcu108/1.7/vcu108_board.jpeg
new file mode 100644
index 000000000..11f20fd3b
Binary files /dev/null and b/boards/Xilinx/vcu108/1.7/vcu108_board.jpeg differ
diff --git a/boards/Xilinx/vcu108/1.7/xitem.json b/boards/Xilinx/vcu108/1.7/xitem.json
new file mode 100644
index 000000000..504f5e5b8
--- /dev/null
+++ b/boards/Xilinx/vcu108/1.7/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu108",
+ "display": "Virtex-UltraScale VCU108 Evaluation Platform",
+ "revision": "1.7",
+ "description": "Virtex-UltraScale VCU108 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vcu108_board.jpeg",
+ "website": "www.xilinx.com/vcu108",
+ "search-keywords": [
+ "vcu108",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu110/1.4/LICENSE b/boards/Xilinx/vcu110/1.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vcu110/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu110/1.4/board.xml b/boards/Xilinx/vcu110/1.4/board.xml
new file mode 100644
index 000000000..72da345d4
--- /dev/null
+++ b/boards/Xilinx/vcu110/1.4/board.xml
@@ -0,0 +1,1066 @@
+
+
+
+
+
+
+ VCU110 Board File Image
+
+
+
+ 1.0
+
+ 1.4
+ Virtex-UltraScale VCU110 Evaluation Platform
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ Virtex-UltraScale FPGA part on the board
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ System Monitor Interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller UART or using IIC interface in the Kintex fabric
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+ PHY RESET OUT
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vcu110/1.4/changelog.txt b/boards/Xilinx/vcu110/1.4/changelog.txt
new file mode 100644
index 000000000..ba820d04c
--- /dev/null
+++ b/boards/Xilinx/vcu110/1.4/changelog.txt
@@ -0,0 +1,12 @@
+######### VCU110 change log ##############
+1.4
+Enabled Sysmon board support
+
+1.3
+FMC Support
+
+1.2
+Avoiding upper case attributes
+
+
+
diff --git a/boards/Xilinx/vcu110/1.4/part0_pins.xml b/boards/Xilinx/vcu110/1.4/part0_pins.xml
new file mode 100644
index 000000000..799b883b0
--- /dev/null
+++ b/boards/Xilinx/vcu110/1.4/part0_pins.xml
@@ -0,0 +1,345 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
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+
+
+
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+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
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+
+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vcu110/1.4/preset.xml b/boards/Xilinx/vcu110/1.4/preset.xml
new file mode 100644
index 000000000..a6aeb9891
--- /dev/null
+++ b/boards/Xilinx/vcu110/1.4/preset.xml
@@ -0,0 +1,308 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
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+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vcu110/1.4/vcu110_board.jpeg b/boards/Xilinx/vcu110/1.4/vcu110_board.jpeg
new file mode 100644
index 000000000..b94237406
Binary files /dev/null and b/boards/Xilinx/vcu110/1.4/vcu110_board.jpeg differ
diff --git a/boards/Xilinx/vcu110/1.4/xitem.json b/boards/Xilinx/vcu110/1.4/xitem.json
new file mode 100644
index 000000000..492798551
--- /dev/null
+++ b/boards/Xilinx/vcu110/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu110",
+ "display": "Virtex-UltraScale VCU110 Evaluation Platform",
+ "revision": "1.4",
+ "description": "Virtex-UltraScale VCU110 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vcu110_board.jpeg",
+ "website": "www.xilinx.com/vcu110",
+ "search-keywords": [
+ "vcu110",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu118/2.0/LICENSE b/boards/Xilinx/vcu118/2.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu118/2.0/board.xml b/boards/Xilinx/vcu118/2.0/board.xml
new file mode 100644
index 000000000..191310e76
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.0/board.xml
@@ -0,0 +1,1996 @@
+
+
+
+
+
+ VCU118 Board File Image
+
+
+
+ 2.0
+
+ 2.0
+ Virtex UltraScale+ VCU118 Evaluation Platform
+
+
+
+
+
+
+
+
+
+ Virtex-UltraScale+ FPGA part on the board
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface C2, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
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+
+
+
+
+
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+
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+
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+
+
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+
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+
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+
+
+
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+
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+
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+
+
+
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+
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+
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+
+
+
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+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+ >>
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+ >
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+
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+
+
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+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
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+ 2-lane GT interface over QSFP2
+
+
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+
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+ 3-lane GT interface over QSFP2
+
+
+
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+
+
+ 4-lane GT interface over QSFP2
+
+
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+
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+ QSFP Connector 1
+
+
+
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+ QSFP Connector 2
+
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+ 4Gb DDR4 SDRAM memory C1
+
+
+
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+
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+
+
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+
+
+ 4Gb DDR4 SDRAM memory C2
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ Dip Switches 3 to 0
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 1.8V LVDS differential 250 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+ 1.8V LVDS differential 250 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller or using IIC interface in Virtex fabric
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ PCI Express
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ PHY RESET OUT
+
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
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+
+
diff --git a/boards/Xilinx/vcu118/2.0/changelog.txt b/boards/Xilinx/vcu118/2.0/changelog.txt
new file mode 100644
index 000000000..f118dc7c7
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.0/changelog.txt
@@ -0,0 +1,11 @@
+######### vcu118 chnage log ##############
+2.0
+Enabled production device Support
+
+1.2
+Enabled SGMII, 10/25, 40/50, Interlaken, CMAC+ Ethernet interfaces
+
+1.1
+Added PCI X16 data width support.
+Updated DDR4 speed grade
+Changed display name to refelct ES1 platform: (Virtex UltraScale+ VCU118-ES1 Evaluation Platform)
diff --git a/boards/Xilinx/vcu118/2.0/part0_pins.xml b/boards/Xilinx/vcu118/2.0/part0_pins.xml
new file mode 100644
index 000000000..15edd02d8
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.0/part0_pins.xml
@@ -0,0 +1,418 @@
+
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+
diff --git a/boards/Xilinx/vcu118/2.0/preset.xml b/boards/Xilinx/vcu118/2.0/preset.xml
new file mode 100644
index 000000000..08946cd47
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.0/preset.xml
@@ -0,0 +1,634 @@
+
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+
diff --git a/boards/Xilinx/vcu118/2.0/vcu118_board.jpeg b/boards/Xilinx/vcu118/2.0/vcu118_board.jpeg
new file mode 100644
index 000000000..c4f66e5b0
Binary files /dev/null and b/boards/Xilinx/vcu118/2.0/vcu118_board.jpeg differ
diff --git a/boards/Xilinx/vcu118/2.0/xitem.json b/boards/Xilinx/vcu118/2.0/xitem.json
new file mode 100644
index 000000000..c19c676f1
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu118",
+ "display": "Virtex UltraScale+ VCU118 Evaluation Platform",
+ "revision": "2.0",
+ "description": "Virtex UltraScale+ VCU118 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vcu118",
+ "search-keywords": [
+ "vcu118",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vcu118/2.3/LICENSE b/boards/Xilinx/vcu118/2.3/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu118/2.3/board.xml b/boards/Xilinx/vcu118/2.3/board.xml
new file mode 100644
index 000000000..f35876d2e
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.3/board.xml
@@ -0,0 +1,2177 @@
+
+
+
+
+
+
+ VCU118 Board File Image
+
+
+
+ 2.0
+
+ 2.3
+ Virtex UltraScale+ VCU118 Evaluation Platform
+
+
+
+
+
+
+
+
+
+ Virtex-UltraScale+ FPGA part on the board
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface C2, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
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+ 4-position user DIP Switch
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+ Primary interface to communicate with ethernet phy in SGMII mode.
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+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
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+ 1-lane GT interface over QSFP
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+ 2-lane GT interface over QSFP1
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+ 3-lane GT interface over QSFP1
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+ 4-lane GT interface over QSFP1
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+ 1-lane GT interface over QSFP2
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+ 2-lane GT interface over QSFP2
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+ 3-lane GT interface over QSFP2
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+ 4-lane GT interface over QSFP2
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+ QSFP Connector 1
+
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+ QSFP Connector 2
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+
+ 4Gb DDR4 SDRAM memory C1
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+ 4Gb DDR4 SDRAM memory C2
+
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+
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+
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+
+
+ Dip Switches 3 to 0
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 1.8V LVDS differential 250 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 1.8V LVDS differential 250 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller or using IIC interface in Virtex fabric
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ PCI Express
+
+
+
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+
+ PHY RESET OUT
+
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
+
+
+ 2G bit of nonvolatile storage that can be used for configuration or data storage
+
+
+
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+
diff --git a/boards/Xilinx/vcu118/2.3/changelog.txt b/boards/Xilinx/vcu118/2.3/changelog.txt
new file mode 100644
index 000000000..39b15c1d6
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.3/changelog.txt
@@ -0,0 +1,19 @@
+######### vcu118 chnage log ##############
+2.3
+Enabled QSPI board support
+Updated SGMII Interface IO attributes
+Enabled support for pcie4_uscale_plus IP
+
+2.2
+Added GT location for XDMA IP
+
+2.0
+Enabled production device Support
+
+1.2
+Enabled SGMII, 10/25, 40/50, Interlaken, CMAC+ Ethernet interfaces
+
+1.1
+Added PCI X16 data width support.
+Updated DDR4 speed grade
+Changed display name to refelct ES1 platform: (Virtex UltraScale+ VCU118-ES1 Evaluation Platform)
diff --git a/boards/Xilinx/vcu118/2.3/part0_pins.xml b/boards/Xilinx/vcu118/2.3/part0_pins.xml
new file mode 100644
index 000000000..5e1fbe379
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.3/part0_pins.xml
@@ -0,0 +1,426 @@
+
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+
diff --git a/boards/Xilinx/vcu118/2.3/preset.xml b/boards/Xilinx/vcu118/2.3/preset.xml
new file mode 100644
index 000000000..f6da75cb1
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.3/preset.xml
@@ -0,0 +1,756 @@
+
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diff --git a/boards/Xilinx/vcu118/2.3/vcu118_board.jpeg b/boards/Xilinx/vcu118/2.3/vcu118_board.jpeg
new file mode 100644
index 000000000..c4f66e5b0
Binary files /dev/null and b/boards/Xilinx/vcu118/2.3/vcu118_board.jpeg differ
diff --git a/boards/Xilinx/vcu118/2.3/xitem.json b/boards/Xilinx/vcu118/2.3/xitem.json
new file mode 100644
index 000000000..f3a991d3d
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu118",
+ "display": "Virtex UltraScale+ VCU118 Evaluation Platform",
+ "revision": "2.3",
+ "description": "Virtex UltraScale+ VCU118 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vcu118_board.jpeg",
+ "website": "www.xilinx.com/vcu118",
+ "search-keywords": [
+ "vcu118",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu118/2.4/LICENSE b/boards/Xilinx/vcu118/2.4/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu118/2.4/board.xml b/boards/Xilinx/vcu118/2.4/board.xml
new file mode 100644
index 000000000..6c3d18099
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.4/board.xml
@@ -0,0 +1,2674 @@
+
+
+
+
+
+
+ VCU118 Board File Image
+
+
+
+ 2.0
+
+ 2.4
+ Virtex UltraScale+ VCU118 Evaluation Platform
+
+
+
+
+
+
+
+
+
+ Virtex-UltraScale+ FPGA part on the board
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
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+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
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+
+
+ DDR4 board interface C2, it can use DDR4 IP for connection.
+
+
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+
+
+
+
+
+
+
+ DDR4 board interface C2, it can use DDR4 IP for connection.
+
+
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+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over QSFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP1
+
+
+
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+
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+
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+
+
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+
+
+
+
+
+
+ 1-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2-lane GT interface over QSFP2
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 3-lane GT interface over QSFP2
+
+
+
+
+
+
+
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+
+
+
+
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+
+
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+
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+
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+
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+
+
+
+
+
+
+
+ 4-lane GT interface over QSFP2
+
+
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+
+
+
+
+ QSFP Connector 1
+
+
+
+
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+ QSFP Connector 2
+
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+
+
+
+ 4Gb DDR4 SDRAM memory C1
+
+
+
+
+
+
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+
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+
+
+
+
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+ 4Gb DDR4 SDRAM memory C2
+
+
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+
+
+
+
+
+
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+
+
+ Dip Switches 3 to 0
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+ 1.8V LVDS differential 250 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 1.8V LVDS differential 250 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+ 3.3V LVDS SI570 programmable oscillator used as differential clock on the board; Can be programmed using system controller or using IIC interface in Virtex fabric
+
+
+
+
+
+ 1.8V LVDS differential 125 MHz oscillator used as differential clock on the board
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ I2C
+
+
+ CPU Reset Push Button, Active High
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ PCI Express
+
+
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+
+
+
+ PHY RESET OUT
+
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
+
+
+ 2G bit of nonvolatile storage that can be used for configuration or data storage
+
+
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diff --git a/boards/Xilinx/vcu118/2.4/changelog.txt b/boards/Xilinx/vcu118/2.4/changelog.txt
new file mode 100644
index 000000000..1ada72050
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.4/changelog.txt
@@ -0,0 +1,22 @@
+######### vcu118 chnage log ##############
+2.4
+Added New DDR4 Memory Part MT40A256M16LY-062E support.
+
+2.3
+Enabled QSPI board support
+Updated SGMII Interface IO attributes
+Enabled support for pcie4_uscale_plus IP
+
+2.2
+Added GT location for XDMA IP
+
+2.0
+Enabled production device Support
+
+1.2
+Enabled SGMII, 10/25, 40/50, Interlaken, CMAC+ Ethernet interfaces
+
+1.1
+Added PCI X16 data width support.
+Updated DDR4 speed grade
+Changed display name to refelct ES1 platform: (Virtex UltraScale+ VCU118-ES1 Evaluation Platform)
diff --git a/boards/Xilinx/vcu118/2.4/part0_pins.xml b/boards/Xilinx/vcu118/2.4/part0_pins.xml
new file mode 100644
index 000000000..72ed597ab
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.4/part0_pins.xml
@@ -0,0 +1,438 @@
+
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diff --git a/boards/Xilinx/vcu118/2.4/preset.xml b/boards/Xilinx/vcu118/2.4/preset.xml
new file mode 100644
index 000000000..cb59e7a36
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.4/preset.xml
@@ -0,0 +1,801 @@
+
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diff --git a/boards/Xilinx/vcu118/2.4/vcu118_board.jpeg b/boards/Xilinx/vcu118/2.4/vcu118_board.jpeg
new file mode 100644
index 000000000..c4f66e5b0
Binary files /dev/null and b/boards/Xilinx/vcu118/2.4/vcu118_board.jpeg differ
diff --git a/boards/Xilinx/vcu118/2.4/xitem.json b/boards/Xilinx/vcu118/2.4/xitem.json
new file mode 100644
index 000000000..65482773a
--- /dev/null
+++ b/boards/Xilinx/vcu118/2.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu118",
+ "display": "Virtex UltraScale+ VCU118 Evaluation Platform",
+ "revision": "2.4",
+ "description": "Virtex UltraScale+ VCU118 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vcu118_board.jpeg",
+ "website": "www.xilinx.com/vcu118",
+ "search-keywords": [
+ "vcu118",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu128/production/1.0/LICENSE b/boards/Xilinx/vcu128/production/1.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vcu128/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu128/production/1.0/board.xml b/boards/Xilinx/vcu128/production/1.0/board.xml
new file mode 100644
index 000000000..b6c026dfb
--- /dev/null
+++ b/boards/Xilinx/vcu128/production/1.0/board.xml
@@ -0,0 +1,2204 @@
+
+
+
+
+
+
+ VCU128 Board File Image
+
+
+
+ Rev 1.0
+
+ 1.0
+ Virtex Ultrascale+ HBM VCU128 Evaluation Platform
+
+
+
+
+
+
+
+
+
+ Virtex-UltraScale+ FPGA part on the board
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+ Primary interface to communicate with ethernet phy in SGMII mode.
+
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+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
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+ 1-lane GT interface over QSFP
+
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+ 2-lane GT interface over QSFP1
+
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+ 3-lane GT interface over QSFP1
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+ 4-lane GT interface over QSFP1
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+ 1-lane GT interface over QSFP2
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+ 2-lane GT interface over QSFP2
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+ 3-lane GT interface over QSFP2
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+ 4-lane GT interface over QSFP2
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+ 1-lane GT interface over QSFP3
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+ 2-lane GT interface over QSFP3
+
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+ 3-lane GT interface over QSFP3
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+ 4-lane GT interface over QSFP3
+
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+ 1-lane GT interface over QSFP4
+
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+ 2-lane GT interface over QSFP4
+
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+ 3-lane GT interface over QSFP4
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+ 4-lane GT interface over QSFP4
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+
+
+ QSFP Connector 1
+
+
+
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+
+
+
+ QSFP Connector 2
+
+
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+
+
+
+ QSFP Connector 3
+
+
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+
+
+
+
+
+ QSFP Connector 4
+
+
+
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+
+
+
+
+
+
+
+
+
+ 8Gb DDR4 SDRAM memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ 1.8V LVDS differential 100 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ I2C_0
+
+
+
+ I2C_1
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ Dummy port in
+
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
+
+
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+
+
+
diff --git a/boards/Xilinx/vcu128/production/1.0/changelog.txt b/boards/Xilinx/vcu128/production/1.0/changelog.txt
new file mode 100644
index 000000000..77f27adef
--- /dev/null
+++ b/boards/Xilinx/vcu128/production/1.0/changelog.txt
@@ -0,0 +1,18 @@
+######### VCU128 change log ##############
+Production 1.0
+VCU128 Vivado Board Support for 2019.2
+
+ES
+1.1
+VCU128 Vivado board support(Vivado 2019.1)
+Removed qsfp2_si5328 and qsfp3_si5328 clocks
+Changed default frequency for si570 qsfp clocks from 161.132812 Mhz to 156.25 Mhz
+
+1.0
+VCU128 Initial board support(Vivado 2018.3 web)
+
+
+
+
+
+
diff --git a/boards/Xilinx/vcu128/production/1.0/part0_pins.xml b/boards/Xilinx/vcu128/production/1.0/part0_pins.xml
new file mode 100644
index 000000000..5f5569c6b
--- /dev/null
+++ b/boards/Xilinx/vcu128/production/1.0/part0_pins.xml
@@ -0,0 +1,359 @@
+
+
+
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+
+
diff --git a/boards/Xilinx/vcu128/production/1.0/preset.xml b/boards/Xilinx/vcu128/production/1.0/preset.xml
new file mode 100644
index 000000000..a8c15e606
--- /dev/null
+++ b/boards/Xilinx/vcu128/production/1.0/preset.xml
@@ -0,0 +1,796 @@
+
+
+
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diff --git a/boards/Xilinx/vcu128/production/1.0/vcu128_board.jpeg b/boards/Xilinx/vcu128/production/1.0/vcu128_board.jpeg
new file mode 100644
index 000000000..5626505a4
Binary files /dev/null and b/boards/Xilinx/vcu128/production/1.0/vcu128_board.jpeg differ
diff --git a/boards/Xilinx/vcu128/production/1.0/xitem.json b/boards/Xilinx/vcu128/production/1.0/xitem.json
new file mode 100644
index 000000000..82f2ca841
--- /dev/null
+++ b/boards/Xilinx/vcu128/production/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu128",
+ "display": "Virtex Ultrascale+ HBM VCU128 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Virtex Ultrascale+ HBM VCU128 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vcu128_board.jpeg",
+ "website": "www.xilinx.com/vcu128",
+ "search-keywords": [
+ "vcu128",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu129/production/1.0/LICENSE b/boards/Xilinx/vcu129/production/1.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vcu129/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu129/production/1.0/VCU129_board.jpeg b/boards/Xilinx/vcu129/production/1.0/VCU129_board.jpeg
new file mode 100755
index 000000000..895266562
Binary files /dev/null and b/boards/Xilinx/vcu129/production/1.0/VCU129_board.jpeg differ
diff --git a/boards/Xilinx/vcu129/production/1.0/board.xml b/boards/Xilinx/vcu129/production/1.0/board.xml
new file mode 100644
index 000000000..5ca2407a9
--- /dev/null
+++ b/boards/Xilinx/vcu129/production/1.0/board.xml
@@ -0,0 +1,1324 @@
+
+
+
+
+
+
+ VCU129 Board File Image
+
+
+
+ 1.1
+
+ 1.0
+ Virtex Ultrascale+ 56G VCU129 Evaluation Platform
+
+
+
+
+
+
+
+
+
+ Virtex-UltraScale+ FPGA part on the board
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Primary interface to communicate with ethernet phy in SGMII mode.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Secondary interface to communicate with ethernet phy when mode is selected as SGMII.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16Gb DDR4 SDRAM memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1.8V LVDS differential 100 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ 1.8V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ I2C_0
+
+
+
+ I2C_1
+
+
+
+ I2C_2
+
+
+
+ I2C_3
+
+
+
+ I2C_4
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY RESET OUT
+
+
+
+ Dummy port in
+
+
+
+
+ PHY on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 625 MHz SGMII differential clock from Marvell PHY used as clock for SGMII interface
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
diff --git a/boards/Xilinx/vcu129/production/1.0/changelog.txt b/boards/Xilinx/vcu129/production/1.0/changelog.txt
new file mode 100644
index 000000000..4ad3d0ecd
--- /dev/null
+++ b/boards/Xilinx/vcu129/production/1.0/changelog.txt
@@ -0,0 +1,10 @@
+######### VCU129 change log ##############
+1.0
+VCU129 Production board support(Vivado 2019.1.1)
+QSPI and PCI Express support is not included
+
+
+
+
+
+
diff --git a/boards/Xilinx/vcu129/production/1.0/part0_pins.xml b/boards/Xilinx/vcu129/production/1.0/part0_pins.xml
new file mode 100644
index 000000000..3f6dc55bc
--- /dev/null
+++ b/boards/Xilinx/vcu129/production/1.0/part0_pins.xml
@@ -0,0 +1,284 @@
+
+
+
+
+
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diff --git a/boards/Xilinx/vcu129/production/1.0/preset.xml b/boards/Xilinx/vcu129/production/1.0/preset.xml
new file mode 100644
index 000000000..b6835a8a7
--- /dev/null
+++ b/boards/Xilinx/vcu129/production/1.0/preset.xml
@@ -0,0 +1,317 @@
+
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diff --git a/boards/Xilinx/vcu129/production/1.0/xitem.json b/boards/Xilinx/vcu129/production/1.0/xitem.json
new file mode 100644
index 000000000..41c888a4f
--- /dev/null
+++ b/boards/Xilinx/vcu129/production/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu129",
+ "display": "Virtex Ultrascale+ 56G VCU129 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Virtex Ultrascale+ 56G VCU129 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "VCU129_board.jpeg",
+ "website": "www.xilinx.com/VCU129",
+ "search-keywords": [
+ "vcu129",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vcu1525/1.3/LICENSE b/boards/Xilinx/vcu1525/1.3/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vcu1525/1.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vcu1525/1.3/board.xml b/boards/Xilinx/vcu1525/1.3/board.xml
new file mode 100644
index 000000000..544fb8363
--- /dev/null
+++ b/boards/Xilinx/vcu1525/1.3/board.xml
@@ -0,0 +1,3088 @@
+
+
+
+
+
+
+ Virtex UltraScale+ VCU1525 Acceleration Development Board
+
+
+
+
+ 1.0
+
+
+ 1.3
+
+ Virtex UltraScale+ VCU1525 Acceleration Development Board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Virtex UltraScale+ VU9P FPGA
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
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+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
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+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
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+
+
+
+
+
+
+
+
+ 4-position user DIP Switch
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+ I2C
+
+
+
+ 16GB DDR4 SDRAM memory C0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM memory C1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM memory C2
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM memory C3
+
+
+
+
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+ CPU Reset Push Button, Active Low
+
+
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+ LEDs, 2 to 0, Active High
+
+
+
+ Dip Switches 3 to 0
+
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+
+ PCI Express
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+ Clock input from PCI Express edge connector
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+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
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+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
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+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
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+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
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+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
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diff --git a/boards/Xilinx/vcu1525/1.3/changelog.txt b/boards/Xilinx/vcu1525/1.3/changelog.txt
new file mode 100644
index 000000000..cdf88fa89
--- /dev/null
+++ b/boards/Xilinx/vcu1525/1.3/changelog.txt
@@ -0,0 +1,19 @@
+######### VCU1525 change log ############
+1.3
+Added GT quad location for XDMA IP
+Enabled support for pcie4_uscale_plus IP
+Updated DDR4 system clock IO attributes. Using LVDS and DQS_BIAS now (2019.1)
+
+1.2
+DIMM functionality enabled
+QDMA support is added
+
+1.1
+FPPGA part change, 1.0 is deprecated
+
+1.0
+Added SLR parameter to DDR4 components(Vivado 2018.1)
+
+1.0
+VCU1525 Initial board support(Vivado 2017.4)
+
diff --git a/boards/Xilinx/vcu1525/1.3/part0_pins.xml b/boards/Xilinx/vcu1525/1.3/part0_pins.xml
new file mode 100644
index 000000000..6b4233617
--- /dev/null
+++ b/boards/Xilinx/vcu1525/1.3/part0_pins.xml
@@ -0,0 +1,754 @@
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diff --git a/boards/Xilinx/vcu1525/1.3/preset.xml b/boards/Xilinx/vcu1525/1.3/preset.xml
new file mode 100644
index 000000000..0782e4e25
--- /dev/null
+++ b/boards/Xilinx/vcu1525/1.3/preset.xml
@@ -0,0 +1,449 @@
+
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diff --git a/boards/Xilinx/vcu1525/1.3/vcu1525_image.png b/boards/Xilinx/vcu1525/1.3/vcu1525_image.png
new file mode 100644
index 000000000..839e4a4af
Binary files /dev/null and b/boards/Xilinx/vcu1525/1.3/vcu1525_image.png differ
diff --git a/boards/Xilinx/vcu1525/1.3/xitem.json b/boards/Xilinx/vcu1525/1.3/xitem.json
new file mode 100644
index 000000000..5d901b010
--- /dev/null
+++ b/boards/Xilinx/vcu1525/1.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vcu1525",
+ "display": "Virtex UltraScale+ VCU1525 Acceleration Development Board",
+ "revision": "1.3",
+ "description": "Virtex UltraScale+ VCU1525 Acceleration Development Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "vcu1525_image.png",
+ "website": "https://www.xilinx.com/products/boards-and-kits/vcu1525-a.html",
+ "search-keywords": [
+ "VCU1525",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vek280/es/rev_a/1.0/LICENSE b/boards/Xilinx/vek280/es/rev_a/1.0/LICENSE
new file mode 100644
index 000000000..bbb038fb7
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vek280/es/rev_a/1.0/README.md b/boards/Xilinx/vek280/es/rev_a/1.0/README.md
new file mode 100644
index 000000000..139e072db
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.0/README.md
@@ -0,0 +1,4 @@
+Validate that the xcve2802-vsvh1760-2LP-e-S-es1 is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vek280/es/rev_a/1.0/board.xml b/boards/Xilinx/vek280/es/rev_a/1.0/board.xml
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index 000000000..4fe475369
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.0/board.xml
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+ Versal VEK280 ES1 Evaluation Platform"
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+ Rev A01
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+ 1.0
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+ Versal VEK280 ES1 Evaluation Platform
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+ XCVE2802 FPGA
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ Versal CIPS component
+
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+ 16GBIT LPDDR4 memory
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+ 16GBIT LPDDR4 memory
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+ 16GBIT LPDDR4 memory
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+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
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+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
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+ GPIO Push Buttons
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+ GPIO DIP Switches
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+ GPIO LEDs
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+ System Controller GPIO
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diff --git a/boards/Xilinx/vek280/es/rev_a/1.0/changelog.txt b/boards/Xilinx/vek280/es/rev_a/1.0/changelog.txt
new file mode 100644
index 000000000..476e05b29
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.0/changelog.txt
@@ -0,0 +1,7 @@
+######### VEK280 change log ##############
+1.0
+
+Initial support for VEK280 ES1 Evaluation Platform (2022.2_web)
+
+
+
diff --git a/boards/Xilinx/vek280/es/rev_a/1.0/part0_pins.xml b/boards/Xilinx/vek280/es/rev_a/1.0/part0_pins.xml
new file mode 100644
index 000000000..de19c5482
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.0/part0_pins.xml
@@ -0,0 +1,683 @@
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diff --git a/boards/Xilinx/vek280/es/rev_a/1.0/preset.xml b/boards/Xilinx/vek280/es/rev_a/1.0/preset.xml
new file mode 100644
index 000000000..ad8c2ae1b
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.0/preset.xml
@@ -0,0 +1,297 @@
+
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diff --git a/boards/Xilinx/vek280/es/rev_a/1.0/xitem.json b/boards/Xilinx/vek280/es/rev_a/1.0/xitem.json
new file mode 100644
index 000000000..86fb9196a
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vek280_es",
+ "display": "Versal VEK280 ES1 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Versal VEK280 ES1 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vek280",
+ "search-keywords": [
+ "vek280_es",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vek280/es/rev_a/1.1/LICENSE b/boards/Xilinx/vek280/es/rev_a/1.1/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vek280/es/rev_a/1.1/README.md b/boards/Xilinx/vek280/es/rev_a/1.1/README.md
new file mode 100644
index 000000000..139e072db
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.1/README.md
@@ -0,0 +1,4 @@
+Validate that the xcve2802-vsvh1760-2LP-e-S-es1 is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vek280/es/rev_a/1.1/board.xml b/boards/Xilinx/vek280/es/rev_a/1.1/board.xml
new file mode 100644
index 000000000..05786574c
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.1/board.xml
@@ -0,0 +1,1798 @@
+
+
+
+
+
+
+
+ Versal VEK280 ES1 Evaluation Platform"
+
+
+
+
+ Rev A01
+
+
+ 1.1
+
+ Versal VEK280 ES1 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVE2802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
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+
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+
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+
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+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
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+
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+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
diff --git a/boards/Xilinx/vek280/es/rev_a/1.1/changelog.txt b/boards/Xilinx/vek280/es/rev_a/1.1/changelog.txt
new file mode 100644
index 000000000..06c9069ff
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.1/changelog.txt
@@ -0,0 +1,9 @@
+######### VEK280 change log ##############
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0
+Initial support for VEK280 ES1 Evaluation Platform (2022.2_web)
+
+
+
diff --git a/boards/Xilinx/vek280/es/rev_a/1.1/part0_pins.xml b/boards/Xilinx/vek280/es/rev_a/1.1/part0_pins.xml
new file mode 100644
index 000000000..65977ef95
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.1/part0_pins.xml
@@ -0,0 +1,683 @@
+
+
+
+
+
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diff --git a/boards/Xilinx/vek280/es/rev_a/1.1/preset.xml b/boards/Xilinx/vek280/es/rev_a/1.1/preset.xml
new file mode 100644
index 000000000..520d6c204
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.1/preset.xml
@@ -0,0 +1,302 @@
+
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diff --git a/boards/Xilinx/vek280/es/rev_a/1.1/xitem.json b/boards/Xilinx/vek280/es/rev_a/1.1/xitem.json
new file mode 100644
index 000000000..9cafcb312
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_a/1.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vek280_es",
+ "display": "Versal VEK280 ES1 Evaluation Platform",
+ "revision": "1.1",
+ "description": "Versal VEK280 ES1 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vek280",
+ "search-keywords": [
+ "vek280_es",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vek280/es/rev_b/1.0/LICENSE b/boards/Xilinx/vek280/es/rev_b/1.0/LICENSE
new file mode 100755
index 000000000..bbb038fb7
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vek280/es/rev_b/1.0/README.md b/boards/Xilinx/vek280/es/rev_b/1.0/README.md
new file mode 100755
index 000000000..2462a399b
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.0/README.md
@@ -0,0 +1,4 @@
+Validate that the xcve2802-vsvh1760-2MP-e-S-es1 is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vek280/es/rev_b/1.0/board.xml b/boards/Xilinx/vek280/es/rev_b/1.0/board.xml
new file mode 100755
index 000000000..48092cee1
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.0/board.xml
@@ -0,0 +1,1798 @@
+
+
+
+
+
+
+
+ Versal VEK280 ES1 Rev B01 Evaluation Platform"
+
+
+
+
+ Rev B01
+
+
+ 1.0
+
+ Versal VEK280 ES1 Rev B01 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVE2802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vek280/es/rev_b/1.0/changelog.txt b/boards/Xilinx/vek280/es/rev_b/1.0/changelog.txt
new file mode 100755
index 000000000..d05adb2de
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.0/changelog.txt
@@ -0,0 +1,7 @@
+######### VEK280 change log ##############
+1.0
+
+Initial support for VEK280 ES1 Rev B01 Evaluation Platform (2022.2_web)
+
+
+
diff --git a/boards/Xilinx/vek280/es/rev_b/1.0/part0_pins.xml b/boards/Xilinx/vek280/es/rev_b/1.0/part0_pins.xml
new file mode 100755
index 000000000..1c10b2282
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.0/part0_pins.xml
@@ -0,0 +1,683 @@
+
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diff --git a/boards/Xilinx/vek280/es/rev_b/1.0/preset.xml b/boards/Xilinx/vek280/es/rev_b/1.0/preset.xml
new file mode 100755
index 000000000..849aada12
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.0/preset.xml
@@ -0,0 +1,297 @@
+
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diff --git a/boards/Xilinx/vek280/es/rev_b/1.0/xitem.json b/boards/Xilinx/vek280/es/rev_b/1.0/xitem.json
new file mode 100755
index 000000000..278ecc957
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vek280_es_revb",
+ "display": "Versal VEK280 ES1 Rev B01 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Versal VEK280 ES1 Rev B01 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vek280",
+ "search-keywords": [
+ "vek280_es_revb",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vek280/es/rev_b/1.1/LICENSE b/boards/Xilinx/vek280/es/rev_b/1.1/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vek280/es/rev_b/1.1/README.md b/boards/Xilinx/vek280/es/rev_b/1.1/README.md
new file mode 100755
index 000000000..7063cc124
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.1/README.md
@@ -0,0 +1,7 @@
+Validate that the xcve2802-vsvh1760-2MP-e-S-es1 is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
+
+Note : As per the schematic, bank 705 & bank 706 are provided with 1.5v (VADJ_FMC), but board file sets these bank pin's I/O standard to support MIPI interface (requires 1.2v).
+ User needs to take care of bank 705 & 706 pins I/O standard, if the MIPI interface is added and used in the design through board connections.
diff --git a/boards/Xilinx/vek280/es/rev_b/1.1/board.xml b/boards/Xilinx/vek280/es/rev_b/1.1/board.xml
new file mode 100755
index 000000000..e2267ceca
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.1/board.xml
@@ -0,0 +1,1789 @@
+
+
+
+
+
+ Versal VEK280 ES1 Evaluation Platform"
+
+
+
+
+ Rev B01
+
+
+ 1.1
+
+ Versal VEK280 ES1 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ XCVE2802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
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+
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+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
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+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
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+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+ System Controller GPIO
+
+
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diff --git a/boards/Xilinx/vek280/es/rev_b/1.1/changelog.txt b/boards/Xilinx/vek280/es/rev_b/1.1/changelog.txt
new file mode 100755
index 000000000..a6c710a71
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.1/changelog.txt
@@ -0,0 +1,9 @@
+######### VEK280 change log ##############
+1.1
+Added FPCP_HSPC connector support for MIPI Interface (2023.1)
+
+1.0
+Initial support for VEK280 ES1 Evaluation Platform (2022.2_web)
+
+
+
diff --git a/boards/Xilinx/vek280/es/rev_b/1.1/part0_pins.xml b/boards/Xilinx/vek280/es/rev_b/1.1/part0_pins.xml
new file mode 100755
index 000000000..e860a3be6
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.1/part0_pins.xml
@@ -0,0 +1,761 @@
+
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+
diff --git a/boards/Xilinx/vek280/es/rev_b/1.1/preset.xml b/boards/Xilinx/vek280/es/rev_b/1.1/preset.xml
new file mode 100755
index 000000000..73187a60c
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.1/preset.xml
@@ -0,0 +1,301 @@
+
+
+
+
+
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+
+
\ No newline at end of file
diff --git a/boards/Xilinx/vek280/es/rev_b/1.1/xitem.json b/boards/Xilinx/vek280/es/rev_b/1.1/xitem.json
new file mode 100755
index 000000000..50abba221
--- /dev/null
+++ b/boards/Xilinx/vek280/es/rev_b/1.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vek280_es_revb",
+ "display": "Versal VEK280 ES1 Evaluation Platform with FMC Connector",
+ "revision": "1.1",
+ "description": "Versal VEK280 ES1 Evaluation Platform with FMC Connector",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vek280",
+ "search-keywords": [
+ "vek280_es_revb",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vek280/production/1.0/LICENSE b/boards/Xilinx/vek280/production/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vek280/production/1.0/README.md b/boards/Xilinx/vek280/production/1.0/README.md
new file mode 100644
index 000000000..9c43d9e48
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.0/README.md
@@ -0,0 +1,7 @@
+Validate that the xcve2802-vsvh1760-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
+
+Note : As per the schematic, bank 705 & bank 706 are provided with 1.5v (VADJ_FMC), but board file sets these bank pin's I/O standard to support MIPI interface (requires 1.2v).
+ User needs to take care of bank 705 & 706 pins I/O standard, if the MIPI interface is added and used in the design through board connections.
diff --git a/boards/Xilinx/vek280/production/1.0/board.xml b/boards/Xilinx/vek280/production/1.0/board.xml
new file mode 100644
index 000000000..65652ccb0
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.0/board.xml
@@ -0,0 +1,1789 @@
+
+
+
+
+
+ Versal VEK280 Evaluation Platform"
+
+
+
+
+ Rev B03
+
+
+ 1.0
+
+ Versal VEK280 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVE2802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ Versal CIPS component
+
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+ 16GBIT LPDDR4 memory
+
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+ 16GBIT LPDDR4 memory
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+ 16GBIT LPDDR4 memory
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+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
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+
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+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
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+ GPIO Push Buttons
+
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+ GPIO DIP Switches
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+ GPIO LEDs
+
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+ System Controller GPIO
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diff --git a/boards/Xilinx/vek280/production/1.0/changelog.txt b/boards/Xilinx/vek280/production/1.0/changelog.txt
new file mode 100644
index 000000000..30a2892b9
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.0/changelog.txt
@@ -0,0 +1,6 @@
+######### VEK280 change log ##############
+1.0
+Initial support for VEK280 pre_production Evaluation Platform (2023.2)
+
+
+
diff --git a/boards/Xilinx/vek280/production/1.0/part0_pins.xml b/boards/Xilinx/vek280/production/1.0/part0_pins.xml
new file mode 100644
index 000000000..f65378eb8
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.0/part0_pins.xml
@@ -0,0 +1,761 @@
+
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diff --git a/boards/Xilinx/vek280/production/1.0/preset.xml b/boards/Xilinx/vek280/production/1.0/preset.xml
new file mode 100644
index 000000000..73187a60c
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.0/preset.xml
@@ -0,0 +1,301 @@
+
+
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+
+
\ No newline at end of file
diff --git a/boards/Xilinx/vek280/production/1.0/xitem.json b/boards/Xilinx/vek280/production/1.0/xitem.json
new file mode 100644
index 000000000..c51d2cf0d
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vek280",
+ "display": "Versal VEK280 Evaluation Platform with FMC Connector",
+ "revision": "1.0",
+ "description": "Versal VEK280 Evaluation Platform with FMC Connector",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "skemidi",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vek280",
+ "search-keywords": [
+ "vek280",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vek280/production/1.1/LICENSE b/boards/Xilinx/vek280/production/1.1/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vek280/production/1.1/README.md b/boards/Xilinx/vek280/production/1.1/README.md
new file mode 100644
index 000000000..9c43d9e48
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.1/README.md
@@ -0,0 +1,7 @@
+Validate that the xcve2802-vsvh1760-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
+
+Note : As per the schematic, bank 705 & bank 706 are provided with 1.5v (VADJ_FMC), but board file sets these bank pin's I/O standard to support MIPI interface (requires 1.2v).
+ User needs to take care of bank 705 & 706 pins I/O standard, if the MIPI interface is added and used in the design through board connections.
diff --git a/boards/Xilinx/vek280/production/1.1/board.xml b/boards/Xilinx/vek280/production/1.1/board.xml
new file mode 100644
index 000000000..2907e8007
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.1/board.xml
@@ -0,0 +1,1789 @@
+
+
+
+
+
+ Versal VEK280 Evaluation Platform"
+
+
+
+
+ Rev B03
+
+
+ 1.1
+
+ Versal VEK280 Evaluation Platform
+
+
+
+
+
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+
+
+ XCVE2802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
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+
diff --git a/boards/Xilinx/vek280/production/1.1/changelog.txt b/boards/Xilinx/vek280/production/1.1/changelog.txt
new file mode 100644
index 000000000..26fd5c711
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.1/changelog.txt
@@ -0,0 +1,9 @@
+######### VEK280 change log ##############
+1.1
+Initial support for VEK280 Evaluation Platform (2023.2)
+
+1.0
+Initial support for VEK280 production Evaluation Platform (2023.2)
+
+
+
diff --git a/boards/Xilinx/vek280/production/1.1/part0_pins.xml b/boards/Xilinx/vek280/production/1.1/part0_pins.xml
new file mode 100644
index 000000000..f65378eb8
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.1/part0_pins.xml
@@ -0,0 +1,761 @@
+
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diff --git a/boards/Xilinx/vek280/production/1.1/preset.xml b/boards/Xilinx/vek280/production/1.1/preset.xml
new file mode 100644
index 000000000..c7080e0ad
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.1/preset.xml
@@ -0,0 +1,321 @@
+
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\ No newline at end of file
diff --git a/boards/Xilinx/vek280/production/1.1/xitem.json b/boards/Xilinx/vek280/production/1.1/xitem.json
new file mode 100644
index 000000000..953f05477
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vek280",
+ "display": "Versal VEK280 Evaluation Platform with FMC Connector",
+ "revision": "1.1",
+ "description": "Versal VEK280 Evaluation Platform with FMC Connector",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "skemidi",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vek280",
+ "search-keywords": [
+ "vek280",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vek280/production/1.2/LICENSE b/boards/Xilinx/vek280/production/1.2/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vek280/production/1.2/README.md b/boards/Xilinx/vek280/production/1.2/README.md
new file mode 100644
index 000000000..9c43d9e48
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.2/README.md
@@ -0,0 +1,7 @@
+Validate that the xcve2802-vsvh1760-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
+
+Note : As per the schematic, bank 705 & bank 706 are provided with 1.5v (VADJ_FMC), but board file sets these bank pin's I/O standard to support MIPI interface (requires 1.2v).
+ User needs to take care of bank 705 & 706 pins I/O standard, if the MIPI interface is added and used in the design through board connections.
diff --git a/boards/Xilinx/vek280/production/1.2/board.xml b/boards/Xilinx/vek280/production/1.2/board.xml
new file mode 100644
index 000000000..a5eb51aba
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.2/board.xml
@@ -0,0 +1,1789 @@
+
+
+
+
+
+ Versal VEK280 Evaluation Platform"
+
+
+
+
+ Rev B03
+
+
+ 1.2
+
+ Versal VEK280 Evaluation Platform
+
+
+
+
+
+
+
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+
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+
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+
+
+ XCVE2802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
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+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/vek280/production/1.2/changelog.txt b/boards/Xilinx/vek280/production/1.2/changelog.txt
new file mode 100644
index 000000000..f7f5bd73c
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.2/changelog.txt
@@ -0,0 +1,12 @@
+######### VEK280 change log ##############
+1.2 - 2024.1
+Updated CAN_FD configuration
+
+1.1 - 2023.2
+Initial support for VEK280 Evaluation Platform
+
+1.0 - 2023.2
+Initial support for VEK280 production Evaluation Platform
+
+
+
diff --git a/boards/Xilinx/vek280/production/1.2/part0_pins.xml b/boards/Xilinx/vek280/production/1.2/part0_pins.xml
new file mode 100644
index 000000000..f65378eb8
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.2/part0_pins.xml
@@ -0,0 +1,761 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vek280/production/1.2/preset.xml b/boards/Xilinx/vek280/production/1.2/preset.xml
new file mode 100644
index 000000000..8b322d645
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.2/preset.xml
@@ -0,0 +1,325 @@
+
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\ No newline at end of file
diff --git a/boards/Xilinx/vek280/production/1.2/xitem.json b/boards/Xilinx/vek280/production/1.2/xitem.json
new file mode 100644
index 000000000..c141ffaf1
--- /dev/null
+++ b/boards/Xilinx/vek280/production/1.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vek280",
+ "display": "Versal VEK280 Evaluation Platform with FMC Connector",
+ "revision": "1.2",
+ "description": "Versal VEK280 Evaluation Platform with FMC Connector",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "skemidi",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vek280",
+ "search-keywords": [
+ "vek280",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vermeo_t1_mpsoc/1.0/LICENSE b/boards/Xilinx/vermeo_t1_mpsoc/1.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_mpsoc/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml b/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml
new file mode 100755
index 000000000..c8ceb547e
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_mpsoc/1.0/board.xml
@@ -0,0 +1,1596 @@
+
+
+
+
+
+
+ Vermeo T1 MPSoC Board
+
+
+
+
+ Rev A
+
+
+ 1.0
+
+ Vermeo T1 MPSoC Board
+
+
+
+
+
+
+
+
+
+
+
+ T1 MPSoC FPGA
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
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+ 4-lane GT interface over QSFP
+
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+
+ 1-lane GT interface over SFP
+
+
+
+
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+
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+
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+
+
+ 1-lane GT interface over SFP
+
+
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+
+
+
+
+
+
+
+
+ 8Gb DDR4 SDRAM memory C0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ I2C
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PCI Express
+
+
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+
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+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ QSFP Connector
+
+
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+ SFP Connector
+
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+ SFP Connector
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diff --git a/boards/Xilinx/vermeo_t1_mpsoc/1.0/changelog.txt b/boards/Xilinx/vermeo_t1_mpsoc/1.0/changelog.txt
new file mode 100755
index 000000000..326154fa1
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_mpsoc/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### Varium change log ##############
+1.0
+Vermeo T1 MPSoC initial board support (Vivado 2020.1)
+
diff --git a/boards/Xilinx/vermeo_t1_mpsoc/1.0/part0_pins.xml b/boards/Xilinx/vermeo_t1_mpsoc/1.0/part0_pins.xml
new file mode 100755
index 000000000..e6f4268ae
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_mpsoc/1.0/part0_pins.xml
@@ -0,0 +1,340 @@
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diff --git a/boards/Xilinx/vermeo_t1_mpsoc/1.0/preset.xml b/boards/Xilinx/vermeo_t1_mpsoc/1.0/preset.xml
new file mode 100755
index 000000000..615b4f6f6
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_mpsoc/1.0/preset.xml
@@ -0,0 +1,537 @@
+
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diff --git a/boards/Xilinx/vermeo_t1_mpsoc/1.0/t1_image.jpg b/boards/Xilinx/vermeo_t1_mpsoc/1.0/t1_image.jpg
new file mode 100755
index 000000000..9d6544a8a
Binary files /dev/null and b/boards/Xilinx/vermeo_t1_mpsoc/1.0/t1_image.jpg differ
diff --git a/boards/Xilinx/vermeo_t1_mpsoc/1.0/xitem.json b/boards/Xilinx/vermeo_t1_mpsoc/1.0/xitem.json
new file mode 100755
index 000000000..1fd1478b1
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_mpsoc/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vermeo_t1_mpsoc",
+ "display": "Zynq Ultrascale+ MPSoC T1 Development Board",
+ "revision": "1.0",
+ "description": "Zynq Ultrascale+ MPSoC T1 Development Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Accelerator Cards/Telco",
+ "logo": "t1_image.jpg",
+ "website": "http://www.xilinx.com",
+ "search-keywords": [
+ "t1_mpsoc",
+ "https://www.xilinx.com/",
+ "board",
+ "Accelerator Cards/Telco"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vermeo_t1_rfsoc/1.0/LICENSE b/boards/Xilinx/vermeo_t1_rfsoc/1.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_rfsoc/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml b/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml
new file mode 100755
index 000000000..3370c63f0
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_rfsoc/1.0/board.xml
@@ -0,0 +1,1430 @@
+
+
+
+
+
+
+ Vermeo T1 RFSoC Board
+
+
+
+
+ Rev A
+
+
+ 1.0
+
+ Vermeo T1 RFSoC Board
+
+
+
+
+
+
+
+
+
+
+
+ T1 RFSoC FPGA
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
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+ 4-lane GT interface over QSFP
+
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+
+
+ 8Gb DDR4 SDRAM memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1.2V LVDS differential 300 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ I2C
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PCI Express
+
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+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ QSFP Connector
+
+
+
+
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+
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diff --git a/boards/Xilinx/vermeo_t1_rfsoc/1.0/changelog.txt b/boards/Xilinx/vermeo_t1_rfsoc/1.0/changelog.txt
new file mode 100755
index 000000000..829d1310b
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_rfsoc/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### Varium change log ##############
+1.0
+Vermeo T1 RFSoC initial board support (Vivado 2020.1)
+
diff --git a/boards/Xilinx/vermeo_t1_rfsoc/1.0/part0_pins.xml b/boards/Xilinx/vermeo_t1_rfsoc/1.0/part0_pins.xml
new file mode 100755
index 000000000..973fa415d
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_rfsoc/1.0/part0_pins.xml
@@ -0,0 +1,326 @@
+
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diff --git a/boards/Xilinx/vermeo_t1_rfsoc/1.0/preset.xml b/boards/Xilinx/vermeo_t1_rfsoc/1.0/preset.xml
new file mode 100755
index 000000000..2248a6517
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_rfsoc/1.0/preset.xml
@@ -0,0 +1,576 @@
+
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diff --git a/boards/Xilinx/vermeo_t1_rfsoc/1.0/t1_image.jpg b/boards/Xilinx/vermeo_t1_rfsoc/1.0/t1_image.jpg
new file mode 100755
index 000000000..9d6544a8a
Binary files /dev/null and b/boards/Xilinx/vermeo_t1_rfsoc/1.0/t1_image.jpg differ
diff --git a/boards/Xilinx/vermeo_t1_rfsoc/1.0/xitem.json b/boards/Xilinx/vermeo_t1_rfsoc/1.0/xitem.json
new file mode 100755
index 000000000..a3e8b6d2d
--- /dev/null
+++ b/boards/Xilinx/vermeo_t1_rfsoc/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vermeo_t1_rfsoc",
+ "display": "Zynq Ultrascale+ RFSoC T1 Development Board",
+ "revision": "1.0",
+ "description": "Zynq Ultrascale+ RFSoC T1 Development Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Accelerator Cards/Telco",
+ "logo": "t1_image.jpg",
+ "website": "http://www.xilinx.com/",
+ "search-keywords": [
+ "t1_rfsoc",
+ "https://www.xilinx.com/",
+ "board",
+ "Accelerator Cards/Telco"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vhk158/production/1.0/LICENSE b/boards/Xilinx/vhk158/production/1.0/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vhk158/production/1.0/board.xml b/boards/Xilinx/vhk158/production/1.0/board.xml
new file mode 100755
index 000000000..37b4f70e9
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.0/board.xml
@@ -0,0 +1,928 @@
+
+
+
+
+
+
+
+ Versal VHK158 Evaluation Platform"
+
+
+
+
+ Rev B1
+
+
+ 1.0
+
+ Versal VHK158 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvh1582 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 DIMM0 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ DDR4 DIMM1 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
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+
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+
+
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+
+
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+
+
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+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM DIMM0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 DIMM0 Controller
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 DIMM1 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vhk158/production/1.0/changelog.txt b/boards/Xilinx/vhk158/production/1.0/changelog.txt
new file mode 100755
index 000000000..b8525721a
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.0/changelog.txt
@@ -0,0 +1,5 @@
+######### VHK158 change log ##############
+
+1.0 - 2023.1
+VHK158 Production Initial board support
+
diff --git a/boards/Xilinx/vhk158/production/1.0/part0_pins.xml b/boards/Xilinx/vhk158/production/1.0/part0_pins.xml
new file mode 100755
index 000000000..56fffc477
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.0/part0_pins.xml
@@ -0,0 +1,468 @@
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diff --git a/boards/Xilinx/vhk158/production/1.0/preset.xml b/boards/Xilinx/vhk158/production/1.0/preset.xml
new file mode 100755
index 000000000..70d6ae78b
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.0/preset.xml
@@ -0,0 +1,337 @@
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diff --git a/boards/Xilinx/vhk158/production/1.0/readme.txt b/boards/Xilinx/vhk158/production/1.0/readme.txt
new file mode 100755
index 000000000..79e620db9
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.0/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvh1582-vsva3697-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vhk158/production/1.0/xitem.json b/boards/Xilinx/vhk158/production/1.0/xitem.json
new file mode 100755
index 000000000..827763671
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vhk158",
+ "display": "Versal VHK158 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Versal VHK158 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "ashishd",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vhk158",
+ "search-keywords": [
+ "vhk158",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vhk158/production/1.1/LICENSE b/boards/Xilinx/vhk158/production/1.1/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vhk158/production/1.1/board.xml b/boards/Xilinx/vhk158/production/1.1/board.xml
new file mode 100644
index 000000000..c9e32923b
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.1/board.xml
@@ -0,0 +1,930 @@
+
+
+
+
+
+
+
+ Versal VHK158 Evaluation Platform"
+
+
+
+
+ Rev B01
+
+
+ 1.1
+
+ Versal VHK158 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvh1582 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 DIMM0 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
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+
+
+ DDR4 DIMM1 board interface, it can use DDR4 IP for connection.
+
+
+
+
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+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM DIMM0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 DIMM0 Controller
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 DIMM1 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
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+
+
+
+
+
diff --git a/boards/Xilinx/vhk158/production/1.1/changelog.txt b/boards/Xilinx/vhk158/production/1.1/changelog.txt
new file mode 100644
index 000000000..148a2b0aa
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.1/changelog.txt
@@ -0,0 +1,7 @@
+######### VHK158 change log ##############
+1.1 - 2023.1
+Corrected board files to include support for multiple parts.
+
+1.0 - 2023.1
+VHK158 Production Initial board support.
+
diff --git a/boards/Xilinx/vhk158/production/1.1/part0_pins.xml b/boards/Xilinx/vhk158/production/1.1/part0_pins.xml
new file mode 100644
index 000000000..56fffc477
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.1/part0_pins.xml
@@ -0,0 +1,468 @@
+
+
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diff --git a/boards/Xilinx/vhk158/production/1.1/preset.xml b/boards/Xilinx/vhk158/production/1.1/preset.xml
new file mode 100644
index 000000000..70d6ae78b
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.1/preset.xml
@@ -0,0 +1,337 @@
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vhk158/production/1.1/readme.txt b/boards/Xilinx/vhk158/production/1.1/readme.txt
new file mode 100644
index 000000000..79e620db9
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.1/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvh1582-vsva3697-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vhk158/production/1.1/xitem.json b/boards/Xilinx/vhk158/production/1.1/xitem.json
new file mode 100644
index 000000000..b27a75917
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.1/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vhk158",
+ "display": "Versal VHK158 Evaluation Platform",
+ "revision": "1.1",
+ "description": "Versal VHK158 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "ashishd",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vhk158",
+ "search-keywords": [
+ "vhk158",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
+
diff --git a/boards/Xilinx/vhk158/production/1.2/LICENSE b/boards/Xilinx/vhk158/production/1.2/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vhk158/production/1.2/board.xml b/boards/Xilinx/vhk158/production/1.2/board.xml
new file mode 100644
index 000000000..98b94df67
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.2/board.xml
@@ -0,0 +1,960 @@
+
+
+
+
+
+
+
+ Versal VHK158 Evaluation Platform"
+
+
+
+
+ Rev B01
+
+
+ 1.2
+
+ Versal VHK158 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvh1582 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 DIMM0 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ DDR4 DIMM1 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
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+
+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM DIMM0
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 DIMM0 Controller
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 DIMM1 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vhk158/production/1.2/changelog.txt b/boards/Xilinx/vhk158/production/1.2/changelog.txt
new file mode 100644
index 000000000..2e5865e20
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.2/changelog.txt
@@ -0,0 +1,10 @@
+######### VHK158 change log ##############
+1.2 - 2024.2
+Added sysctrl_uart interface
+
+1.1 - 2023.1
+Corrected board files to include support for multiple parts.
+
+1.0 - 2023.1
+VHK158 Production Initial board support.
+
diff --git a/boards/Xilinx/vhk158/production/1.2/part0_pins.xml b/boards/Xilinx/vhk158/production/1.2/part0_pins.xml
new file mode 100644
index 000000000..1483d5fa9
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.2/part0_pins.xml
@@ -0,0 +1,471 @@
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
diff --git a/boards/Xilinx/vhk158/production/1.2/preset.xml b/boards/Xilinx/vhk158/production/1.2/preset.xml
new file mode 100644
index 000000000..70d6ae78b
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.2/preset.xml
@@ -0,0 +1,337 @@
+
+
+
+
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+
diff --git a/boards/Xilinx/vhk158/production/1.2/readme.txt b/boards/Xilinx/vhk158/production/1.2/readme.txt
new file mode 100644
index 000000000..79e620db9
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.2/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvh1582-vsva3697-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vhk158/production/1.2/xitem.json b/boards/Xilinx/vhk158/production/1.2/xitem.json
new file mode 100644
index 000000000..b27a75917
--- /dev/null
+++ b/boards/Xilinx/vhk158/production/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vhk158",
+ "display": "Versal VHK158 Evaluation Platform",
+ "revision": "1.1",
+ "description": "Versal VHK158 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "ashishd",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vhk158",
+ "search-keywords": [
+ "vhk158",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
+
diff --git a/boards/Xilinx/vmk180/production/2.2/LICENSE b/boards/Xilinx/vmk180/production/2.2/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/2.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vmk180/production/2.2/board.xml b/boards/Xilinx/vmk180/production/2.2/board.xml
new file mode 100755
index 000000000..edc250217
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/2.2/board.xml
@@ -0,0 +1,1535 @@
+
+
+
+
+
+
+
+ Versal VMK180 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 2.2
+
+ Versal VMK180 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvm1802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vmk180/production/2.2/changelog.txt b/boards/Xilinx/vmk180/production/2.2/changelog.txt
new file mode 100755
index 000000000..bf90a3e6b
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/2.2/changelog.txt
@@ -0,0 +1,21 @@
+######### VMK180 change log ##############
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VMK180 Initial board support
+
diff --git a/boards/Xilinx/vmk180/production/2.2/part0_pins.xml b/boards/Xilinx/vmk180/production/2.2/part0_pins.xml
new file mode 100755
index 000000000..3f4a429d7
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/2.2/part0_pins.xml
@@ -0,0 +1,527 @@
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/vmk180/production/2.2/preset.xml b/boards/Xilinx/vmk180/production/2.2/preset.xml
new file mode 100755
index 000000000..597cf32c9
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/2.2/preset.xml
@@ -0,0 +1,164 @@
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
diff --git a/boards/Xilinx/vmk180/production/2.2/readme.txt b/boards/Xilinx/vmk180/production/2.2/readme.txt
new file mode 100755
index 000000000..a84265656
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/2.2/readme.txt
@@ -0,0 +1,4 @@
+Validate that the xcvm1802-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vmk180/production/2.2/xitem.json b/boards/Xilinx/vmk180/production/2.2/xitem.json
new file mode 100755
index 000000000..02cd4fadc
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/2.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vmk180",
+ "display": "Versal VMK180 Evaluation Platform",
+ "revision": "2.2",
+ "description": "Versal VMK180 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vmk180",
+ "search-keywords": [
+ "vmk180",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vmk180/production/3.0/LICENSE b/boards/Xilinx/vmk180/production/3.0/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vmk180/production/3.0/board.xml b/boards/Xilinx/vmk180/production/3.0/board.xml
new file mode 100755
index 000000000..0de778b28
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.0/board.xml
@@ -0,0 +1,2181 @@
+
+
+
+
+
+
+
+ Versal VMK180 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 3.0
+
+ Versal VMK180 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvm1802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
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+
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+
+
+
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+
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+
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+
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+
+
+
+
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+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty2_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vmk180/production/3.0/changelog.txt b/boards/Xilinx/vmk180/production/3.0/changelog.txt
new file mode 100755
index 000000000..706f9035b
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.0/changelog.txt
@@ -0,0 +1,29 @@
+######### VMK180 change log ##############
+3.0 - 2022.1
+Added OSPI and eMMC Boot Mode presets to Board Interface
+Added Board Flow Support For Versal GTs
+IPs : xxv_ethernet, l_ethernet and axi_ethernet
+Modified cips 3.0 preset for better readability
+Enabled Inter Processor Interrupts
+Enabled PS I2C on PMC_MIO 46 and 47
+
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VMK180 Initial board support
+
diff --git a/boards/Xilinx/vmk180/production/3.0/part0_pins.xml b/boards/Xilinx/vmk180/production/3.0/part0_pins.xml
new file mode 100755
index 000000000..84374bda8
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.0/part0_pins.xml
@@ -0,0 +1,542 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vmk180/production/3.0/preset.xml b/boards/Xilinx/vmk180/production/3.0/preset.xml
new file mode 100755
index 000000000..e9887c46c
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.0/preset.xml
@@ -0,0 +1,713 @@
+
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+ Â Â Â Â Â
+ Â Â Â Â Â Â Â Â Â
+
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+ Â Â Â Â Â
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diff --git a/boards/Xilinx/vmk180/production/3.0/readme.txt b/boards/Xilinx/vmk180/production/3.0/readme.txt
new file mode 100755
index 000000000..7805dc9da
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.0/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvm1802-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vmk180/production/3.0/xitem.json b/boards/Xilinx/vmk180/production/3.0/xitem.json
new file mode 100755
index 000000000..f4fb90b46
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vmk180",
+ "display": "Versal VMK180 Evaluation Platform",
+ "revision": "3.0",
+ "description": "Versal VMK180 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vmk180",
+ "search-keywords": [
+ "vmk180",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vmk180/production/3.1/LICENSE b/boards/Xilinx/vmk180/production/3.1/LICENSE
new file mode 100644
index 000000000..bbb038fb7
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vmk180/production/3.1/board.xml b/boards/Xilinx/vmk180/production/3.1/board.xml
new file mode 100755
index 000000000..10de9cb83
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.1/board.xml
@@ -0,0 +1,3416 @@
+
+
+
+
+
+
+
+ Versal VMK180 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 3.1
+
+ Versal VMK180 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvm1802 FPGA
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
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+
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty2_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single lane GT interface for PCIe X1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
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+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Eight lane GT interface for PCIe X8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+ PCIE X1 on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+
+
+ PCIE on Bank103 GT01
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+
+ PCIE on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+
+
+ PCIE X8 on Bank103 and Bank 104 GT
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+ PCIE RX on Bank104 GTY0
+
+
+ PCIE TX on Bank104 GTY0
+
+
+ PCIE RX on Bank104 GTY1
+
+
+ PCIE TX on Bank104 GTY1
+
+
+
+ PCIE RX on Bank104 GTY2
+
+
+ PCIE TX on Bank104 GTY2
+
+
+ PCIE RX on Bank104 GTY3
+
+
+ PCIE TX on Bank104 GTY3
+
+
+
+ PCIE REFCLK on Bank 103"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vmk180/production/3.1/changelog.txt b/boards/Xilinx/vmk180/production/3.1/changelog.txt
new file mode 100755
index 000000000..2377b51e7
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.1/changelog.txt
@@ -0,0 +1,32 @@
+######### VMK180 change log ##############
+3.1 - 2022.1_web
+Added board flow support for PCIe interface (X1,X2,X4 and X8 mode)
+
+3.0 - 2022.1
+Added OSPI and eMMC Boot Mode presets to Board Interface
+Added Board Flow Support For Versal GTs
+IPs : xxv_ethernet, l_ethernet and axi_ethernet
+Modified cips 3.0 preset for better readability
+Enabled Inter Processor Interrupts
+Enabled PS I2C on PMC_MIO 46 and 47
+
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VMK180 Initial board support
+
diff --git a/boards/Xilinx/vmk180/production/3.1/part0_pins.xml b/boards/Xilinx/vmk180/production/3.1/part0_pins.xml
new file mode 100755
index 000000000..4b165121c
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.1/part0_pins.xml
@@ -0,0 +1,581 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vmk180/production/3.1/preset.xml b/boards/Xilinx/vmk180/production/3.1/preset.xml
new file mode 100755
index 000000000..b85561574
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.1/preset.xml
@@ -0,0 +1,780 @@
+
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+ Â Â Â Â Â
+ Â Â Â Â Â Â Â Â Â
+
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+ Â Â Â Â Â
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diff --git a/boards/Xilinx/vmk180/production/3.1/readme.txt b/boards/Xilinx/vmk180/production/3.1/readme.txt
new file mode 100755
index 000000000..7805dc9da
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.1/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvm1802-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vmk180/production/3.1/xitem.json b/boards/Xilinx/vmk180/production/3.1/xitem.json
new file mode 100755
index 000000000..cf08e8cc0
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vmk180",
+ "display": "Versal VMK180 Evaluation Platform",
+ "revision": "3.1",
+ "description": "Versal VMK180 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vmk180",
+ "search-keywords": [
+ "vmk180",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vmk180/production/3.2/LICENSE b/boards/Xilinx/vmk180/production/3.2/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vmk180/production/3.2/board.xml b/boards/Xilinx/vmk180/production/3.2/board.xml
new file mode 100755
index 000000000..99b505ab3
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.2/board.xml
@@ -0,0 +1,3416 @@
+
+
+
+
+
+
+
+ Versal VMK180 Evaluation Platform"
+
+
+
+
+ Rev B02
+
+
+ 3.2
+
+ Versal VMK180 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvm1802 FPGA
+
+
+
+
+
+
+
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+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
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+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
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+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
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+
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+
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+
+
+
+
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+
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+
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+
+
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+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty2_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
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+
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+
+
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+
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+
+
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+
+
+
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+
+
+
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+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Single lane GT interface for PCIe X1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
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+
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+
+
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+
+
+
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+
+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Eight lane GT interface for PCIe X8
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+ PCIE X1 on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+
+
+ PCIE on Bank103 GT01
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+
+ PCIE on Bank103 GT0
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+
+
+ PCIE X8 on Bank103 and Bank 104 GT
+
+
+
+
+ PCIE RX on Bank103 GTY0
+
+
+ PCIE TX on Bank103 GTY0
+
+
+ PCIE RX on Bank103 GTY1
+
+
+ PCIE TX on Bank103 GTY1
+
+
+
+ PCIE RX on Bank103 GTY2
+
+
+ PCIE TX on Bank103 GTY2
+
+
+ PCIE RX on Bank103 GTY3
+
+
+ PCIE TX on Bank103 GTY3
+
+
+
+
+ PCIE RX on Bank104 GTY0
+
+
+ PCIE TX on Bank104 GTY0
+
+
+ PCIE RX on Bank104 GTY1
+
+
+ PCIE TX on Bank104 GTY1
+
+
+
+ PCIE RX on Bank104 GTY2
+
+
+ PCIE TX on Bank104 GTY2
+
+
+ PCIE RX on Bank104 GTY3
+
+
+ PCIE TX on Bank104 GTY3
+
+
+
+ PCIE REFCLK on Bank 103"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vmk180/production/3.2/changelog.txt b/boards/Xilinx/vmk180/production/3.2/changelog.txt
new file mode 100755
index 000000000..cf5886141
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.2/changelog.txt
@@ -0,0 +1,36 @@
+######### VMK180 change log ##############
+3.2 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+3.1 - 2022.1_web
+Added board flow support for PCIe interface (X1,X2,X4 and X8 mode)
+Added MIO12 for OSPI preset - 2023.1
+
+3.0 - 2022.1
+Added OSPI and eMMC Boot Mode presets to Board Interface
+Added Board Flow Support For Versal GTs
+IPs : xxv_ethernet, l_ethernet and axi_ethernet
+Modified cips 3.0 preset for better readability
+Enabled Inter Processor Interrupts
+Enabled PS I2C on PMC_MIO 46 and 47
+
+2.2 - 2021.1
+Added support for CIPS 3.0
+Renamed CIPS board interface to ps_pmc_fixed_io
+Enabled Inter Processor Interrupts
+
+2.1 - 2020.3
+Updated speed bin and LPDDR4 frequency for triplet 2 & 4
+
+2.0 - 2020.2
+Production support
+
+1.1 - 2020.1
+Added IOSTANDARD to all clocks
+Fixed GPIO port polarities
+Fix added for LPDDR Controller 1 standalone usage
+
+
+1.0 - 2019.2
+VMK180 Initial board support
+
diff --git a/boards/Xilinx/vmk180/production/3.2/part0_pins.xml b/boards/Xilinx/vmk180/production/3.2/part0_pins.xml
new file mode 100755
index 000000000..9630b040f
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.2/part0_pins.xml
@@ -0,0 +1,581 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vmk180/production/3.2/preset.xml b/boards/Xilinx/vmk180/production/3.2/preset.xml
new file mode 100755
index 000000000..11347ca31
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.2/preset.xml
@@ -0,0 +1,810 @@
+
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+ Â Â Â Â Â
+ Â Â Â Â Â Â Â Â Â
+
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+ Â Â Â Â Â
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diff --git a/boards/Xilinx/vmk180/production/3.2/readme.txt b/boards/Xilinx/vmk180/production/3.2/readme.txt
new file mode 100755
index 000000000..7805dc9da
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.2/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvm1802-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vmk180/production/3.2/xitem.json b/boards/Xilinx/vmk180/production/3.2/xitem.json
new file mode 100755
index 000000000..7878c3d39
--- /dev/null
+++ b/boards/Xilinx/vmk180/production/3.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vmk180",
+ "display": "Versal VMK180 Evaluation Platform",
+ "revision": "3.2",
+ "description": "Versal VMK180 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vmk180",
+ "search-keywords": [
+ "vmk180",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vmk180_newl/production/1.0/LICENSE b/boards/Xilinx/vmk180_newl/production/1.0/LICENSE
new file mode 100644
index 000000000..bbb038fb7
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vmk180_newl/production/1.0/board.xml b/boards/Xilinx/vmk180_newl/production/1.0/board.xml
new file mode 100755
index 000000000..d061f5956
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.0/board.xml
@@ -0,0 +1,2181 @@
+
+
+
+
+
+
+
+ Versal VMK180 Evaluation Platform with New SD Level Shifter"
+
+
+
+
+ Rev B03
+
+
+ 1.0
+
+ Versal VMK180 Evaluation Platform with New SD Level Shifter
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvm1802 FPGA
+
+
+
+
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+
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+
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+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
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+
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ bank105_gty2_axi_eth
+
+
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+
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+ bank105_gty3_axi_eth
+
+
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+
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+
+
+ Four lane GT interface over qsfp1_connector
+
+
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+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
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+
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+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
diff --git a/boards/Xilinx/vmk180_newl/production/1.0/changelog.txt b/boards/Xilinx/vmk180_newl/production/1.0/changelog.txt
new file mode 100755
index 000000000..cfda396c3
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### VMK180 change log ##############
+1.0 - 2022.1
+VMK180 Board Files having support for new SD level shifter
+
diff --git a/boards/Xilinx/vmk180_newl/production/1.0/part0_pins.xml b/boards/Xilinx/vmk180_newl/production/1.0/part0_pins.xml
new file mode 100755
index 000000000..f668703e1
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.0/part0_pins.xml
@@ -0,0 +1,542 @@
+
+
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+
diff --git a/boards/Xilinx/vmk180_newl/production/1.0/preset.xml b/boards/Xilinx/vmk180_newl/production/1.0/preset.xml
new file mode 100755
index 000000000..eb962931e
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.0/preset.xml
@@ -0,0 +1,715 @@
+
+
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+ Â Â Â Â Â
+
+ Â Â Â Â Â Â Â Â Â
+
+
+
+ Â Â Â Â Â
+
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diff --git a/boards/Xilinx/vmk180_newl/production/1.0/readme.txt b/boards/Xilinx/vmk180_newl/production/1.0/readme.txt
new file mode 100755
index 000000000..7805dc9da
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.0/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvm1802-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vmk180_newl/production/1.0/xitem.json b/boards/Xilinx/vmk180_newl/production/1.0/xitem.json
new file mode 100755
index 000000000..255fe0796
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vmk180_newl",
+ "display": "Versal VMK180 Evaluation Platform with New SD Level Shifter",
+ "revision": "1.0",
+ "description": "Versal VMK180 Evaluation Platform with New SD Level Shifter",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vmk180",
+ "search-keywords": [
+ "vmk180_newl",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vmk180_newl/production/1.1/LICENSE b/boards/Xilinx/vmk180_newl/production/1.1/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vmk180_newl/production/1.1/board.xml b/boards/Xilinx/vmk180_newl/production/1.1/board.xml
new file mode 100755
index 000000000..b17bdeeee
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.1/board.xml
@@ -0,0 +1,2181 @@
+
+
+
+
+
+
+
+ Versal VMK180 Evaluation Platform with New SD Level Shifter"
+
+
+
+
+ Rev B03
+
+
+ 1.1
+
+ Versal VMK180 Evaluation Platform with New SD Level Shifter
+
+
+
+
+
+
+
+
+
+
+
+
+
+ xcvm1802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
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+
+
+
+
+
+
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+
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+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty2_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ bank105_gty3_axi_eth
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Four lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Two lane GT interface over qsfp1_connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB DDR4 SDRAM DIMM1
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 200 MHz oscillator used for DDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential 100 MHz oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+ DC PL GPIO
+
+
+
+ System Controller GPIO
+
+
+
+ AXI_ethernet on Bank 105 GTY2
+
+
+
+ AXI_ethernet RX on Bank 105 GTY2
+
+
+
+ AXI_ethernet TX on Bank 105 GTY2
+
+
+
+
+ AXI_ethernet on Bank 105 GTY3
+
+
+
+ AXI_ethernet RX on Bank 105 GTY3
+
+
+
+ AXI_ethernet TX on Bank 105 GTY3
+
+
+
+
+
+ XXV on Bank105 GTY2
+
+
+
+ XXV RX on Bank105 GTY2
+
+
+
+ XXV TX on Bank105 GTY2"
+
+
+
+ XXV on Bank105 GTY3
+
+
+
+ XXV RX on Bank105 GTY3
+
+
+
+ XXV TX on Bank105 GTY3
+
+
+
+ L_Ethernet with 50G on Bank105 GTY2,GTY3
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY2
+
+
+
+ L_Ethernet RX with 50G on Bank105 GTY3
+
+
+
+ L_Ethernet TX with 50G on Bank105 GTY3
+
+
+
+ GT REFCLK0 on Bank 105"
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vmk180_newl/production/1.1/changelog.txt b/boards/Xilinx/vmk180_newl/production/1.1/changelog.txt
new file mode 100755
index 000000000..1963f3999
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.1/changelog.txt
@@ -0,0 +1,10 @@
+######### VMK180 change log ##############
+1.1 - 2024.2
+Corrected the SD1_DATA_TRANSFER_MODE format
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0 - 2022.1
+VMK180 Board Files having support for new SD level shifter
+Added MIO12 for OSPI preset - 2023.1
+
diff --git a/boards/Xilinx/vmk180_newl/production/1.1/part0_pins.xml b/boards/Xilinx/vmk180_newl/production/1.1/part0_pins.xml
new file mode 100755
index 000000000..84374bda8
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.1/part0_pins.xml
@@ -0,0 +1,542 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/vmk180_newl/production/1.1/preset.xml b/boards/Xilinx/vmk180_newl/production/1.1/preset.xml
new file mode 100755
index 000000000..8ed6d0444
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.1/preset.xml
@@ -0,0 +1,746 @@
+
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+ Â Â Â Â Â
+
+ Â Â Â Â Â Â Â Â Â
+
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+ Â Â Â Â Â
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diff --git a/boards/Xilinx/vmk180_newl/production/1.1/readme.txt b/boards/Xilinx/vmk180_newl/production/1.1/readme.txt
new file mode 100755
index 000000000..7805dc9da
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.1/readme.txt
@@ -0,0 +1,4 @@
+Validate that part xcvm1802-vsva2197-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vmk180_newl/production/1.1/xitem.json b/boards/Xilinx/vmk180_newl/production/1.1/xitem.json
new file mode 100755
index 000000000..999ffe874
--- /dev/null
+++ b/boards/Xilinx/vmk180_newl/production/1.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vmk180_newl",
+ "display": "Versal VMK180 Evaluation Platform with New SD Level Shifter",
+ "revision": "1.1",
+ "description": "Versal VMK180 Evaluation Platform with New SD Level Shifter",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vmk180",
+ "search-keywords": [
+ "vmk180_newl",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vpk120/production/1.0/LICENSE b/boards/Xilinx/vpk120/production/1.0/LICENSE
new file mode 100644
index 000000000..bbb038fb7
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2019, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vpk120/production/1.0/README.md b/boards/Xilinx/vpk120/production/1.0/README.md
new file mode 100755
index 000000000..30762fa35
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.0/README.md
@@ -0,0 +1,4 @@
+Validate that the xcvp1202-vsva2785-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vpk120/production/1.0/board.xml b/boards/Xilinx/vpk120/production/1.0/board.xml
new file mode 100755
index 000000000..6eec1747c
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.0/board.xml
@@ -0,0 +1,1798 @@
+
+
+
+
+
+
+
+
+ Versal VPK120 Evaluation Platform"
+
+
+
+
+ Rev B01
+
+
+ 1.0
+
+ Versal VPK120 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVP1202 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
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+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
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+
+
+ 16GBIT LPDDR4 memory
+
+
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+
+
+ 16GBIT LPDDR4 memory
+
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+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
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+
diff --git a/boards/Xilinx/vpk120/production/1.0/changelog.txt b/boards/Xilinx/vpk120/production/1.0/changelog.txt
new file mode 100755
index 000000000..d9720ece4
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.0/changelog.txt
@@ -0,0 +1,7 @@
+######### VPK120 change log ##############
+1.0
+
+Initial board file for vpk120 pre-production and production (2022.1_web)
+
+
+
diff --git a/boards/Xilinx/vpk120/production/1.0/part0_pins.xml b/boards/Xilinx/vpk120/production/1.0/part0_pins.xml
new file mode 100755
index 000000000..0bc68c893
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.0/part0_pins.xml
@@ -0,0 +1,686 @@
+
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+
diff --git a/boards/Xilinx/vpk120/production/1.0/preset.xml b/boards/Xilinx/vpk120/production/1.0/preset.xml
new file mode 100755
index 000000000..b7e426192
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.0/preset.xml
@@ -0,0 +1,303 @@
+
+
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diff --git a/boards/Xilinx/vpk120/production/1.0/vpk120_image.jpg b/boards/Xilinx/vpk120/production/1.0/vpk120_image.jpg
new file mode 100755
index 000000000..173b7236d
Binary files /dev/null and b/boards/Xilinx/vpk120/production/1.0/vpk120_image.jpg differ
diff --git a/boards/Xilinx/vpk120/production/1.0/xitem.json b/boards/Xilinx/vpk120/production/1.0/xitem.json
new file mode 100755
index 000000000..3174d6430
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vpk120",
+ "display": "Versal VPK120 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Versal VPK120 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vpk120",
+ "search-keywords": [
+ "vpk120",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vpk120/production/1.1/LICENSE b/boards/Xilinx/vpk120/production/1.1/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vpk120/production/1.1/README.md b/boards/Xilinx/vpk120/production/1.1/README.md
new file mode 100755
index 000000000..30762fa35
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.1/README.md
@@ -0,0 +1,4 @@
+Validate that the xcvp1202-vsva2785-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vpk120/production/1.1/board.xml b/boards/Xilinx/vpk120/production/1.1/board.xml
new file mode 100755
index 000000000..353610325
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.1/board.xml
@@ -0,0 +1,1798 @@
+
+
+
+
+
+
+
+
+ Versal VPK120 Evaluation Platform"
+
+
+
+
+ Rev B01
+
+
+ 1.1
+
+ Versal VPK120 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVP1202 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ Versal CIPS component
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+ 16GBIT LPDDR4 memory
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+ 16GBIT LPDDR4 memory
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+ 16GBIT LPDDR4 memory
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+ LVDS differential oscillator used for LPDDR4 Controller
+
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+ LVDS differential oscillator used for LPDDR4 Controller
+
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+
+ LVDS differential oscillator used for LPDDR4 Controller
+
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+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
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+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
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+ GPIO Push Buttons
+
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+ GPIO DIP Switches
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+ GPIO LEDs
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+ System Controller GPIO
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diff --git a/boards/Xilinx/vpk120/production/1.1/changelog.txt b/boards/Xilinx/vpk120/production/1.1/changelog.txt
new file mode 100755
index 000000000..03081f42c
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.1/changelog.txt
@@ -0,0 +1,9 @@
+######### VPK120 change log ##############
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0
+Initial board file for vpk120 pre-production and production (2022.1_web)
+
+
+
diff --git a/boards/Xilinx/vpk120/production/1.1/part0_pins.xml b/boards/Xilinx/vpk120/production/1.1/part0_pins.xml
new file mode 100755
index 000000000..fd5100826
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.1/part0_pins.xml
@@ -0,0 +1,686 @@
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diff --git a/boards/Xilinx/vpk120/production/1.1/preset.xml b/boards/Xilinx/vpk120/production/1.1/preset.xml
new file mode 100755
index 000000000..7612a7698
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.1/preset.xml
@@ -0,0 +1,312 @@
+
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diff --git a/boards/Xilinx/vpk120/production/1.1/vpk120_image.jpg b/boards/Xilinx/vpk120/production/1.1/vpk120_image.jpg
new file mode 100755
index 000000000..173b7236d
Binary files /dev/null and b/boards/Xilinx/vpk120/production/1.1/vpk120_image.jpg differ
diff --git a/boards/Xilinx/vpk120/production/1.1/xitem.json b/boards/Xilinx/vpk120/production/1.1/xitem.json
new file mode 100755
index 000000000..82c492910
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vpk120",
+ "display": "Versal VPK120 Evaluation Platform",
+ "revision": "1.1",
+ "description": "Versal VPK120 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vpk120",
+ "search-keywords": [
+ "vpk120",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vpk120/production/1.2/LICENSE b/boards/Xilinx/vpk120/production/1.2/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vpk120/production/1.2/README.md b/boards/Xilinx/vpk120/production/1.2/README.md
new file mode 100755
index 000000000..30762fa35
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.2/README.md
@@ -0,0 +1,4 @@
+Validate that the xcvp1202-vsva2785-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vpk120/production/1.2/board.xml b/boards/Xilinx/vpk120/production/1.2/board.xml
new file mode 100755
index 000000000..8257f3543
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.2/board.xml
@@ -0,0 +1,1800 @@
+
+
+
+
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+
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+ Versal VPK120 ES1 Evaluation Platform"
+
+
+
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+ Rev B01
+
+
+ 1.2
+
+ Versal VPK120 Evaluation Platform
+
+
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+ XCVP1202 FPGA
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+
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
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+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
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+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
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+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
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+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
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+
diff --git a/boards/Xilinx/vpk120/production/1.2/changelog.txt b/boards/Xilinx/vpk120/production/1.2/changelog.txt
new file mode 100755
index 000000000..2c32f945f
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.2/changelog.txt
@@ -0,0 +1,12 @@
+######### VPK120 Rev B change log ##############
+1.2 - 2023.1
+Corrected board files to include support for multiple parts, sysmon_i2c , sysctrl_uart and pcie reset pin location
+
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0 - 2022.1_web
+Initial board file for vpk120 pre-production and production
+
+
+
diff --git a/boards/Xilinx/vpk120/production/1.2/part0_pins.xml b/boards/Xilinx/vpk120/production/1.2/part0_pins.xml
new file mode 100755
index 000000000..fd5100826
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.2/part0_pins.xml
@@ -0,0 +1,686 @@
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diff --git a/boards/Xilinx/vpk120/production/1.2/preset.xml b/boards/Xilinx/vpk120/production/1.2/preset.xml
new file mode 100755
index 000000000..016824cc8
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.2/preset.xml
@@ -0,0 +1,310 @@
+
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diff --git a/boards/Xilinx/vpk120/production/1.2/xitem.json b/boards/Xilinx/vpk120/production/1.2/xitem.json
new file mode 100755
index 000000000..5ac6b8558
--- /dev/null
+++ b/boards/Xilinx/vpk120/production/1.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vpk120",
+ "display": "Versal VPK120 Evaluation Platform",
+ "revision": "1.2",
+ "description": "Versal VPK120 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vpk120",
+ "search-keywords": [
+ "vpk120",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/vpk180/production/1.0/LICENSE b/boards/Xilinx/vpk180/production/1.0/LICENSE
new file mode 100644
index 000000000..2a6926ec7
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices,, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vpk180/production/1.0/README.md b/boards/Xilinx/vpk180/production/1.0/README.md
new file mode 100755
index 000000000..3be29022d
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.0/README.md
@@ -0,0 +1,4 @@
+Validate that the xcvp1802-lsvc4072-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vpk180/production/1.0/board.xml b/boards/Xilinx/vpk180/production/1.0/board.xml
new file mode 100755
index 000000000..de8745273
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.0/board.xml
@@ -0,0 +1,1810 @@
+
+
+
+
+
+
+
+
+ Versal VPK180 Evaluation Platform"
+
+
+
+
+ Rev A01
+
+
+ 1.0
+
+ Versal VPK180 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVP1802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/vpk180/production/1.0/changelog.txt b/boards/Xilinx/vpk180/production/1.0/changelog.txt
new file mode 100755
index 000000000..7fce2afbe
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.0/changelog.txt
@@ -0,0 +1,7 @@
+######### VPK180 change log ##############
+1.0 - 2022.2_web
+Initial board file support - vpk180 production
+
+
+
+
diff --git a/boards/Xilinx/vpk180/production/1.0/part0_pins.xml b/boards/Xilinx/vpk180/production/1.0/part0_pins.xml
new file mode 100755
index 000000000..8afd1bf0d
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.0/part0_pins.xml
@@ -0,0 +1,702 @@
+
+
+
+
+
+
+
+
+
+
+
+
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+
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diff --git a/boards/Xilinx/vpk180/production/1.0/preset.xml b/boards/Xilinx/vpk180/production/1.0/preset.xml
new file mode 100755
index 000000000..dca3d6c94
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.0/preset.xml
@@ -0,0 +1,323 @@
+
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diff --git a/boards/Xilinx/vpk180/production/1.0/xitem.json b/boards/Xilinx/vpk180/production/1.0/xitem.json
new file mode 100755
index 000000000..3d79e53d6
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vpk180",
+ "display": "Versal VPK180 Evaluation Platform",
+ "revision": "1.0",
+ "description": "Versal VPK180 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vpk180",
+ "search-keywords": [
+ "vpk180",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vpk180/production/1.1/LICENSE b/boards/Xilinx/vpk180/production/1.1/LICENSE
new file mode 100755
index 000000000..2a6926ec7
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices,, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vpk180/production/1.1/README.md b/boards/Xilinx/vpk180/production/1.1/README.md
new file mode 100755
index 000000000..3be29022d
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.1/README.md
@@ -0,0 +1,4 @@
+Validate that the xcvp1802-lsvc4072-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vpk180/production/1.1/board.xml b/boards/Xilinx/vpk180/production/1.1/board.xml
new file mode 100755
index 000000000..0e3afa878
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.1/board.xml
@@ -0,0 +1,1810 @@
+
+
+
+
+
+
+
+
+ Versal VPK180 Evaluation Platform"
+
+
+
+
+ Rev A01
+
+
+ 1.1
+
+ Versal VPK180 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVP1802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
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+
+
+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
diff --git a/boards/Xilinx/vpk180/production/1.1/changelog.txt b/boards/Xilinx/vpk180/production/1.1/changelog.txt
new file mode 100755
index 000000000..335ba801a
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.1/changelog.txt
@@ -0,0 +1,10 @@
+######### VPK180 change log ##############
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0 - 2023.1
+Initial board file support - vpk180 production
+Corrected the format of PCIe reset pins for CIPS preset
+
+
+
diff --git a/boards/Xilinx/vpk180/production/1.1/part0_pins.xml b/boards/Xilinx/vpk180/production/1.1/part0_pins.xml
new file mode 100755
index 000000000..8afd1bf0d
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.1/part0_pins.xml
@@ -0,0 +1,702 @@
+
+
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+
diff --git a/boards/Xilinx/vpk180/production/1.1/preset.xml b/boards/Xilinx/vpk180/production/1.1/preset.xml
new file mode 100755
index 000000000..45bf0e57c
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.1/preset.xml
@@ -0,0 +1,316 @@
+
+
+
+
+
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+
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+
diff --git a/boards/Xilinx/vpk180/production/1.1/xitem.json b/boards/Xilinx/vpk180/production/1.1/xitem.json
new file mode 100755
index 000000000..a7db088ca
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.1/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vpk180",
+ "display": "Versal VPK180 Evaluation Platform",
+ "revision": "1.1",
+ "description": "Versal VPK180 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vpk180",
+ "search-keywords": [
+ "vpk180",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/vpk180/production/1.2/LICENSE b/boards/Xilinx/vpk180/production/1.2/LICENSE
new file mode 100644
index 000000000..2a6926ec7
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices,, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/vpk180/production/1.2/README.md b/boards/Xilinx/vpk180/production/1.2/README.md
new file mode 100644
index 000000000..3be29022d
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.2/README.md
@@ -0,0 +1,4 @@
+Validate that the xcvp1802-lsvc4072-2MP-e-S is available in your Vivado installation.
+Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+For more information please refer to user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/vpk180/production/1.2/board.xml b/boards/Xilinx/vpk180/production/1.2/board.xml
new file mode 100644
index 000000000..18cc242ef
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.2/board.xml
@@ -0,0 +1,1810 @@
+
+
+
+
+
+
+
+
+ Versal VPK180 Evaluation Platform"
+
+
+
+
+ Rev A01
+
+
+ 1.2
+
+ Versal VPK180 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+ XCVP1802 FPGA
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+ LPDDR4 board interface, it can use AXI_NoC IP for connection.
+
+
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+
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+
+
+
+
+
+ Versal CIPS component
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
+
+
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+
+
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+
+
+
+
+
+
+ 16GBIT LPDDR4 memory
+
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+
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+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ LVDS differential oscillator used for LPDDR4 Controller
+
+
+
+
+
+
+ USB-to-UART Bridge, which allows serial communication to host computer with a USB port
+
+
+
+
+
+
+
+ System Controller USB-to-UART Bridge, supported only for Rev_B01 board
+
+
+
+
+
+
+
+
+ GPIO Push Buttons
+
+
+
+ GPIO DIP Switches
+
+
+
+ GPIO LEDs
+
+
+
+
+
+
+
+ System Controller GPIO
+
+
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+
diff --git a/boards/Xilinx/vpk180/production/1.2/changelog.txt b/boards/Xilinx/vpk180/production/1.2/changelog.txt
new file mode 100644
index 000000000..ac68a1b37
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.2/changelog.txt
@@ -0,0 +1,13 @@
+######### VPK180 change log ##############
+1.2 - 2023.2
+Corrected Memory clock period to support XPIO banks performance.
+
+1.1 - 2023.1
+Corrected the format of PCIe reset pins for CIPS preset
+
+1.0 - 2023.1
+Initial board file support - vpk180 production
+Corrected the format of PCIe reset pins for CIPS preset
+
+
+
diff --git a/boards/Xilinx/vpk180/production/1.2/part0_pins.xml b/boards/Xilinx/vpk180/production/1.2/part0_pins.xml
new file mode 100644
index 000000000..8afd1bf0d
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.2/part0_pins.xml
@@ -0,0 +1,702 @@
+
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+
diff --git a/boards/Xilinx/vpk180/production/1.2/preset.xml b/boards/Xilinx/vpk180/production/1.2/preset.xml
new file mode 100644
index 000000000..7e8b2c576
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.2/preset.xml
@@ -0,0 +1,316 @@
+
+
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+
diff --git a/boards/Xilinx/vpk180/production/1.2/xitem.json b/boards/Xilinx/vpk180/production/1.2/xitem.json
new file mode 100644
index 000000000..8639a1223
--- /dev/null
+++ b/boards/Xilinx/vpk180/production/1.2/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "vpk180",
+ "display": "Versal VPK180 Evaluation Platform",
+ "revision": "1.2",
+ "description": "Versal VPK180 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/vpk180",
+ "search-keywords": [
+ "vpk180",
+ "xilinx.com",
+ "board",
+ "Single Part"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/xm105/1.0/LICENSE b/boards/Xilinx/xm105/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/xm105/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/xm105/1.0/board.xml b/boards/Xilinx/xm105/1.0/board.xml
new file mode 100644
index 000000000..fa2bc0eaa
--- /dev/null
+++ b/boards/Xilinx/xm105/1.0/board.xml
@@ -0,0 +1,530 @@
+
+ 1.0
+ FMC XM105 Debug Card
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
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+
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+
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+
+
+
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+
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+
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+
+
diff --git a/boards/Xilinx/xm105/1.0/xitem.json b/boards/Xilinx/xm105/1.0/xitem.json
new file mode 100644
index 000000000..df975d1f2
--- /dev/null
+++ b/boards/Xilinx/xm105/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "xm105",
+ "display": "FMC XM105 Debug Card",
+ "revision": "1.0",
+ "description": "FMC XM105 Debug Card",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "FMCs & Accessories",
+ "logo": "",
+ "website": "www.xilinx.com/SOM",
+ "search-keywords": [
+ "FMC",
+ "xilinx.com",
+ "board",
+ "XM105"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zc702/1.4/LICENSE b/boards/Xilinx/zc702/1.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zc702/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zc702/1.4/board.xml b/boards/Xilinx/zc702/1.4/board.xml
new file mode 100644
index 000000000..7c3da9b59
--- /dev/null
+++ b/boards/Xilinx/zc702/1.4/board.xml
@@ -0,0 +1,488 @@
+
+
+
+
+
+
+ ZC702 Board File Image
+
+
+
+ 1.0
+
+ 1.4
+ Zynq 7000 ZC702 Evaluation Board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DIP Switches 1 to 0
+
+
+
+ Push Buttons, S N, Active High
+
+
+
+ I2C
+
+
+ LEDs, 3 to 0, Active High
+
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/zc702/1.4/changelog.txt b/boards/Xilinx/zc702/1.4/changelog.txt
new file mode 100644
index 000000000..f794bd94b
--- /dev/null
+++ b/boards/Xilinx/zc702/1.4/changelog.txt
@@ -0,0 +1,6 @@
+######### ZC702 Change log ##############
+1.4
+Enabled board support for push buttons
+
+1.3
+Added FMC support
diff --git a/boards/Xilinx/zc702/1.4/part0_pins.xml b/boards/Xilinx/zc702/1.4/part0_pins.xml
new file mode 100644
index 000000000..d1fea900e
--- /dev/null
+++ b/boards/Xilinx/zc702/1.4/part0_pins.xml
@@ -0,0 +1,178 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/zc702/1.4/preset.xml b/boards/Xilinx/zc702/1.4/preset.xml
new file mode 100644
index 000000000..0f233b6be
--- /dev/null
+++ b/boards/Xilinx/zc702/1.4/preset.xml
@@ -0,0 +1,166 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/zc702/1.4/xitem.json b/boards/Xilinx/zc702/1.4/xitem.json
new file mode 100644
index 000000000..ade3fd11e
--- /dev/null
+++ b/boards/Xilinx/zc702/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zc702",
+ "display": "Zynq 7000 ZC702 Evaluation Board",
+ "revision": "1.4",
+ "description": "Zynq 7000 ZC702 Evaluation Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zc702_board.jpg",
+ "website": "http://www.xilinx.com/zc702",
+ "search-keywords": [
+ "zc702",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zc702/1.4/zc702_board.jpg b/boards/Xilinx/zc702/1.4/zc702_board.jpg
new file mode 100644
index 000000000..5173f9edc
Binary files /dev/null and b/boards/Xilinx/zc702/1.4/zc702_board.jpg differ
diff --git a/boards/Xilinx/zc706/1.4/LICENSE b/boards/Xilinx/zc706/1.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zc706/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zc706/1.4/board.xml b/boards/Xilinx/zc706/1.4/board.xml
new file mode 100644
index 000000000..fc4fc4a2b
--- /dev/null
+++ b/boards/Xilinx/zc706/1.4/board.xml
@@ -0,0 +1,841 @@
+
+
+
+
+
+
+ ZC706 Board File Image
+
+
+
+ 1.1
+
+ 1.4
+ Zynq 7000 ZC706 Evaluation Board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+ DDR3 board interface, it can use MIG IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ true
+ false
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ false
+ true
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1 GB DDR3 memory SODIMM
+
+
+
+
+
+
+ DIP Switches 3 to 0
+
+
+ Push Buttons, Active High
+
+
+ The primary purpose of this clock is to support CPRI/OBSAI applications that perform clock recovery from a user-supplied SFP/SFP+ module and use the jitter attenuated recovered clock to drive the reference clock inputs of a GTX transceiver
+
+
+ LEDs, 3 to 0, Active High
+
+
+
+ CPU Reset Push Button, Active High
+
+
+ PHY outside the board connected through sfp
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PHY outside the board connected through sma
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SMA MGT Clock, 125 MHz
+
+
+ 2.5V LVDS differential 200 MHz oscillator used as system differential clock on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/zc706/1.4/changelog.txt b/boards/Xilinx/zc706/1.4/changelog.txt
new file mode 100644
index 000000000..bb346a14d
--- /dev/null
+++ b/boards/Xilinx/zc706/1.4/changelog.txt
@@ -0,0 +1,5 @@
+######### ZC706 Change log ##############
+
+1.4
+Added FMC support
+
diff --git a/boards/Xilinx/zc706/1.4/mig.prj b/boards/Xilinx/zc706/1.4/mig.prj
new file mode 100644
index 000000000..d98eee717
--- /dev/null
+++ b/boards/Xilinx/zc706/1.4/mig.prj
@@ -0,0 +1,203 @@
+
+
+
+ design_1_mig_7series_1_0
+ 1
+ 1
+ OFF
+ 1024
+ ON
+ Enabled
+ xc7z045-ffg900/-2
+ 1.9
+ Differential
+ Use System Clock
+ ACTIVE HIGH
+ FALSE
+ 0
+ 50 Ohms
+ 1
+
+ DDR3_SDRAM/SODIMMs/MT8JTF12864HZ-1G6
+ 1250
+ 1.8V
+ 4:1
+ 200
+ 1
+ 8.000
+ 1
+ 1
+ 1
+ 1
+ 64
+ 1
+ 1
+ Disabled
+ Normal
+ FALSE
+
+ 14
+ 10
+ 3
+ 1.5V
+ BANK_ROW_COLUMN
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8 - Fixed
+ Sequential
+ 6
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Enable
+ RZQ/6
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 5
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 32
+ 512
+ 2
+ 0
+
+
+
+
diff --git a/boards/Xilinx/zc706/1.4/part0_pins.xml b/boards/Xilinx/zc706/1.4/part0_pins.xml
new file mode 100644
index 000000000..02fee8bee
--- /dev/null
+++ b/boards/Xilinx/zc706/1.4/part0_pins.xml
@@ -0,0 +1,227 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/zc706/1.4/preset.xml b/boards/Xilinx/zc706/1.4/preset.xml
new file mode 100644
index 000000000..f0c63578c
--- /dev/null
+++ b/boards/Xilinx/zc706/1.4/preset.xml
@@ -0,0 +1,301 @@
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diff --git a/boards/Xilinx/zc706/1.4/xitem.json b/boards/Xilinx/zc706/1.4/xitem.json
new file mode 100644
index 000000000..8f9fffc3d
--- /dev/null
+++ b/boards/Xilinx/zc706/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "ZC706",
+ "display": "Zynq 7000 ZC706 Evaluation Board",
+ "revision": "1.4",
+ "description": "Zynq 7000 ZC706 Evaluation Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zc706_board.jpg",
+ "website": "http://www.xilinx.com/zc706",
+ "search-keywords": [
+ "zc706",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zc706/1.4/zc706_board.jpg b/boards/Xilinx/zc706/1.4/zc706_board.jpg
new file mode 100644
index 000000000..69bb54edf
Binary files /dev/null and b/boards/Xilinx/zc706/1.4/zc706_board.jpg differ
diff --git a/boards/Xilinx/zcu102/3.3/LICENSE b/boards/Xilinx/zcu102/3.3/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu102/3.3/board.xml b/boards/Xilinx/zcu102/3.3/board.xml
new file mode 100644
index 000000000..ef3d66c48
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.3/board.xml
@@ -0,0 +1,913 @@
+
+
+
+
+
+ ZCU102 Board File Image
+
+
+
+ 1.0
+ 1.1
+
+ 3.3
+ Zynq UltraScale+ ZCU102 Evaluation Board
+
+
+
+
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+
+ FPGA part on the board
+
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+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
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+
+ 8-position user DIP Switch
+
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+
+
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+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+ PL I2C0
+
+
+ PL I2C1
+
+
+ 2GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+
+
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diff --git a/boards/Xilinx/zcu102/3.3/changelog.txt b/boards/Xilinx/zcu102/3.3/changelog.txt
new file mode 100644
index 000000000..1b306db7b
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.3/changelog.txt
@@ -0,0 +1,21 @@
+3.3
+Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset
+Added 1.1 as compatible board rev
+
+3.2
+Updated DDR4 CLK IOSTANDARDs
+
+3.1
+Updated PS_REF_CLK frequency to match ZCU102 board UG
+Added FMC support
+
+3.0
+production device support
+Revised MPSOC clock settings for Display port
+APU frequency chnaged from 1100M to 1200Mhz
+
+
+2.1
+GT configuration revised from DP-DP-USB-SATA to PCIe-DP-USB-SATA
+PMU GPI is disbaled
+
diff --git a/boards/Xilinx/zcu102/3.3/part0_pins.xml b/boards/Xilinx/zcu102/3.3/part0_pins.xml
new file mode 100644
index 000000000..dcb6721f7
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.3/part0_pins.xml
@@ -0,0 +1,338 @@
+
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diff --git a/boards/Xilinx/zcu102/3.3/preset.xml b/boards/Xilinx/zcu102/3.3/preset.xml
new file mode 100644
index 000000000..0c613d9a7
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.3/preset.xml
@@ -0,0 +1,448 @@
+
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diff --git a/boards/Xilinx/zcu102/3.3/xitem.json b/boards/Xilinx/zcu102/3.3/xitem.json
new file mode 100644
index 000000000..4120e31a7
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu102",
+ "display": "Zynq UltraScale+ ZCU102 Evaluation Board",
+ "revision": "3.3",
+ "description": "Zynq UltraScale+ ZCU102 Evaluation Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu102_board.jpeg",
+ "website": "www.xilinx.com/zcu102",
+ "search-keywords": [
+ "zcu102",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu102/3.3/zcu102_board.jpeg b/boards/Xilinx/zcu102/3.3/zcu102_board.jpeg
new file mode 100644
index 000000000..4679f7a21
Binary files /dev/null and b/boards/Xilinx/zcu102/3.3/zcu102_board.jpeg differ
diff --git a/boards/Xilinx/zcu102/3.4/LICENSE b/boards/Xilinx/zcu102/3.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu102/3.4/board.xml b/boards/Xilinx/zcu102/3.4/board.xml
new file mode 100755
index 000000000..2218fd554
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.4/board.xml
@@ -0,0 +1,1049 @@
+
+
+
+
+
+
+ ZCU102 Board File Image
+
+
+
+ 1.0
+ 1.1
+
+ 3.4
+ Zynq UltraScale+ ZCU102 Evaluation Board
+
+
+
+
+
+
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+
+ FPGA part on the board
+
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+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
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+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
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+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
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+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+ PL I2C0
+
+
+ PL I2C1
+
+
+ 2GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+
+
+
+
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+
+
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diff --git a/boards/Xilinx/zcu102/3.4/changelog.txt b/boards/Xilinx/zcu102/3.4/changelog.txt
new file mode 100755
index 000000000..20d05c11c
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.4/changelog.txt
@@ -0,0 +1,24 @@
+3.4
+Added New DDR4 Memory Part MT40A256M16LY-062E support
+
+3.3
+Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset
+Added 1.1 as compatible board rev
+
+3.2
+Updated DDR4 CLK IOSTANDARDs
+
+3.1
+Updated PS_REF_CLK frequency to match ZCU102 board UG
+Added FMC support
+
+3.0
+production device support
+Revised MPSOC clock settings for Display port
+APU frequency chnaged from 1100M to 1200Mhz
+
+
+2.1
+GT configuration revised from DP-DP-USB-SATA to PCIe-DP-USB-SATA
+PMU GPI is disbaled
+
diff --git a/boards/Xilinx/zcu102/3.4/part0_pins.xml b/boards/Xilinx/zcu102/3.4/part0_pins.xml
new file mode 100755
index 000000000..b8065cfe2
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.4/part0_pins.xml
@@ -0,0 +1,338 @@
+
+
+
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+
diff --git a/boards/Xilinx/zcu102/3.4/preset.xml b/boards/Xilinx/zcu102/3.4/preset.xml
new file mode 100755
index 000000000..433b7af97
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.4/preset.xml
@@ -0,0 +1,461 @@
+
+
+
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diff --git a/boards/Xilinx/zcu102/3.4/xitem.json b/boards/Xilinx/zcu102/3.4/xitem.json
new file mode 100755
index 000000000..83726b242
--- /dev/null
+++ b/boards/Xilinx/zcu102/3.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu102",
+ "display": "Zynq UltraScale+ ZCU102 Evaluation Board",
+ "revision": "3.4",
+ "description": "Zynq UltraScale+ ZCU102 Evaluation Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu102_board.jpeg",
+ "website": "www.xilinx.com/zcu102",
+ "search-keywords": [
+ "zcu102",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu102/3.4/zcu102_board.jpeg b/boards/Xilinx/zcu102/3.4/zcu102_board.jpeg
new file mode 100755
index 000000000..4679f7a21
Binary files /dev/null and b/boards/Xilinx/zcu102/3.4/zcu102_board.jpeg differ
diff --git a/boards/Xilinx/zcu104/1.1/LICENSE b/boards/Xilinx/zcu104/1.1/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu104/1.1/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu104/1.1/board.xml b/boards/Xilinx/zcu104/1.1/board.xml
new file mode 100644
index 000000000..2569f5d44
--- /dev/null
+++ b/boards/Xilinx/zcu104/1.1/board.xml
@@ -0,0 +1,667 @@
+
+
+
+
+
+
+ ZCU104 Board File Image
+
+
+
+
+ RevA
+ RevB
+ RevC
+
+
+ 1.1
+
+ Zynq UltraScale+ ZCU104 Evaluation Board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4-Position User DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C
+
+
+
+
+ 2GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 3 to 0
+
+
+
+ LEDs, 3 to 0, Active High
+
+
+
+ Push Buttons, 3 to 0, Active High
+
+
+
+
+
+
+
+
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+
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+
diff --git a/boards/Xilinx/zcu104/1.1/changelog.txt b/boards/Xilinx/zcu104/1.1/changelog.txt
new file mode 100644
index 000000000..b19dd52cf
--- /dev/null
+++ b/boards/Xilinx/zcu104/1.1/changelog.txt
@@ -0,0 +1,11 @@
+**********ZCU104 changelog **************
+1.1
+Removed MIG IO attributes
+
+----Dec 13(2018.1) ---------
+Enabled PLDDR4 and FMC
+
+Int_1.0
+Internal support for ZCU104 with MPSoC, a PL clock, CPU reset interfaces
+
+
diff --git a/boards/Xilinx/zcu104/1.1/part0_pins.xml b/boards/Xilinx/zcu104/1.1/part0_pins.xml
new file mode 100644
index 000000000..bbfdd6f20
--- /dev/null
+++ b/boards/Xilinx/zcu104/1.1/part0_pins.xml
@@ -0,0 +1,238 @@
+
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diff --git a/boards/Xilinx/zcu104/1.1/preset.xml b/boards/Xilinx/zcu104/1.1/preset.xml
new file mode 100644
index 000000000..d40af6b4d
--- /dev/null
+++ b/boards/Xilinx/zcu104/1.1/preset.xml
@@ -0,0 +1,457 @@
+
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+
diff --git a/boards/Xilinx/zcu104/1.1/xitem.json b/boards/Xilinx/zcu104/1.1/xitem.json
new file mode 100644
index 000000000..82e9bbd23
--- /dev/null
+++ b/boards/Xilinx/zcu104/1.1/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu104",
+ "display": "Zynq UltraScale+ ZCU104 Evaluation Board",
+ "revision": "1.1",
+ "description": "Zynq UltraScale+ ZCU104 Evaluation Board",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu104_board.jpeg",
+ "website": "www.xilinx.com/zcu104",
+ "search-keywords": [
+ "zcu104",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu104/1.1/zcu104_board.jpeg b/boards/Xilinx/zcu104/1.1/zcu104_board.jpeg
new file mode 100644
index 000000000..ba6436a84
Binary files /dev/null and b/boards/Xilinx/zcu104/1.1/zcu104_board.jpeg differ
diff --git a/boards/Xilinx/zcu106/2.4/LICENSE b/boards/Xilinx/zcu106/2.4/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu106/2.4/board.xml b/boards/Xilinx/zcu106/2.4/board.xml
new file mode 100644
index 000000000..c295ee467
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.4/board.xml
@@ -0,0 +1,1187 @@
+
+
+
+
+
+ ZCU106 Board File Image
+
+
+
+ 1.1
+
+ 2.4
+ Zynq UltraScale+ ZCU106 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ PCI Express
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 2GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+
+
+
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diff --git a/boards/Xilinx/zcu106/2.4/changelog.txt b/boards/Xilinx/zcu106/2.4/changelog.txt
new file mode 100644
index 000000000..61e78b412
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.4/changelog.txt
@@ -0,0 +1,33 @@
+######### ZCU106 changelog ############
+2.4
+Enabled support for pcie4_uscale_plus IP
+Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset
+
+2.3
+Added GT Quad locations for XDMA
+
+2.2
+Swapped PL UART pins and updated DIP switch IO-Standards
+
+2.1
+Removed MIG IO attributes
+
+2.0
+Production Silicon Support
+
+1.2(June 23 2017)
+Enabled FMC Support
+
+1.1(June 23 2017)
+2017.2_web release
+PSS_REF_CLK__FREQMHZ changed from 33.333 to 33.330 to match with board UG
+
+
+1.0(April 28 2017)
+2017.1_web release
+Updated DP and other clocking parameters to match with ZCU102 board
+Moved LED3 location from AP8 to AE15 and increased PL DDR4 frequency from 1066Mhz to 1200Mhz
+
+1.0
+ZCU106 es2 board support
+
diff --git a/boards/Xilinx/zcu106/2.4/part0_pins.xml b/boards/Xilinx/zcu106/2.4/part0_pins.xml
new file mode 100644
index 000000000..2fe8fa0e7
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.4/part0_pins.xml
@@ -0,0 +1,356 @@
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diff --git a/boards/Xilinx/zcu106/2.4/preset.xml b/boards/Xilinx/zcu106/2.4/preset.xml
new file mode 100644
index 000000000..b8e74ee94
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.4/preset.xml
@@ -0,0 +1,569 @@
+
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diff --git a/boards/Xilinx/zcu106/2.4/xitem.json b/boards/Xilinx/zcu106/2.4/xitem.json
new file mode 100644
index 000000000..12ebbbebc
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.4/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu106",
+ "display": "Zynq UltraScale+ ZCU106 Evaluation Platform",
+ "revision": "2.4",
+ "description": "Zynq UltraScale+ ZCU106 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/zcu106",
+ "search-keywords": [
+ "zcu106",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/zcu106/2.4/zcu106_board.jpeg b/boards/Xilinx/zcu106/2.4/zcu106_board.jpeg
new file mode 100644
index 000000000..844ac625e
Binary files /dev/null and b/boards/Xilinx/zcu106/2.4/zcu106_board.jpeg differ
diff --git a/boards/Xilinx/zcu106/2.5/LICENSE b/boards/Xilinx/zcu106/2.5/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.5/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu106/2.5/board.xml b/boards/Xilinx/zcu106/2.5/board.xml
new file mode 100644
index 000000000..2f2dc2708
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.5/board.xml
@@ -0,0 +1,1319 @@
+
+
+
+
+
+ ZCU106 Board File Image
+
+
+
+ 1.1
+
+ 2.5
+ Zynq UltraScale+ ZCU106 Evaluation Platform
+
+
+
+
+
+
+
+
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+
+
+ FPGA part on the board
+
+
+
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+ 8-position user DIP Switch
+
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+ 1-lane GT interface over SFP
+
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+ 2-lane GT interface over SFP
+
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+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
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+
+ Clock input from PCI Express edge connector
+
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+ PCI Express
+
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+ PL UART
+
+
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+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 2GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ SFP Connector
+
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diff --git a/boards/Xilinx/zcu106/2.5/changelog.txt b/boards/Xilinx/zcu106/2.5/changelog.txt
new file mode 100644
index 000000000..95bf226c3
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.5/changelog.txt
@@ -0,0 +1,36 @@
+######### ZCU106 changelog ############
+2.5
+Added support for xxv_ethernet IP
+
+2.4
+Enabled support for pcie4_uscale_plus IP
+Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset
+
+2.3
+Added GT Quad locations for XDMA
+
+2.2
+Swapped PL UART pins and updated DIP switch IO-Standards
+
+2.1
+Removed MIG IO attributes
+
+2.0
+Production Silicon Support
+
+1.2(June 23 2017)
+Enabled FMC Support
+
+1.1(June 23 2017)
+2017.2_web release
+PSS_REF_CLK__FREQMHZ changed from 33.333 to 33.330 to match with board UG
+
+
+1.0(April 28 2017)
+2017.1_web release
+Updated DP and other clocking parameters to match with ZCU102 board
+Moved LED3 location from AP8 to AE15 and increased PL DDR4 frequency from 1066Mhz to 1200Mhz
+
+1.0
+ZCU106 es2 board support
+
diff --git a/boards/Xilinx/zcu106/2.5/part0_pins.xml b/boards/Xilinx/zcu106/2.5/part0_pins.xml
new file mode 100644
index 000000000..f2b6cc587
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.5/part0_pins.xml
@@ -0,0 +1,365 @@
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diff --git a/boards/Xilinx/zcu106/2.5/preset.xml b/boards/Xilinx/zcu106/2.5/preset.xml
new file mode 100644
index 000000000..863577e6d
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.5/preset.xml
@@ -0,0 +1,600 @@
+
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diff --git a/boards/Xilinx/zcu106/2.5/xitem.json b/boards/Xilinx/zcu106/2.5/xitem.json
new file mode 100644
index 000000000..c7eb965fd
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.5/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu106",
+ "display": "Zynq UltraScale+ ZCU106 Evaluation Platform",
+ "revision": "2.5",
+ "description": "Zynq UltraScale+ ZCU106 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu106_board.jpeg",
+ "website": "www.xilinx.com/zcu106",
+ "search-keywords": [
+ "zcu106",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu106/2.5/zcu106_board.jpeg b/boards/Xilinx/zcu106/2.5/zcu106_board.jpeg
new file mode 100644
index 000000000..844ac625e
Binary files /dev/null and b/boards/Xilinx/zcu106/2.5/zcu106_board.jpeg differ
diff --git a/boards/Xilinx/zcu106/2.6/LICENSE b/boards/Xilinx/zcu106/2.6/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.6/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu106/2.6/board.xml b/boards/Xilinx/zcu106/2.6/board.xml
new file mode 100644
index 000000000..9740a39e5
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.6/board.xml
@@ -0,0 +1,1506 @@
+
+
+
+
+
+ ZCU106 Board File Image
+
+
+
+ 1.1
+
+ 2.6
+ Zynq UltraScale+ ZCU106 Evaluation Platform
+
+
+
+
+
+
+
+
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+
+ FPGA part on the board
+
+
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+ 8-position user DIP Switch
+
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+ 1-lane GT interface over SFP
+
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+ 2-lane GT interface over SFP
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ Clock input from PCI Express edge connector
+
+
+
+
+
+
+ PCI Express
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 2GB DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ SFP Connector
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/zcu106/2.6/changelog.txt b/boards/Xilinx/zcu106/2.6/changelog.txt
new file mode 100644
index 000000000..31c215293
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.6/changelog.txt
@@ -0,0 +1,39 @@
+######### ZCU106 changelog ############
+2.6
+Added New DDR4 Memory Part MT40A256M16LY-062E support
+
+2.5
+Added support for xxv_ethernet IP
+
+2.4
+Enabled support for pcie4_uscale_plus IP
+Added PSU_DYNAMIC_DDR_CONFIG_EN to MPSoC preset
+
+2.3
+Added GT Quad locations for XDMA
+
+2.2
+Swapped PL UART pins and updated DIP switch IO-Standards
+
+2.1
+Removed MIG IO attributes
+
+2.0
+Production Silicon Support
+
+1.2(June 23 2017)
+Enabled FMC Support
+
+1.1(June 23 2017)
+2017.2_web release
+PSS_REF_CLK__FREQMHZ changed from 33.333 to 33.330 to match with board UG
+
+
+1.0(April 28 2017)
+2017.1_web release
+Updated DP and other clocking parameters to match with ZCU102 board
+Moved LED3 location from AP8 to AE15 and increased PL DDR4 frequency from 1066Mhz to 1200Mhz
+
+1.0
+ZCU106 es2 board support
+
diff --git a/boards/Xilinx/zcu106/2.6/part0_pins.xml b/boards/Xilinx/zcu106/2.6/part0_pins.xml
new file mode 100644
index 000000000..f2b6cc587
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.6/part0_pins.xml
@@ -0,0 +1,365 @@
+
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diff --git a/boards/Xilinx/zcu106/2.6/preset.xml b/boards/Xilinx/zcu106/2.6/preset.xml
new file mode 100644
index 000000000..2b9b583d7
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.6/preset.xml
@@ -0,0 +1,614 @@
+
+
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+
diff --git a/boards/Xilinx/zcu106/2.6/xitem.json b/boards/Xilinx/zcu106/2.6/xitem.json
new file mode 100644
index 000000000..393f1e80e
--- /dev/null
+++ b/boards/Xilinx/zcu106/2.6/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu106",
+ "display": "Zynq UltraScale+ ZCU106 Evaluation Platform",
+ "revision": "2.6",
+ "description": "Zynq UltraScale+ ZCU106 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu106_board.jpeg",
+ "website": "www.xilinx.com/zcu106",
+ "search-keywords": [
+ "zcu106",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu106/2.6/zcu106_board.jpeg b/boards/Xilinx/zcu106/2.6/zcu106_board.jpeg
new file mode 100644
index 000000000..844ac625e
Binary files /dev/null and b/boards/Xilinx/zcu106/2.6/zcu106_board.jpeg differ
diff --git a/boards/Xilinx/zcu111/1.2/LICENSE b/boards/Xilinx/zcu111/1.2/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.2/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu111/1.2/board.xml b/boards/Xilinx/zcu111/1.2/board.xml
new file mode 100644
index 000000000..ceb6c236d
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.2/board.xml
@@ -0,0 +1,648 @@
+
+
+
+
+
+ ZCU111 Board File Image
+
+
+
+ Rev A
+ Rev B
+ Rev 1.0
+
+ 1.2
+ Zynq UltraScale+ ZCU111 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
+
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+
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+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+ PL HP Bank GC input with external termination
+
+
+
+
+
+
+ PL HP Bank GC input with external termination
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/zcu111/1.2/changelog.txt b/boards/Xilinx/zcu111/1.2/changelog.txt
new file mode 100644
index 000000000..b92699968
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.2/changelog.txt
@@ -0,0 +1,11 @@
+######### ZCU111 change log ############
+1.2
+PSU_DYNAMIC_DDR_CONFIG_EN(2019.2 update)
+Increaed DDDR4 frequency from 1200 to 1333Mhz
+
+1.1
+Viavdo Board Support for Rev 1.0, Production Silicon
+
+1.0
+ZCU111 initial board support for Rev B, Pre production Silicon
+
diff --git a/boards/Xilinx/zcu111/1.2/part0_pins.xml b/boards/Xilinx/zcu111/1.2/part0_pins.xml
new file mode 100644
index 000000000..1f071b2c0
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.2/part0_pins.xml
@@ -0,0 +1,186 @@
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diff --git a/boards/Xilinx/zcu111/1.2/preset.xml b/boards/Xilinx/zcu111/1.2/preset.xml
new file mode 100644
index 000000000..8ef333d8e
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.2/preset.xml
@@ -0,0 +1,442 @@
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diff --git a/boards/Xilinx/zcu111/1.2/xitem.json b/boards/Xilinx/zcu111/1.2/xitem.json
new file mode 100644
index 000000000..339c7099b
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.2/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu111",
+ "display": "Zynq UltraScale+ ZCU111 Evaluation Platform",
+ "revision": "1.2",
+ "description": "Zynq UltraScale+ ZCU111 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu111_board.jpeg",
+ "website": "www.xilinx.com/zcu111",
+ "search-keywords": [
+ "zcu111",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu111/1.2/zcu111_board.jpeg b/boards/Xilinx/zcu111/1.2/zcu111_board.jpeg
new file mode 100644
index 000000000..1058a14eb
Binary files /dev/null and b/boards/Xilinx/zcu111/1.2/zcu111_board.jpeg differ
diff --git a/boards/Xilinx/zcu111/1.3/LICENSE b/boards/Xilinx/zcu111/1.3/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.3/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu111/1.3/board.xml b/boards/Xilinx/zcu111/1.3/board.xml
new file mode 100644
index 000000000..cb80b00f9
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.3/board.xml
@@ -0,0 +1,839 @@
+
+
+
+
+
+ ZCU111 Board File Image
+
+
+
+ Rev A
+ Rev B
+ Rev 1.0
+
+ 1.3
+ Zynq UltraScale+ ZCU111 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
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+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
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+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+ PL HP Bank GC input with external termination
+
+
+
+
+
+
+ PL HP Bank GC input with external termination
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/zcu111/1.3/changelog.txt b/boards/Xilinx/zcu111/1.3/changelog.txt
new file mode 100644
index 000000000..79a6b0d7e
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.3/changelog.txt
@@ -0,0 +1,13 @@
+######### ZCU111 change log ############
+1.3
+Added new DDR4 Memory part MT40A512M16LY-075 support
+1.2
+PSU_DYNAMIC_DDR_CONFIG_EN(2019.2 update)
+Increaed DDDR4 frequency from 1200 to 1333Mhz
+
+1.1
+Viavdo Board Support for Rev 1.0, Production Silicon
+
+1.0
+ZCU111 initial board support for Rev B, Pre production Silicon
+
diff --git a/boards/Xilinx/zcu111/1.3/part0_pins.xml b/boards/Xilinx/zcu111/1.3/part0_pins.xml
new file mode 100644
index 000000000..1f071b2c0
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.3/part0_pins.xml
@@ -0,0 +1,186 @@
+
+
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diff --git a/boards/Xilinx/zcu111/1.3/preset.xml b/boards/Xilinx/zcu111/1.3/preset.xml
new file mode 100644
index 000000000..e8d4e59b3
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.3/preset.xml
@@ -0,0 +1,454 @@
+
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diff --git a/boards/Xilinx/zcu111/1.3/xitem.json b/boards/Xilinx/zcu111/1.3/xitem.json
new file mode 100644
index 000000000..6afdb4f69
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.3/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu111",
+ "display": "Zynq UltraScale+ ZCU111 Evaluation Platform",
+ "revision": "1.3",
+ "description": "Zynq UltraScale+ ZCU111 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu111_board.jpeg",
+ "website": "www.xilinx.com/zcu111",
+ "search-keywords": [
+ "zcu111",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu111/1.3/zcu111_board.jpeg b/boards/Xilinx/zcu111/1.3/zcu111_board.jpeg
new file mode 100644
index 000000000..1058a14eb
Binary files /dev/null and b/boards/Xilinx/zcu111/1.3/zcu111_board.jpeg differ
diff --git a/boards/Xilinx/zcu111/1.4/LICENSE b/boards/Xilinx/zcu111/1.4/LICENSE
new file mode 100755
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.4/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu111/1.4/board.xml b/boards/Xilinx/zcu111/1.4/board.xml
new file mode 100755
index 000000000..94a2881b3
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.4/board.xml
@@ -0,0 +1,1055 @@
+
+
+
+
+
+ ZCU111 Board File Image
+
+
+
+ Rev A
+ Rev B
+ Rev 1.0
+
+ 1.4
+ Zynq UltraScale+ ZCU111 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+ PL HP Bank GC input with external termination
+
+
+
+
+
+
+ PL HP Bank GC input with external termination
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ SFP Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/zcu111/1.4/changelog.txt b/boards/Xilinx/zcu111/1.4/changelog.txt
new file mode 100755
index 000000000..5dc4410b1
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.4/changelog.txt
@@ -0,0 +1,16 @@
+######### ZCU111 change log ############
+1.4
+Added sfp[0-3] interface support for xxv_ethernet IP (Vivado 2020.1)
+
+1.3
+Added new DDR4 Memory part MT40A512M16LY-075 support
+1.2
+PSU_DYNAMIC_DDR_CONFIG_EN(2019.2 update)
+Increaed DDDR4 frequency from 1200 to 1333Mhz
+
+1.1
+Viavdo Board Support for Rev 1.0, Production Silicon
+
+1.0
+ZCU111 initial board support for Rev B, Pre production Silicon
+
diff --git a/boards/Xilinx/zcu111/1.4/part0_pins.xml b/boards/Xilinx/zcu111/1.4/part0_pins.xml
new file mode 100755
index 000000000..1f22ab0c0
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.4/part0_pins.xml
@@ -0,0 +1,202 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
diff --git a/boards/Xilinx/zcu111/1.4/preset.xml b/boards/Xilinx/zcu111/1.4/preset.xml
new file mode 100755
index 000000000..ee40c2388
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.4/preset.xml
@@ -0,0 +1,515 @@
+
+
+
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+
diff --git a/boards/Xilinx/zcu111/1.4/xitem.json b/boards/Xilinx/zcu111/1.4/xitem.json
new file mode 100755
index 000000000..36b5fd935
--- /dev/null
+++ b/boards/Xilinx/zcu111/1.4/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu111",
+ "display": "Zynq UltraScale+ ZCU111 Evaluation Platform",
+ "revision": "1.4",
+ "description": "Zynq UltraScale+ ZCU111 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu111_board.jpeg",
+ "website": "www.xilinx.com/zcu111",
+ "search-keywords": [
+ "zcu111",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu111/1.4/zcu111_board.jpeg b/boards/Xilinx/zcu111/1.4/zcu111_board.jpeg
new file mode 100755
index 000000000..1058a14eb
Binary files /dev/null and b/boards/Xilinx/zcu111/1.4/zcu111_board.jpeg differ
diff --git a/boards/Xilinx/zcu1275/1.0/LICENSE b/boards/Xilinx/zcu1275/1.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu1275/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu1275/1.0/board.xml b/boards/Xilinx/zcu1275/1.0/board.xml
new file mode 100644
index 000000000..2c6be5adc
--- /dev/null
+++ b/boards/Xilinx/zcu1275/1.0/board.xml
@@ -0,0 +1,224 @@
+
+
+
+
+
+ ZCU1275 Board Image
+
+
+
+ 2.0
+
+ 1.0
+ Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ User Switches(8-position)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 downto 0, Active High
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/Xilinx/zcu1275/1.0/changelog.txt b/boards/Xilinx/zcu1275/1.0/changelog.txt
new file mode 100644
index 000000000..067318fb6
--- /dev/null
+++ b/boards/Xilinx/zcu1275/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### ZCU1275 change log ############
+1.0
+ZCU1275 board support
+
diff --git a/boards/Xilinx/zcu1275/1.0/part0_pins.xml b/boards/Xilinx/zcu1275/1.0/part0_pins.xml
new file mode 100644
index 000000000..db0af9758
--- /dev/null
+++ b/boards/Xilinx/zcu1275/1.0/part0_pins.xml
@@ -0,0 +1,48 @@
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/zcu1275/1.0/preset.xml b/boards/Xilinx/zcu1275/1.0/preset.xml
new file mode 100644
index 000000000..cb1dcb33d
--- /dev/null
+++ b/boards/Xilinx/zcu1275/1.0/preset.xml
@@ -0,0 +1,413 @@
+
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diff --git a/boards/Xilinx/zcu1275/1.0/readme.txt b/boards/Xilinx/zcu1275/1.0/readme.txt
new file mode 100644
index 000000000..adfaedddf
--- /dev/null
+++ b/boards/Xilinx/zcu1275/1.0/readme.txt
@@ -0,0 +1,14 @@
+
+1)Validate that the xczu29dr-ffvf1760-2-e is available in your Vivado installation. Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+2) Copy the contents from the zip for into local Vivado install.
+Vivado\201X.x\data\boards\board_files\zcu1275\
+
+Alternative to step 2)
+Copy the contents from the zip into a local directory .
+Set the following parameter either in your Vivado_init.tcl or on the Vivado TCL console before project creation.
+>> set_param board.repoPaths
+
+For more information please refer to user guide UG895: Vivado System-Level Design Guide, Appendix A.
+
+
diff --git a/boards/Xilinx/zcu1275/1.0/xitem.json b/boards/Xilinx/zcu1275/1.0/xitem.json
new file mode 100644
index 000000000..1da03e6fd
--- /dev/null
+++ b/boards/Xilinx/zcu1275/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu1275",
+ "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit",
+ "revision": "1.0",
+ "description": "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu1275_board.jpeg",
+ "website": "www.xilinx.com/zcu1254",
+ "search-keywords": [
+ "zcu1275",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu1275/1.0/zcu1275_board.jpeg b/boards/Xilinx/zcu1275/1.0/zcu1275_board.jpeg
new file mode 100644
index 000000000..a9ffdc73e
Binary files /dev/null and b/boards/Xilinx/zcu1275/1.0/zcu1275_board.jpeg differ
diff --git a/boards/Xilinx/zcu1285/1.0/LICENSE b/boards/Xilinx/zcu1285/1.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu1285/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu1285/1.0/board.xml b/boards/Xilinx/zcu1285/1.0/board.xml
new file mode 100644
index 000000000..7258125df
--- /dev/null
+++ b/boards/Xilinx/zcu1285/1.0/board.xml
@@ -0,0 +1,224 @@
+
+
+
+
+
+ ZCU1285 Board Image
+
+
+
+ 2.0
+
+ 1.0
+ Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ User Switches(8-position)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 downto 0, Active High
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/zcu1285/1.0/changelog.txt b/boards/Xilinx/zcu1285/1.0/changelog.txt
new file mode 100644
index 000000000..73eb33e99
--- /dev/null
+++ b/boards/Xilinx/zcu1285/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### ZCU1285 change log ############
+1.0
+ZCU1285 board support
+
diff --git a/boards/Xilinx/zcu1285/1.0/part0_pins.xml b/boards/Xilinx/zcu1285/1.0/part0_pins.xml
new file mode 100644
index 000000000..6806dde50
--- /dev/null
+++ b/boards/Xilinx/zcu1285/1.0/part0_pins.xml
@@ -0,0 +1,48 @@
+
+
+
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+
diff --git a/boards/Xilinx/zcu1285/1.0/preset.xml b/boards/Xilinx/zcu1285/1.0/preset.xml
new file mode 100644
index 000000000..353e4583a
--- /dev/null
+++ b/boards/Xilinx/zcu1285/1.0/preset.xml
@@ -0,0 +1,412 @@
+
+
+
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+
diff --git a/boards/Xilinx/zcu1285/1.0/readme.txt b/boards/Xilinx/zcu1285/1.0/readme.txt
new file mode 100644
index 000000000..d3fc9f46b
--- /dev/null
+++ b/boards/Xilinx/zcu1285/1.0/readme.txt
@@ -0,0 +1,14 @@
+
+1)Validate that the xczu39dr-ffvf1760-2-i is available in your Vivado installation. Please see details in the board lounge or in user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+2) Copy the contents from the zip for into local Vivado install.
+Vivado\201X.x\data\boards\board_files\zcu1285\
+
+Alternative to step 2)
+Copy the contents from the zip into a local directory .
+Set the following parameter either in your Vivado_init.tcl or on the Vivado TCL console before project creation.
+>> set_param board.repoPaths
+
+For more information please refer to user guide UG895: Vivado System-Level Design Guide, Appendix A.
+
+
diff --git a/boards/Xilinx/zcu1285/1.0/xitem.json b/boards/Xilinx/zcu1285/1.0/xitem.json
new file mode 100644
index 000000000..f2c206998
--- /dev/null
+++ b/boards/Xilinx/zcu1285/1.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu1285",
+ "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit",
+ "revision": "1.0",
+ "description": "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Vanitha",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu1285_board.jpeg",
+ "website": "www.xilinx.com/zcu1285",
+ "search-keywords": [
+ "zcu1285",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu1285/1.0/zcu1285_board.jpeg b/boards/Xilinx/zcu1285/1.0/zcu1285_board.jpeg
new file mode 100644
index 000000000..a9ffdc73e
Binary files /dev/null and b/boards/Xilinx/zcu1285/1.0/zcu1285_board.jpeg differ
diff --git a/boards/Xilinx/zcu208/production/2.0/LICENSE b/boards/Xilinx/zcu208/production/2.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu208/production/2.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu208/production/2.0/board.xml b/boards/Xilinx/zcu208/production/2.0/board.xml
new file mode 100755
index 000000000..759b13b93
--- /dev/null
+++ b/boards/Xilinx/zcu208/production/2.0/board.xml
@@ -0,0 +1,1349 @@
+
+
+
+
+
+ ZCU08 Board File Image
+
+
+
+ Rev A
+
+
+
+ 2.0
+ Zynq UltraScale+ RFSoC ZCU208 Evaluation Kit
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
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+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
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+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ SFP Connector
+
+
+
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diff --git a/boards/Xilinx/zcu208/production/2.0/changelog.txt b/boards/Xilinx/zcu208/production/2.0/changelog.txt
new file mode 100755
index 000000000..d568f234f
--- /dev/null
+++ b/boards/Xilinx/zcu208/production/2.0/changelog.txt
@@ -0,0 +1,7 @@
+######### ZCU208 change log ############
+2022.1
+Enabled CONFIG.PSU_DYNAMIC_DDR_CONFIG_EN. Retained same version
+
+2.0
+ZCU208 production initial board support (Vivado 2020.2)
+
diff --git a/boards/Xilinx/zcu208/production/2.0/part0_pins.xml b/boards/Xilinx/zcu208/production/2.0/part0_pins.xml
new file mode 100755
index 000000000..060e41393
--- /dev/null
+++ b/boards/Xilinx/zcu208/production/2.0/part0_pins.xml
@@ -0,0 +1,251 @@
+
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diff --git a/boards/Xilinx/zcu208/production/2.0/preset.xml b/boards/Xilinx/zcu208/production/2.0/preset.xml
new file mode 100755
index 000000000..46ac3c96d
--- /dev/null
+++ b/boards/Xilinx/zcu208/production/2.0/preset.xml
@@ -0,0 +1,575 @@
+
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+
diff --git a/boards/Xilinx/zcu208/production/2.0/xitem.json b/boards/Xilinx/zcu208/production/2.0/xitem.json
new file mode 100755
index 000000000..3471cfc48
--- /dev/null
+++ b/boards/Xilinx/zcu208/production/2.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu208",
+ "display": "Zynq UltraScale+ ZCU208 Evaluation Platform",
+ "revision": "2.0",
+ "description": "Zynq UltraScale+ ZCU208 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu208_board.jpeg",
+ "website": "www.xilinx.com/zcu208",
+ "search-keywords": [
+ "zcu208",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/zcu208/production/2.0/zcu208_board.jpeg b/boards/Xilinx/zcu208/production/2.0/zcu208_board.jpeg
new file mode 100755
index 000000000..906641b71
Binary files /dev/null and b/boards/Xilinx/zcu208/production/2.0/zcu208_board.jpeg differ
diff --git a/boards/Xilinx/zcu208ld/production/2.0/LICENSE b/boards/Xilinx/zcu208ld/production/2.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu208ld/production/2.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu208ld/production/2.0/board.xml b/boards/Xilinx/zcu208ld/production/2.0/board.xml
new file mode 100755
index 000000000..0fdd8e53d
--- /dev/null
+++ b/boards/Xilinx/zcu208ld/production/2.0/board.xml
@@ -0,0 +1,1031 @@
+
+
+
+
+
+
+
+
+
+ ZCU08 Board File Image
+
+
+
+ Rev A
+
+
+
+ 2.0
+ Zynq UltraScale+ RFSoC ZCU208-LD Evaluation Kit
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ SFP Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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diff --git a/boards/Xilinx/zcu208ld/production/2.0/changelog.txt b/boards/Xilinx/zcu208ld/production/2.0/changelog.txt
new file mode 100755
index 000000000..7ea501e95
--- /dev/null
+++ b/boards/Xilinx/zcu208ld/production/2.0/changelog.txt
@@ -0,0 +1,5 @@
+######### ZCU208-LD change log ############
+
+2.0
+ZCU208-LD Production board support for Rev A (2020.2)
+
diff --git a/boards/Xilinx/zcu208ld/production/2.0/part0_pins.xml b/boards/Xilinx/zcu208ld/production/2.0/part0_pins.xml
new file mode 100755
index 000000000..c7bc8e3a7
--- /dev/null
+++ b/boards/Xilinx/zcu208ld/production/2.0/part0_pins.xml
@@ -0,0 +1,258 @@
+
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diff --git a/boards/Xilinx/zcu208ld/production/2.0/preset.xml b/boards/Xilinx/zcu208ld/production/2.0/preset.xml
new file mode 100755
index 000000000..81c8f769b
--- /dev/null
+++ b/boards/Xilinx/zcu208ld/production/2.0/preset.xml
@@ -0,0 +1,553 @@
+
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diff --git a/boards/Xilinx/zcu208ld/production/2.0/xitem.json b/boards/Xilinx/zcu208ld/production/2.0/xitem.json
new file mode 100755
index 000000000..8487c60b8
--- /dev/null
+++ b/boards/Xilinx/zcu208ld/production/2.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu208ld",
+ "display": "Zynq UltraScale+ ZCU208-LD Evaluation Platform",
+ "revision": "2.0",
+ "description": "Zynq UltraScale+ ZCU208-LD Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/zcu208",
+ "search-keywords": [
+ "zcu208ld",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu216/production/2.0/LICENSE b/boards/Xilinx/zcu216/production/2.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu216/production/2.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu216/production/2.0/board.xml b/boards/Xilinx/zcu216/production/2.0/board.xml
new file mode 100755
index 000000000..8ba9a8a05
--- /dev/null
+++ b/boards/Xilinx/zcu216/production/2.0/board.xml
@@ -0,0 +1,1390 @@
+
+
+
+
+
+
+ ZCU216 Board File Image
+
+
+
+ Rev A
+
+
+
+ 2.0
+ Zynq UltraScale+ ZCU216 Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ RGB_R LEDs, 7 to 0, Active High
+
+
+
+ RGB_G LEDs, 7 to 0, Active High
+
+
+
+ RGB_B LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ SFP Connector
+
+
+
+
+
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diff --git a/boards/Xilinx/zcu216/production/2.0/changelog.txt b/boards/Xilinx/zcu216/production/2.0/changelog.txt
new file mode 100755
index 000000000..a66a00b7b
--- /dev/null
+++ b/boards/Xilinx/zcu216/production/2.0/changelog.txt
@@ -0,0 +1,5 @@
+######### ZCU216 Production change log ############
+
+2.0
+ZCU216 initial board support for Production Board with dual memory support (Vivado 2020.2)
+
diff --git a/boards/Xilinx/zcu216/production/2.0/part0_pins.xml b/boards/Xilinx/zcu216/production/2.0/part0_pins.xml
new file mode 100755
index 000000000..6ea6be483
--- /dev/null
+++ b/boards/Xilinx/zcu216/production/2.0/part0_pins.xml
@@ -0,0 +1,271 @@
+
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diff --git a/boards/Xilinx/zcu216/production/2.0/preset.xml b/boards/Xilinx/zcu216/production/2.0/preset.xml
new file mode 100755
index 000000000..351583541
--- /dev/null
+++ b/boards/Xilinx/zcu216/production/2.0/preset.xml
@@ -0,0 +1,706 @@
+
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diff --git a/boards/Xilinx/zcu216/production/2.0/xitem.json b/boards/Xilinx/zcu216/production/2.0/xitem.json
new file mode 100755
index 000000000..ad5ebd9d9
--- /dev/null
+++ b/boards/Xilinx/zcu216/production/2.0/xitem.json
@@ -0,0 +1,35 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu216",
+ "display": "Zynq UltraScale+ ZCU216 Evaluation Platform",
+ "revision": "2.0",
+ "description": "Zynq UltraScale+ ZCU216 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu216_board.jpeg",
+ "website": "www.xilinx.com/zcu216",
+ "search-keywords": [
+ "zcu216",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu216/production/2.0/zcu216_board.jpeg b/boards/Xilinx/zcu216/production/2.0/zcu216_board.jpeg
new file mode 100755
index 000000000..52d0852a2
Binary files /dev/null and b/boards/Xilinx/zcu216/production/2.0/zcu216_board.jpeg differ
diff --git a/boards/Xilinx/zcu216ld/production/2.0/LICENSE b/boards/Xilinx/zcu216ld/production/2.0/LICENSE
new file mode 100755
index 000000000..e9a4ac2f2
--- /dev/null
+++ b/boards/Xilinx/zcu216ld/production/2.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu216ld/production/2.0/board.xml b/boards/Xilinx/zcu216ld/production/2.0/board.xml
new file mode 100755
index 000000000..ad192ded5
--- /dev/null
+++ b/boards/Xilinx/zcu216ld/production/2.0/board.xml
@@ -0,0 +1,1078 @@
+
+
+
+
+
+ ZCU216 Board File Image
+
+
+
+ Rev A
+
+ 2.0
+ Zynq UltraScale+ ZCU216-LD Evaluation Platform
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8-position user DIP Switch
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1-lane GT interface over SFP
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ PL I2C0
+
+
+
+ PL I2C1
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8Gb DDR4 SDRAM memory SODIMM
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ DIP Switches 7 to 0
+
+
+
+ RGB_R LEDs, 7 to 0, Active High
+
+
+
+ RGB_G LEDs, 7 to 0, Active High
+
+
+
+ RGB_B LEDs, 7 to 0, Active High
+
+
+
+ Push Buttons, C W E S N, Active High
+
+
+
+ SFP Connector
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
diff --git a/boards/Xilinx/zcu216ld/production/2.0/changelog.txt b/boards/Xilinx/zcu216ld/production/2.0/changelog.txt
new file mode 100755
index 000000000..03c7bde00
--- /dev/null
+++ b/boards/Xilinx/zcu216ld/production/2.0/changelog.txt
@@ -0,0 +1,6 @@
+######### ZCU216-LD change log ############
+
+2.0
+ZCU216-LD production board support for Rev A (Vivado 2020.2)
+
+
diff --git a/boards/Xilinx/zcu216ld/production/2.0/part0_pins.xml b/boards/Xilinx/zcu216ld/production/2.0/part0_pins.xml
new file mode 100755
index 000000000..0fd0829a3
--- /dev/null
+++ b/boards/Xilinx/zcu216ld/production/2.0/part0_pins.xml
@@ -0,0 +1,272 @@
+
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diff --git a/boards/Xilinx/zcu216ld/production/2.0/preset.xml b/boards/Xilinx/zcu216ld/production/2.0/preset.xml
new file mode 100755
index 000000000..8f41912b5
--- /dev/null
+++ b/boards/Xilinx/zcu216ld/production/2.0/preset.xml
@@ -0,0 +1,679 @@
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diff --git a/boards/Xilinx/zcu216ld/production/2.0/xitem.json b/boards/Xilinx/zcu216ld/production/2.0/xitem.json
new file mode 100755
index 000000000..18f84d955
--- /dev/null
+++ b/boards/Xilinx/zcu216ld/production/2.0/xitem.json
@@ -0,0 +1,34 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu216ld",
+ "display": "Zynq UltraScale+ ZCU216-LD Evaluation Platform",
+ "revision": "2.0",
+ "description": "Zynq UltraScale+ ZCU216-LD Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Ashish",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "logo": "zcu216_board.jpeg",
+ "website": "www.xilinx.com/zcu216",
+ "search-keywords": [
+ "zcu216ld",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
diff --git a/boards/Xilinx/zcu216ld/production/2.0/zcu216_board.jpeg b/boards/Xilinx/zcu216ld/production/2.0/zcu216_board.jpeg
new file mode 100755
index 000000000..52d0852a2
Binary files /dev/null and b/boards/Xilinx/zcu216ld/production/2.0/zcu216_board.jpeg differ
diff --git a/boards/Xilinx/zcu670/2.0/LICENSE b/boards/Xilinx/zcu670/2.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/zcu670/2.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu670/2.0/README.md b/boards/Xilinx/zcu670/2.0/README.md
new file mode 100644
index 000000000..d9a6ea5f8
--- /dev/null
+++ b/boards/Xilinx/zcu670/2.0/README.md
@@ -0,0 +1,23 @@
+# Verify that ZCU670 parts are available in your Vivado installation:
+get_parts *xczu67dr* in Viavdo TCL console should return xczu67dr-fsve1156-2-i
+
+# If parts are not available:
+Please see details in the board lounge or user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+# Steps to install board parts :
+1. Copy conetents of this folder to your desired directory
+2. Set below param in Vivado_init.tcl
+set_param board.repo Paths
+
+
+#Details on Vivado_init.tcl
+In every launch Vivado looks for a Tcl initialization script in the following locations:
+
+In the software installation: /Vivado/version/scripts/Vivado_init.tcl.
+(Where is the installation directory where the Vivado Design Suite is installed.)
+In the local user directory:
+a. For Windows : %APPDATA%/Xilinx/Vivado/Vivado_init.tcl
+b. For Linux: $HOME/.Xilinx/Vivado/Vivado_init.tcl
+
+#For information on design creation
+Refer user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/zcu670/2.0/board.xml b/boards/Xilinx/zcu670/2.0/board.xml
new file mode 100644
index 000000000..0c6eeb7fe
--- /dev/null
+++ b/boards/Xilinx/zcu670/2.0/board.xml
@@ -0,0 +1,612 @@
+
+
+
+
+
+ ZCU670 Board File Image
+
+
+
+ Rev B
+
+ 2.0
+ Zynq UltraScale+ RFSoC ZCU670 Evaluation Kit
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
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+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+ 1-lane GT interface over SFP
+
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+ 1-lane GT interface over SFP
+
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+ 1-lane GT interface over SFP
+
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+ 1-lane GT interface over SFP
+
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+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ 4GB DDR4 SDRAM memory
+
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+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ LEDs, 3 to 0, Active High
+
+
+
+ DIP Switches,GPIO 0 1 2 3, Active High
+
+
+
+ SFP Connector
+
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\ No newline at end of file
diff --git a/boards/Xilinx/zcu670/2.0/changelog.txt b/boards/Xilinx/zcu670/2.0/changelog.txt
new file mode 100644
index 000000000..a14e793ba
--- /dev/null
+++ b/boards/Xilinx/zcu670/2.0/changelog.txt
@@ -0,0 +1,7 @@
+######### ZCU670 change log ############
+
+2.0
+ZCU670 (Rev B) New SD Level Shifter support (Vivado 2021.2_web)
+
+1.0
+ZCU670 initial board support (Vivado 2021.1_web)
\ No newline at end of file
diff --git a/boards/Xilinx/zcu670/2.0/part0_pins.xml b/boards/Xilinx/zcu670/2.0/part0_pins.xml
new file mode 100644
index 000000000..a4bcafb9e
--- /dev/null
+++ b/boards/Xilinx/zcu670/2.0/part0_pins.xml
@@ -0,0 +1,144 @@
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diff --git a/boards/Xilinx/zcu670/2.0/preset.xml b/boards/Xilinx/zcu670/2.0/preset.xml
new file mode 100644
index 000000000..cf70e153f
--- /dev/null
+++ b/boards/Xilinx/zcu670/2.0/preset.xml
@@ -0,0 +1,473 @@
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diff --git a/boards/Xilinx/zcu670/2.0/xitem.json b/boards/Xilinx/zcu670/2.0/xitem.json
new file mode 100644
index 000000000..810db589a
--- /dev/null
+++ b/boards/Xilinx/zcu670/2.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu670",
+ "display": "Zynq UltraScale+ ZCU670 Evaluation Platform",
+ "revision": "2.0",
+ "description": "Zynq UltraScale+ ZCU670 Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Devarajulu",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/zcu670",
+ "search-keywords": [
+ "zcu670",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/Xilinx/zcu670ld/1.0/LICENSE b/boards/Xilinx/zcu670ld/1.0/LICENSE
new file mode 100644
index 000000000..24120d9e8
--- /dev/null
+++ b/boards/Xilinx/zcu670ld/1.0/LICENSE
@@ -0,0 +1,15 @@
+#########################################################################
+Copyright (C) 2023, Advanced Micro Devices, Inc - All rights reserved
+
+Licensed under the Apache License, Version 2.0 (the "License"). You may
+not use this file except in compliance with the License. A copy of the
+License is located at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
+License for the specific language governing permissions and limitations
+under the License.
+#########################################################################
diff --git a/boards/Xilinx/zcu670ld/1.0/README.md b/boards/Xilinx/zcu670ld/1.0/README.md
new file mode 100644
index 000000000..c42d2393d
--- /dev/null
+++ b/boards/Xilinx/zcu670ld/1.0/README.md
@@ -0,0 +1,23 @@
+# Verify that ZCU670-LD parts are available in your Vivado installation:
+get_parts *xczu57dr* in Viavdo TCL console should return xczu57dr-fsve1156-2-i
+
+# If parts are not available:
+Please see details in the board lounge or user guide UG973: Vivado Release Notes, Installation, and Licensing.
+
+# Steps to install board parts :
+1. Copy conetents of this folder to your desired directory
+2. Set below param in Vivado_init.tcl
+set_param board.repo Paths
+
+
+#Details on Vivado_init.tcl
+In every launch Vivado looks for a Tcl initialization script in the following locations:
+
+In the software installation: /Vivado/version/scripts/Vivado_init.tcl.
+(Where is the installation directory where the Vivado Design Suite is installed.)
+In the local user directory:
+a. For Windows : %APPDATA%/Xilinx/Vivado/Vivado_init.tcl
+b. For Linux: $HOME/.Xilinx/Vivado/Vivado_init.tcl
+
+#For information on design creation
+Refer user guide UG994: Using the Platform Board Flow in IP Integrator.
diff --git a/boards/Xilinx/zcu670ld/1.0/board.xml b/boards/Xilinx/zcu670ld/1.0/board.xml
new file mode 100644
index 000000000..6844211fd
--- /dev/null
+++ b/boards/Xilinx/zcu670ld/1.0/board.xml
@@ -0,0 +1,612 @@
+
+
+
+
+
+ ZCU670-LD Board File Image
+
+
+
+ Rev B
+
+ 1.0
+ Zynq UltraScale+ RFSoC ZCU670-LD Evaluation Kit
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
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+
+
+ 1-lane GT interface over SFP
+
+
+
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+ 1-lane GT interface over SFP
+
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+ 1-lane GT interface over SFP
+
+
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+
+
+
+
+
+
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+
+
+ 1-lane GT interface over SFP
+
+
+
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+
+
+
+
+
+
+
+
+ SI570 based User programmable differential 300 MHz Clock. Can be used for DDR4 input system clock
+
+
+
+
+
+
+ PL UART
+
+
+
+
+
+
+
+ 4GB DDR4 SDRAM memory
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ CPU Reset Push Button, Active High
+
+
+
+ LEDs, 3 to 0, Active High
+
+
+
+ DIP Switches,GPIO 0 1 2 3, Active High
+
+
+
+ SFP Connector
+
+
+
+
+
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+
\ No newline at end of file
diff --git a/boards/Xilinx/zcu670ld/1.0/changelog.txt b/boards/Xilinx/zcu670ld/1.0/changelog.txt
new file mode 100644
index 000000000..e1bb5bffa
--- /dev/null
+++ b/boards/Xilinx/zcu670ld/1.0/changelog.txt
@@ -0,0 +1,4 @@
+######### ZCU670-LD change log ############
+
+1.0
+ZCU670-LD initial board support (Vivado 2021.2_web)
\ No newline at end of file
diff --git a/boards/Xilinx/zcu670ld/1.0/part0_pins.xml b/boards/Xilinx/zcu670ld/1.0/part0_pins.xml
new file mode 100644
index 000000000..6a0745aca
--- /dev/null
+++ b/boards/Xilinx/zcu670ld/1.0/part0_pins.xml
@@ -0,0 +1,144 @@
+
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diff --git a/boards/Xilinx/zcu670ld/1.0/preset.xml b/boards/Xilinx/zcu670ld/1.0/preset.xml
new file mode 100644
index 000000000..b11ac1c03
--- /dev/null
+++ b/boards/Xilinx/zcu670ld/1.0/preset.xml
@@ -0,0 +1,468 @@
+
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+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/Xilinx/zcu670ld/1.0/xitem.json b/boards/Xilinx/zcu670ld/1.0/xitem.json
new file mode 100644
index 000000000..57b7b31a7
--- /dev/null
+++ b/boards/Xilinx/zcu670ld/1.0/xitem.json
@@ -0,0 +1,33 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "zcu670ld",
+ "display": "Zynq UltraScale+ ZCU670-LD Evaluation Platform",
+ "revision": "1.0",
+ "description": "Zynq UltraScale+ ZCU670-LD Evaluation Platform",
+ "company": "xilinx.com",
+ "company_display": "Xilinx",
+ "author": "Devarajulu",
+ "contributors": [
+ {
+ "group": "Xilinx",
+ "url": "www.xilinx.com"
+ }
+ ],
+ "category": "Evaluation Boards",
+ "website": "www.xilinx.com/zcu670",
+ "search-keywords": [
+ "zcu670ld",
+ "xilinx.com",
+ "board",
+ "Evaluation Boards"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/board.xml b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/board.xml
new file mode 100644
index 000000000..dc90c28de
--- /dev/null
+++ b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/board.xml
@@ -0,0 +1,84 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G28-SOM Image
+
+
+
+
+ 4.0
+
+
+ 1.0
+
+ ZYNQ-7000 XC7Z020 SOM, 512MB PS DDR3, 2MB QSPI Flash boot, 8GB eMMC and Wifi Module/BT
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 50MHz PL Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/iW-G28-SOM.jpg b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/iW-G28-SOM.jpg
new file mode 100644
index 000000000..c5727f1dd
Binary files /dev/null and b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/iW-G28-SOM.jpg differ
diff --git a/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/part0_pins.xml b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/part0_pins.xml
new file mode 100644
index 000000000..4d82eb832
--- /dev/null
+++ b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/part0_pins.xml
@@ -0,0 +1,15 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/preset.xml b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/preset.xml
new file mode 100644
index 000000000..46c649902
--- /dev/null
+++ b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/preset.xml
@@ -0,0 +1,61 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/xitem.json b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/xitem.json
new file mode 100644
index 000000000..025dc5e2c
--- /dev/null
+++ b/boards/iWave/iW-G28M-SM20-3D512M-E008G-BIF/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G28M-SM20-3D512M-E008G-BIF",
+ "display": "iW-G28M-SM20-3D512M-E008G-BIF",
+ "revision": "4.0",
+ "description": "ZYNQ-7000 XC7Z020 SOM, 512MB PS DDR3, 2MB QSPI Flash boot, 8GB eMMC and Wifi Module/BT",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zynq-7000-sodimm-som/",
+ "logo": "iW-G28-SOM.jpg",
+ "search-keywords": [
+ "iW-G28M-SM20-3D512M-E008G-BIF",
+ "iwavesystems.com",
+ "board",
+ "iW-G28-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/MT40A512M16LY_062E_3200.csv b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/MT40A512M16LY_062E_3200.csv
new file mode 100644
index 000000000..086e12509
--- /dev/null
+++ b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/MT40A512M16LY_062E_3200.csv
@@ -0,0 +1,2 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tMRD,tRAS,tRCD,tREFI,tRFC,tRP,tRRD_S,tRRD_L,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,cas latency,cas write latency,burst length,RTT (nominal) - ODT
+Components,MT40A1G16KH-062E AIT:E,1,1,0,1,17,17,10,2,1,1,1,1,1,062E,8GB,16Gb,16,16,8,1.2V,64,833,1600,5000 ps,30000 ps,8 tck,32000 ps,13750 ps,7800000 ps,350000 ps,13750 ps,5300 ps,6400 ps,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,22,16,8,RZQ/6
diff --git a/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/board.xml b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/board.xml
new file mode 100644
index 000000000..40a96a126
--- /dev/null
+++ b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
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+
+ iW-G35-SOM Image
+
+
+
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+ 1.9
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 11EG-1-I SOM, 8GB PS DDR4, Dual 8GB FPGA DDR4, 8GB eMMC Flash
+
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+ FPGA part on the board
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
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+ 8GB FPGA DDR4 1
+
+
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+
+ FPGA DDR4 1 Reference Clock
+
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+ 8GB FPGA DDR4 2
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+ FPGA DDR4 2 Reference Clock
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\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/part0_pins.xml b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/part0_pins.xml
new file mode 100644
index 000000000..bf7d7e8f5
--- /dev/null
+++ b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
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diff --git a/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/preset.xml b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/preset.xml
new file mode 100644
index 000000000..7094586ae
--- /dev/null
+++ b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/preset.xml
@@ -0,0 +1,184 @@
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diff --git a/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/xitem.json b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/xitem.json
new file mode 100644
index 000000000..cf1e4a0e7
--- /dev/null
+++ b/boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-11EG-4E008G-E008G-BIA",
+ "display": "iW-G35M-11EG-4E008G-E008G-BIA",
+ "revision": "1.9",
+ "description": "Zynq UltraScale+ MPSoC 11EG-1-I SOM, 8GB PS DDR4, Dual 8GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-11EG-4E008G-E008G-BIA",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/board.xml
new file mode 100644
index 000000000..6de5857b0
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.7
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-3-E SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
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+
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
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+ 4GB FPGA DDR4 1
+
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+ FPGA DDR4 1 Reference Clock
+
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+ 4GB FPGA DDR4 2
+
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+ FPGA DDR4 2 Reference Clock
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\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/part0_pins.xml
new file mode 100644
index 000000000..09703dcc3
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/preset.xml
new file mode 100644
index 000000000..6097c6b2c
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/preset.xml
@@ -0,0 +1,182 @@
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/xitem.json
new file mode 100644
index 000000000..5de127da5
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E004G-E008G-BEF",
+ "display": "iW-G35M-19EG-4E004G-E008G-BEF",
+ "revision": "1.7",
+ "description": "Zynq UltraScale+ MPSoC 19EG-3-E SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E004G-E008G-BEF",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/board.xml
new file mode 100644
index 000000000..ee2561079
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.6
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
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+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 4GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/part0_pins.xml
new file mode 100644
index 000000000..512906cd4
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
+
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/preset.xml
new file mode 100644
index 000000000..d938d5c2f
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/xitem.json
new file mode 100644
index 000000000..5b9d66b21
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E004G-E008G-BIG",
+ "display": "iW-G35M-19EG-4E004G-E008G-BIG",
+ "revision": "1.6",
+ "description": "Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E004G-E008G-BIG",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/board.xml
new file mode 100644
index 000000000..78a984877
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.C
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-1-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 4GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/part0_pins.xml
new file mode 100644
index 000000000..c64582559
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
+
+
+
+
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+
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+
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/preset.xml
new file mode 100644
index 000000000..e97f0adbf
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
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+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/xitem.json
new file mode 100644
index 000000000..2b7baa147
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E004G-E008G-BII",
+ "display": "iW-G35M-19EG-4E004G-E008G-BII",
+ "revision": "1.C",
+ "description": "Zynq UltraScale+ MPSoC 19EG-1-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E004G-E008G-BII",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/board.xml
new file mode 100644
index 000000000..9175ea340
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.D
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
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+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 4GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/part0_pins.xml
new file mode 100644
index 000000000..3134e77bc
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/preset.xml
new file mode 100644
index 000000000..9b60d9d83
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/xitem.json
new file mode 100644
index 000000000..5ea04f38f
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E004G-E008G-BIJ",
+ "display": "iW-G35M-19EG-4E004G-E008G-BIJ",
+ "revision": "1.D",
+ "description": "Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E004G-E008G-BIJ",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/board.xml
new file mode 100644
index 000000000..435813216
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.4
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 4GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/part0_pins.xml
new file mode 100644
index 000000000..d7bf5ac72
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
+
+
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/preset.xml
new file mode 100644
index 000000000..6e07e5c92
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/preset.xml
@@ -0,0 +1,182 @@
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/xitem.json
new file mode 100644
index 000000000..aa69393e4
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E004G-E008G-LIE",
+ "display": "iW-G35M-19EG-4E004G-E008G-LIE",
+ "revision": "1.4",
+ "description": "Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E004G-E008G-LIE",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/board.xml
new file mode 100644
index 000000000..832f04831
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.8
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
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+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 4GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
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+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/part0_pins.xml
new file mode 100644
index 000000000..3f96a06ca
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/preset.xml
new file mode 100644
index 000000000..6eeb7b736
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/xitem.json
new file mode 100644
index 000000000..bdb71398a
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E004G-E008G-LIH",
+ "display": "iW-G35M-19EG-4E004G-E008G-LIH",
+ "revision": "1.8",
+ "description": "Zynq UltraScale+ MPSoC 19EG-2-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E004G-E008G-LIH",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/board.xml
new file mode 100644
index 000000000..9ea7a721f
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.3
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-1-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 128GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 4GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/part0_pins.xml
new file mode 100644
index 000000000..0a7e6a8f8
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
+
+
+
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+
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+
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/preset.xml
new file mode 100644
index 000000000..7af034e30
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/preset.xml
@@ -0,0 +1,182 @@
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/xitem.json
new file mode 100644
index 000000000..8f5648986
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E004G-E128G-BIA",
+ "display": "iW-G35M-19EG-4E004G-E128G-BIA",
+ "revision": "1.3",
+ "description": "Zynq UltraScale+ MPSoC 19EG-1-I SOM, 4GB PS DDR4, Dual 4GB FPGA DDR4, 128GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E004G-E128G-BIA",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/MT40A512M16LY_062E_3200.csv b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/MT40A512M16LY_062E_3200.csv
new file mode 100644
index 000000000..086e12509
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/MT40A512M16LY_062E_3200.csv
@@ -0,0 +1,2 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tMRD,tRAS,tRCD,tREFI,tRFC,tRP,tRRD_S,tRRD_L,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,cas latency,cas write latency,burst length,RTT (nominal) - ODT
+Components,MT40A1G16KH-062E AIT:E,1,1,0,1,17,17,10,2,1,1,1,1,1,062E,8GB,16Gb,16,16,8,1.2V,64,833,1600,5000 ps,30000 ps,8 tck,32000 ps,13750 ps,7800000 ps,350000 ps,13750 ps,5300 ps,6400 ps,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,22,16,8,RZQ/6
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/board.xml
new file mode 100644
index 000000000..b21c92a30
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.A
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-2-I SOM, 8GB PS DDR4, Dual 8GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
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+
+
+
+
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+
+
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+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 8GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/part0_pins.xml
new file mode 100644
index 000000000..ec4fde35c
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
+
+
+
+
+
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+
+
+
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+
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+
+
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/preset.xml
new file mode 100644
index 000000000..0b0cad5e1
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/preset.xml
@@ -0,0 +1,184 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/xitem.json
new file mode 100644
index 000000000..269bbcc55
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E008G-E008G-BIE",
+ "display": "iW-G35M-19EG-4E008G-E008G-BIE",
+ "revision": "1.A",
+ "description": "Zynq UltraScale+ MPSoC 19EG-2-I SOM, 8GB PS DDR4, Dual 8GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E008G-E008G-BIE",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/MT40A512M16LY_062E_3200.csv b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/MT40A512M16LY_062E_3200.csv
new file mode 100644
index 000000000..086e12509
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/MT40A512M16LY_062E_3200.csv
@@ -0,0 +1,2 @@
+Part type,Part name,Rank,StackHeight,CA Mirror,Data mask,Address width,Row width,Column width,Bank width,Bank group width,CS width,CKE width,ODT width,CK width,Memory speed grade,Memory density,Component density,Memory device width,Memory component width,Data bits per strobe,IO Voltages,Data widths,Min period,Max period,tCKE,tFAW,tMRD,tRAS,tRCD,tREFI,tRFC,tRP,tRRD_S,tRRD_L,tRTP,tWR,tWTR_S,tWTR_L,tXPR,tZQCS,tZQINIT,cas latency,cas write latency,burst length,RTT (nominal) - ODT
+Components,MT40A1G16KH-062E AIT:E,1,1,0,1,17,17,10,2,1,1,1,1,1,062E,8GB,16Gb,16,16,8,1.2V,64,833,1600,5000 ps,30000 ps,8 tck,32000 ps,13750 ps,7800000 ps,350000 ps,13750 ps,5300 ps,6400 ps,7500 ps,15000 ps,2500 ps,7500 ps,360 ns,128 tck,1024 tck,22,16,8,RZQ/6
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/board.xml
new file mode 100644
index 000000000..ed5a2709f
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.E
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-2-I SOM, 8GB PS DDR4, Dual 8GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+ 8GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 8GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
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+
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+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/part0_pins.xml
new file mode 100644
index 000000000..fb9270841
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/preset.xml
new file mode 100644
index 000000000..65b078410
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/preset.xml
@@ -0,0 +1,184 @@
+
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diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/xitem.json
new file mode 100644
index 000000000..174cbc2ce
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E008G-E008G-BIJ",
+ "display": "iW-G35M-19EG-4E008G-E008G-BIJ",
+ "revision": "1.E",
+ "description": "Zynq UltraScale+ MPSoC 19EG-2-I SOM, 8GB PS DDR4, Dual 8GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E008G-E008G-BIJ",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/board.xml b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/board.xml
new file mode 100644
index 000000000..0e71d427f
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/board.xml
@@ -0,0 +1,504 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G35-SOM Image
+
+
+
+
+ 1.B
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 19EG-1-I SOM, 8GB PS DDR4, Dual 4GB FPGA DDR4, 16GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
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+
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+
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+
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+
+
+
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
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+
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+
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+
+
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+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 4GB FPGA DDR4 1
+
+
+
+
+
+
+
+ FPGA DDR4 1 Reference Clock
+
+
+
+
+
+
+ 4GB FPGA DDR4 2
+
+
+
+
+
+
+
+ FPGA DDR4 2 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/iW-G35-SOM.jpeg b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/iW-G35-SOM.jpeg
new file mode 100644
index 000000000..e2193efb7
Binary files /dev/null and b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/iW-G35-SOM.jpeg differ
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/part0_pins.xml b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/part0_pins.xml
new file mode 100644
index 000000000..09f90d306
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/part0_pins.xml
@@ -0,0 +1,279 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/preset.xml b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/preset.xml
new file mode 100644
index 000000000..6bbd558d1
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
diff --git a/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/xitem.json b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/xitem.json
new file mode 100644
index 000000000..7d122215c
--- /dev/null
+++ b/boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G35M-19EG-4E008G-E016G-BIA",
+ "display": "iW-G35M-19EG-4E008G-E016G-BIA",
+ "revision": "1.B",
+ "description": "Zynq UltraScale+ MPSoC 19EG-1-I SOM, 8GB PS DDR4, Dual 4GB FPGA DDR4, 16GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu19-zu17-zu11-zynq-ultrascale-mpsocsom/",
+ "logo": "iW-G35-SOM.jpeg",
+ "search-keywords": [
+ "iW-G35M-19EG-4E008G-E016G-BIA",
+ "iwavesystems.com",
+ "board",
+ "iW-G35-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/board.xml b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/board.xml
new file mode 100644
index 000000000..a8dc210da
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/board.xml
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G30-SOM Image
+
+
+
+
+ 2.4
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 4CG-1-I SOM, 2GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1GB FPGA DDR4
+
+
+
+
+
+
+
+ FPGA DDR4 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/iW-G30-SOM.png b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/iW-G30-SOM.png
new file mode 100644
index 000000000..60b790b41
Binary files /dev/null and b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/iW-G30-SOM.png differ
diff --git a/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/part0_pins.xml b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/part0_pins.xml
new file mode 100644
index 000000000..4bd77980e
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/part0_pins.xml
@@ -0,0 +1,79 @@
+
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diff --git a/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/preset.xml b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/preset.xml
new file mode 100644
index 000000000..b53d1147a
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
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\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/xitem.json b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/xitem.json
new file mode 100644
index 000000000..41b33ff13
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G30M-C4CG-4E002G-E008G-LIA",
+ "display": "iW-G30M-C4CG-4E002G-E008G-LIA",
+ "revision": "2.4",
+ "description": "Zynq UltraScale+ MPSoC 4CG-1-I SOM, 2GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu7-zu5-zu4-zynq-ultrascale-mpsocsom",
+ "logo": "iW-G30-SOM.png",
+ "search-keywords": [
+ "iW-G30M-C4CG-4E002G-E008G-LIA",
+ "iwavesystems.com",
+ "board",
+ "iW-G30-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/board.xml b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/board.xml
new file mode 100644
index 000000000..d985c2d41
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/board.xml
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G30-SOM Image
+
+
+
+
+ 2.C
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 4EG-1-I SOM, 2GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1GB FPGA DDR4
+
+
+
+
+
+
+
+ FPGA DDR4 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/iW-G30-SOM.png b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/iW-G30-SOM.png
new file mode 100644
index 000000000..60b790b41
Binary files /dev/null and b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/iW-G30-SOM.png differ
diff --git a/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/part0_pins.xml b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/part0_pins.xml
new file mode 100644
index 000000000..8b9794d05
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/part0_pins.xml
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
+
diff --git a/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/preset.xml b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/preset.xml
new file mode 100644
index 000000000..f98d88970
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
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+
+
+
+
+
+
+
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+
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+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/xitem.json b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/xitem.json
new file mode 100644
index 000000000..5cbc28f97
--- /dev/null
+++ b/boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G30M-C4EG-4E002G-E008G-BID",
+ "display": "iW-G30M-C4EG-4E002G-E008G-BID",
+ "revision": "2.C",
+ "description": "Zynq UltraScale+ MPSoC 4EG-1-I SOM, 2GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu7-zu5-zu4-zynq-ultrascale-mpsocsom",
+ "logo": "iW-G30-SOM.png",
+ "search-keywords": [
+ "iW-G30M-C4EG-4E002G-E008G-BID",
+ "iwavesystems.com",
+ "board",
+ "iW-G30-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/board.xml b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/board.xml
new file mode 100644
index 000000000..0a42a7422
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/board.xml
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G30-SOM Image
+
+
+
+
+ 2.D
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 5EV-1-I SOM, 2GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1GB FPGA DDR4
+
+
+
+
+
+
+
+ FPGA DDR4 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/iW-G30-SOM.png b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/iW-G30-SOM.png
new file mode 100644
index 000000000..60b790b41
Binary files /dev/null and b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/iW-G30-SOM.png differ
diff --git a/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/part0_pins.xml b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/part0_pins.xml
new file mode 100644
index 000000000..802462498
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/part0_pins.xml
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/preset.xml b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/preset.xml
new file mode 100644
index 000000000..9c2df3852
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/xitem.json b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/xitem.json
new file mode 100644
index 000000000..f2197cfd2
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G30M-C5EV-4E002G-E008G-BID",
+ "display": "iW-G30M-C5EV-4E002G-E008G-BID",
+ "revision": "2.D",
+ "description": "Zynq UltraScale+ MPSoC 5EV-1-I SOM, 2GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu7-zu5-zu4-zynq-ultrascale-mpsocsom",
+ "logo": "iW-G30-SOM.png",
+ "search-keywords": [
+ "iW-G30M-C5EV-4E002G-E008G-BID",
+ "iwavesystems.com",
+ "board",
+ "iW-G30-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/board.xml b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/board.xml
new file mode 100644
index 000000000..06d91227a
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/board.xml
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G30-SOM Image
+
+
+
+
+ 2.5
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 5EV-1-I SOM, 4GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1GB FPGA DDR4
+
+
+
+
+
+
+
+ FPGA DDR4 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/iW-G30-SOM.png b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/iW-G30-SOM.png
new file mode 100644
index 000000000..60b790b41
Binary files /dev/null and b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/iW-G30-SOM.png differ
diff --git a/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/part0_pins.xml b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/part0_pins.xml
new file mode 100644
index 000000000..9408644a0
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/part0_pins.xml
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
diff --git a/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/preset.xml b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/preset.xml
new file mode 100644
index 000000000..6bb2eff75
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
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+
+
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+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/xitem.json b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/xitem.json
new file mode 100644
index 000000000..11b767290
--- /dev/null
+++ b/boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G30M-C5EV-4E004G-E008G-LIA",
+ "display": "iW-G30M-C5EV-4E004G-E008G-LIA",
+ "revision": "2.5",
+ "description": "Zynq UltraScale+ MPSoC 5EV-1-I SOM, 4GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu7-zu5-zu4-zynq-ultrascale-mpsocsom",
+ "logo": "iW-G30-SOM.png",
+ "search-keywords": [
+ "iW-G30M-C5EV-4E004G-E008G-LIA",
+ "iwavesystems.com",
+ "board",
+ "iW-G30-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/board.xml b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/board.xml
new file mode 100644
index 000000000..ff2d89302
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/board.xml
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G30-SOM Image
+
+
+
+
+ 2.1
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 7CG-1-I SOM, 4GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
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+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 1GB FPGA DDR4
+
+
+
+
+
+
+
+ FPGA DDR4 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/iW-G30-SOM.png b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/iW-G30-SOM.png
new file mode 100644
index 000000000..60b790b41
Binary files /dev/null and b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/iW-G30-SOM.png differ
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/part0_pins.xml b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/part0_pins.xml
new file mode 100644
index 000000000..43cd3b762
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/part0_pins.xml
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/preset.xml b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/preset.xml
new file mode 100644
index 000000000..da5691d83
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
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+
+
+
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+
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+
+
+
+
+
+
+
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+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
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+
+
+
+
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+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
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+
+
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+
+
+
+
+
+
+
+
+
+
+
+
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+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/xitem.json b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/xitem.json
new file mode 100644
index 000000000..34aff1f96
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-lia/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G30M-C7CG-4E004G-E008G-LIA",
+ "display": "iW-G30M-C7CG-4E004G-E008G-LIA",
+ "revision": "2.1",
+ "description": "Zynq UltraScale+ MPSoC 7CG-1-I SOM, 4GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu7-zu5-zu4-zynq-ultrascale-mpsocsom",
+ "logo": "iW-G30-SOM.png",
+ "search-keywords": [
+ "iW-G30M-C7CG-4E004G-E008G-LIA",
+ "iwavesystems.com",
+ "board",
+ "iW-G30-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/board.xml b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/board.xml
new file mode 100644
index 000000000..93d7addd6
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/board.xml
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G30-SOM Image
+
+
+
+
+ 2.H
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 7CG-1-I SOM, 4GB PS DDR4, 2 GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ 2GB FPGA DDR4
+
+
+
+
+
+
+
+ FPGA DDR4 Reference Clock
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/iW-G30-SOM.png b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/iW-G30-SOM.png
new file mode 100644
index 000000000..60b790b41
Binary files /dev/null and b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/iW-G30-SOM.png differ
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/part0_pins.xml b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/part0_pins.xml
new file mode 100644
index 000000000..e134cbc1d
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/part0_pins.xml
@@ -0,0 +1,79 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/preset.xml b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/preset.xml
new file mode 100644
index 000000000..718518f77
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/xitem.json b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/xitem.json
new file mode 100644
index 000000000..6e3aa452a
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7cg-4e004g-e008g-liy/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G30M-C7CG-4E004G-E008G-LIY",
+ "display": "iW-G30M-C7CG-4E004G-E008G-LIY",
+ "revision": "2.H",
+ "description": "Zynq UltraScale+ MPSoC 7CG-1-I SOM, 4GB PS DDR4, 2 GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu7-zu5-zu4-zynq-ultrascale-mpsocsom",
+ "logo": "iW-G30-SOM.png",
+ "search-keywords": [
+ "iW-G30M-C7CG-4E004G-E008G-LIY",
+ "iwavesystems.com",
+ "board",
+ "iW-G30-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/board.xml b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/board.xml
new file mode 100644
index 000000000..c21ffb364
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/board.xml
@@ -0,0 +1,219 @@
+
+
+
+
+
+
+
+
+
+
+
+
+ iW-G30-SOM Image
+
+
+
+
+ 2.B
+
+
+ 1.0
+
+ Zynq UltraScale+ MPSoC 7EV-1-I SOM, 4GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash
+
+
+
+
+
+
+
+
+
+
+ FPGA part on the board
+
+
+
+
+
+
+
+
+ DDR4 board interface, it can use DDR4 controller IP for connection.
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
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+ 1GB FPGA DDR4
+
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+
+ FPGA DDR4 Reference Clock
+
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\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/iW-G30-SOM.png b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/iW-G30-SOM.png
new file mode 100644
index 000000000..60b790b41
Binary files /dev/null and b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/iW-G30-SOM.png differ
diff --git a/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/part0_pins.xml b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/part0_pins.xml
new file mode 100644
index 000000000..36b9ac7ef
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/part0_pins.xml
@@ -0,0 +1,79 @@
+
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+
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diff --git a/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/preset.xml b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/preset.xml
new file mode 100644
index 000000000..79a595daa
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/preset.xml
@@ -0,0 +1,182 @@
+
+
+
+
+
+
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+
\ No newline at end of file
diff --git a/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/xitem.json b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/xitem.json
new file mode 100644
index 000000000..06d03e2be
--- /dev/null
+++ b/boards/iWave/iw-g30m-c7ev-4e004g-e008g-lia/1.0/xitem.json
@@ -0,0 +1,36 @@
+{
+ "config": {
+ "items": [
+ {
+ "infra": {
+ "name": "iW-G30M-C7EV-4E004G-E008G-LIA",
+ "display": "iW-G30M-C7EV-4E004G-E008G-LIA",
+ "revision": "2.B",
+ "description": "Zynq UltraScale+ MPSoC 7EV-1-I SOM, 4GB PS DDR4, 1 GB FPGA DDR4, 8GB eMMC Flash",
+ "company": "iwavesystems.com",
+ "company_display": "iWave Systems Technologies",
+ "author": "iwavesystems.com",
+ "contributors": [
+ {
+ "group": "iWave Systems Technologies",
+ "url": "https://www.iwavesystems.com/"
+ }
+ ],
+ "category": "System on Module",
+ "website": "https://www.iwavesystems.com/product/zu7-zu5-zu4-zynq-ultrascale-mpsocsom",
+ "logo": "iW-G30-SOM.png",
+ "search-keywords": [
+ "iW-G30M-C7EV-4E004G-E008G-LIA",
+ "iwavesystems.com",
+ "board",
+ "iW-G30-SOM",
+ "System on Module",
+ "SOM"
+ ]
+ }
+ }
+ ]
+ },
+ "_major": 1,
+ "_minor": 0
+}
\ No newline at end of file
diff --git a/catalog/boards_ta.json b/catalog/boards_ta.json
new file mode 100644
index 000000000..06218bb0e
--- /dev/null
+++ b/catalog/boards_ta.json
@@ -0,0 +1,9 @@
+{
+"items": [
+ {
+ "name": "tenzing",
+ "repo_path": "Xilinx/tenzing",
+ "Exclude_from_REL": "true"
+ }
+]
+}
diff --git a/catalog/vivado_master.json b/catalog/vivado_2024.2.json
similarity index 73%
rename from catalog/vivado_master.json
rename to catalog/vivado_2024.2.json
index 9a78b3262..b5f2aa943 100644
--- a/catalog/vivado_master.json
+++ b/catalog/vivado_2024.2.json
@@ -6099,6 +6099,2381 @@
"metadata_file": "xitem.json"
},
"company": "OpalKelly.com"
+ },
+ {
+ "name": "XEM8350-KU115",
+ "display": "XEM8350-KU115 Integration Platform",
+ "latest_revision": "1.0",
+ "commit_id": "5849822c189e7f5e03e1efb5bcd3fe13aa68c859",
+ "revisions": [
+ {
+ "revision": "1.0",
+ "commit_id": "5849822c189e7f5e03e1efb5bcd3fe13aa68c859",
+ "date": "25-10-2022:22:16:54",
+ "history": "Added board XEM8350-KU115 Integration Platform v1.0"
+ }
+ ],
+ "config": {
+ "root": "boards/OpalKelly/XEM8350-KU115/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "opalkelly.com"
+ },
+ {
+ "name": "admpa100_2ms",
+ "display": "ADM-PA100/2MS",
+ "latest_revision": "1.0",
+ "commit_id": "715cd7e8c23361f95bd4a25d54903daff010c7ab",
+ "revisions": [
+ {
+ "revision": "1.0",
+ "commit_id": "715cd7e8c23361f95bd4a25d54903daff010c7ab",
+ "date": "27-02-2023:15:21:09",
+ "history": "Added board ADM-PA100/2MS v1.0"
+ }
+ ],
+ "config": {
+ "root": "boards/AlphaData/admpa100_2ms/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "alpha-data.com"
+ },
+ {
+ "name": "admpa101_2ms",
+ "display": "ADM-PA101/2MS",
+ "latest_revision": "1.1",
+ "commit_id": "715cd7e8c23361f95bd4a25d54903daff010c7ab",
+ "revisions": [
+ {
+ "revision": "1.1",
+ "commit_id": "715cd7e8c23361f95bd4a25d54903daff010c7ab",
+ "date": "27-02-2023:15:21:09",
+ "history": "Added board ADM-PA101/2MS v1.1"
+ }
+ ],
+ "config": {
+ "root": "boards/AlphaData/admpa101_2ms/1.1",
+ "metadata_file": "xitem.json"
+ },
+ "company": "alpha-data.com"
+ },
+ {
+ "name": "iW-G35M-11EG-4E008G-E008G-BIA",
+ "display": "iW-G35M-11EG-4E008G-E008G-BIA",
+ "latest_revision": "1.9",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.9",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-11EG-4E008G-E008G-BIA v1.9"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-11EG-4E008G-E008G-BIA/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E004G-E008G-BEF",
+ "display": "iW-G35M-19EG-4E004G-E008G-BEF",
+ "latest_revision": "1.7",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.7",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E004G-E008G-BEF v1.7"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E004G-E008G-BEF/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E004G-E008G-BIG",
+ "display": "iW-G35M-19EG-4E004G-E008G-BIG",
+ "latest_revision": "1.6",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.6",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E004G-E008G-BIG v1.6"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E004G-E008G-BIG/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E004G-E008G-BII",
+ "display": "iW-G35M-19EG-4E004G-E008G-BII",
+ "latest_revision": "1.C",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.C",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E004G-E008G-BII v1.C"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E004G-E008G-BII/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E004G-E008G-BIJ",
+ "display": "iW-G35M-19EG-4E004G-E008G-BIJ",
+ "latest_revision": "1.D",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.D",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E004G-E008G-BIJ v1.D"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E004G-E008G-BIJ/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E004G-E008G-LIE",
+ "display": "iW-G35M-19EG-4E004G-E008G-LIE",
+ "latest_revision": "1.4",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.4",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E004G-E008G-LIE v1.4"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E004G-E008G-LIE/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E004G-E008G-LIH",
+ "display": "iW-G35M-19EG-4E004G-E008G-LIH",
+ "latest_revision": "1.8",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.8",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E004G-E008G-LIH v1.8"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E004G-E008G-LIH/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E004G-E128G-BIA",
+ "display": "iW-G35M-19EG-4E004G-E128G-BIA",
+ "latest_revision": "1.3",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.3",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E004G-E128G-BIA v1.3"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E004G-E128G-BIA/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E008G-E008G-BIE",
+ "display": "iW-G35M-19EG-4E008G-E008G-BIE",
+ "latest_revision": "1.A",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.A",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E008G-E008G-BIE v1.A"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E008G-E008G-BIE/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E008G-E008G-BIJ",
+ "display": "iW-G35M-19EG-4E008G-E008G-BIJ",
+ "latest_revision": "1.E",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.E",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E008G-E008G-BIJ v1.E"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E008G-E008G-BIJ/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G35M-19EG-4E008G-E016G-BIA",
+ "display": "iW-G35M-19EG-4E008G-E016G-BIA",
+ "latest_revision": "1.B",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "1.B",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G35M-19EG-4E008G-E016G-BIA v1.B"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iW-G35M-19EG-4E008G-E016G-BIA/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G30M-C4CG-4E002G-E008G-LIA",
+ "display": "iW-G30M-C4CG-4E002G-E008G-LIA",
+ "latest_revision": "2.4",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "2.4",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G30M-C4CG-4E002G-E008G-LIA v2.4"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iw-g30m-c4cg-4e002g-e008g-lia/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G30M-C4EG-4E002G-E008G-BID",
+ "display": "iW-G30M-C4EG-4E002G-E008G-BID",
+ "latest_revision": "2.C",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "2.C",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G30M-C4EG-4E002G-E008G-BID v2.C"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iw-g30m-c4eg-4e002g-e008g-bid/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G30M-C5EV-4E002G-E008G-BID",
+ "display": "iW-G30M-C5EV-4E002G-E008G-BID",
+ "latest_revision": "2.D",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "2.D",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G30M-C5EV-4E002G-E008G-BID v2.D"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iw-g30m-c5ev-4e002g-e008g-bid/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G30M-C5EV-4E004G-E008G-LIA",
+ "display": "iW-G30M-C5EV-4E004G-E008G-LIA",
+ "latest_revision": "2.5",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
+ "revision": "2.5",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "date": "17-05-2023:14:41:14",
+ "history": "Added board iW-G30M-C5EV-4E004G-E008G-LIA v2.5"
+ }
+ ],
+ "config": {
+ "root": "boards/iWave/iw-g30m-c5ev-4e004g-e008g-lia/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "iwavesystems.com"
+ },
+ {
+ "name": "iW-G30M-C7CG-4E004G-E008G-LIA",
+ "display": "iW-G30M-C7CG-4E004G-E008G-LIA",
+ "latest_revision": "2.1",
+ "commit_id": "f590183e7d40efb867a3fa3a19ad0c3a94b6e458",
+ "revisions": [
+ {
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+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU111 Evaluation Platform v1.3"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu111/1.3",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu111",
+ "display": "Zynq UltraScale+ ZCU111 Evaluation Platform",
+ "latest_revision": "1.4",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "1.4",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU111 Evaluation Platform v1.4"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu111/1.4",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu1275",
+ "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit",
+ "latest_revision": "1.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "1.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Xilinx Zynq UltraScale+ RFSoC ZCU1275 Characterization Kit v1.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu1275/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu1285",
+ "display": "Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit",
+ "latest_revision": "1.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "1.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Xilinx Zynq UltraScale+ RFSoC ZCU1285 Characterization Kit v1.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu1285/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu208",
+ "display": "Zynq UltraScale+ ZCU208 Evaluation Platform",
+ "latest_revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU208 Evaluation Platform v2.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu208/production/2.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu208ld",
+ "display": "Zynq UltraScale+ ZCU208-LD Evaluation Platform",
+ "latest_revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU208-LD Evaluation Platform v2.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu208ld/production/2.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu216",
+ "display": "Zynq UltraScale+ ZCU216 Evaluation Platform",
+ "latest_revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU216 Evaluation Platform v2.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu216/production/2.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu216ld",
+ "display": "Zynq UltraScale+ ZCU216-LD Evaluation Platform",
+ "latest_revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU216-LD Evaluation Platform v2.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu216ld/production/2.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu670",
+ "display": "Zynq UltraScale+ ZCU670 Evaluation Platform",
+ "latest_revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "2.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU670 Evaluation Platform v2.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu670/2.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
+ },
+ {
+ "name": "zcu670ld",
+ "display": "Zynq UltraScale+ ZCU670-LD Evaluation Platform",
+ "latest_revision": "1.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "revisions": [
+ {
+ "revision": "1.0",
+ "commit_id": "a1053dbd205bc0ba03a561ec8dead084554c7494",
+ "date": "25-10-2024:11:37:17",
+ "history": "Added board Zynq UltraScale+ ZCU670-LD Evaluation Platform v1.0"
+ }
+ ],
+ "config": {
+ "root": "boards/Xilinx/zcu670ld/1.0",
+ "metadata_file": "xitem.json"
+ },
+ "company": "xilinx.com"
}
],
"categories": [
diff --git a/catalog/xstore.json b/catalog/xstore.json
index 2e63ade0d..a356ff16b 100644
--- a/catalog/xstore.json
+++ b/catalog/xstore.json
@@ -89,6 +89,31 @@
"xitem_catalogue_file": "catalog/vivado_2022.1.json",
"version": "2022.1",
"remote_repo_branch_to_sync": "2022.1"
+ },
+ {
+ "xitem_catalogue_file": "catalog/vivado_2022.2.json",
+ "version": "2022.2",
+ "remote_repo_branch_to_sync": "2022.2"
+ },
+ {
+ "xitem_catalogue_file": "catalog/vivado_2023.1.json",
+ "version": "2023.1",
+ "remote_repo_branch_to_sync": "2023.1"
+ },
+ {
+ "xitem_catalogue_file": "catalog/vivado_2023.2.json",
+ "version": "2023.2",
+ "remote_repo_branch_to_sync": "2023.2"
+ },
+ {
+ "xitem_catalogue_file": "catalog/vivado_2024.1.json",
+ "version": "2024.1",
+ "remote_repo_branch_to_sync": "2024.1"
+ },
+ {
+ "xitem_catalogue_file": "catalog/vivado_2024.2.json",
+ "version": "2024.2",
+ "remote_repo_branch_to_sync": "2024.2"
}
]
}