From 020cd984f40a51b98f8790219c41663c109e3077 Mon Sep 17 00:00:00 2001 From: jhieb Date: Fri, 14 Nov 2025 13:57:55 -0700 Subject: [PATCH 1/2] Change the pci capability size to be DWORD aligned. --- tlm-modules/pf-config.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/tlm-modules/pf-config.h b/tlm-modules/pf-config.h index 7586975..ca5e266 100644 --- a/tlm-modules/pf-config.h +++ b/tlm-modules/pf-config.h @@ -105,7 +105,7 @@ class PCIExpressCapability: public PCICapability // hardwired to '0' as according to PCI Express Base // specification. // - PCIExpressCapSize = PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 + 0x8, + PCIExpressCapSize = PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 + 0xA, }; PCIExpressCapability(): From c4a9deca2d46abaa77f99ea632c56a9ce9bd8e3c Mon Sep 17 00:00:00 2001 From: jhieb Date: Wed, 19 Nov 2025 13:25:00 -0700 Subject: [PATCH 2/2] Add assert for if capability pointers aren't dword aligned. --- tlm-modules/pf-config.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tlm-modules/pf-config.h b/tlm-modules/pf-config.h index ca5e266..f4f58ed 100644 --- a/tlm-modules/pf-config.h +++ b/tlm-modules/pf-config.h @@ -244,6 +244,7 @@ class PhysFuncConfig { if (m_pciCapTail == 0) { m_pciCapTail = PCI_CONFIG_SIZE - cap_size; + assert((m_pciCapTail & 0x3) == 0); // Dword aligned. SetNextCapPtr(m_pciCapTail); // // Hardwire status 'Capabilities List' to 1 @@ -253,6 +254,7 @@ class PhysFuncConfig uint32_t nextCapPtr = m_pciCapTail + 1; m_pciCapTail -= cap_size; + assert((m_pciCapTail & 0x3) == 0); // Dword aligned. m_config[nextCapPtr] = m_pciCapTail; } memcpy(reinterpret_cast(&m_config[m_pciCapTail]),